coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: soc/amd/morgana/data_fabric: Add register bitslice struct
by Fred Reitberger (Code Review) 03 Nov '22

03 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69071 ) Change subject: soc/amd/morgana/data_fabric: Add register bitslice struct ...................................................................... soc/amd/morgana/data_fabric: Add register bitslice struct Add structs to define the data_fabric register bitfields, updated per morgana ppr #57396, rev 1.52 Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/morgana/include/soc/data_fabric.h 1 file changed, 46 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/morgana/include/soc/data_fabric.h b/src/soc/amd/morgana/include/soc/data_fabric.h index c210e47..203ca1c 100644 --- a/src/soc/amd/morgana/include/soc/data_fabric.h +++ b/src/soc/amd/morgana/include/soc/data_fabric.h @@ -8,10 +8,36 @@ #include <types.h> /* SoC-specific bits in D18F0_MMIO_CTRL0 */ -#define DF_MMIO_NP BIT(16) +#define DF_MMIO_NP BIT(3) -#define IOMS0_FABRIC_ID 9 +#define IOMS0_FABRIC_ID 14 #define NUM_NB_MMIO_REGS 8 +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 1; /* [ 2.. 2] */ + uint32_t np : 1; /* [ 3.. 3] */ + uint32_t : 12; /* [15.. 4] */ + uint32_t fabric_id : 6; /* [21..16] */ + uint32_t : 10; /* [31..22] */ + }; + uint32_t raw; +}; + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t reg_num : 10; /* [10.. 1] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + #endif /* AMD_MORGANA_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44 Gerrit-Change-Number: 69071 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: drivers/i2c/generic: Print error when using _CRS and PowerResource
by Tim Van Patten (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Tim Crawford, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Martin Roth, Karthik Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60174 ) Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 Gerrit-Change-Number: 60174 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 19:49:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino/data_fabric: Add register bitslice struct
by Fred Reitberger (Code Review) 03 Nov '22

03 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69070 ) Change subject: soc/amd/mendocino/data_fabric: Add register bitslice struct ...................................................................... soc/amd/mendocino/data_fabric: Add register bitslice struct Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/mendocino/include/soc/data_fabric.h 1 file changed, 43 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index a73bc42..a1a1f4e 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -12,4 +12,32 @@ #define NUM_NB_MMIO_REGS 8 +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 2; /* [ 3.. 2] */ + uint32_t fabric_id : 4; /* [ 7.. 4] */ + uint32_t : 8; /* [15.. 8] */ + uint32_t np : 1; /* [16..16] */ + uint32_t : 15; /* [31..17] */ + }; + uint32_t raw; +}; + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t : 1; /* [ 1.. 1] */ + uint32_t reg_num : 9; /* [10.. 2] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + + #endif /* AMD_MENDOCINO_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 Gerrit-Change-Number: 69070 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/picasso/data_fabric: Add register bitslice struct
by Fred Reitberger (Code Review) 03 Nov '22

03 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69069 ) Change subject: soc/amd/picasso/data_fabric: Add register bitslice struct ...................................................................... soc/amd/picasso/data_fabric: Add register bitslice struct Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69069 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/data_fabric.h 1 file changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 054ca89..f71abe0 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -14,6 +14,33 @@ #define NUM_NB_MMIO_REGS 8 +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 2; /* [ 3.. 2] */ + uint32_t fabric_id : 8; /* [11.. 4] */ + uint32_t np : 1; /* [12..12] */ + uint32_t : 19; /* [31..13] */ + }; + uint32_t raw; +}; + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t : 1; /* [ 1.. 1] */ + uint32_t reg_num : 9; /* [10.. 2] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + + #define D18F0_VGAEN 0x80 #define VGA_ADDR_ENABLE BIT(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/69069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9 Gerrit-Change-Number: 69069 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/cezanne/data_fabric: Add register bitslice struct
by Fred Reitberger (Code Review) 03 Nov '22

03 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69068 ) Change subject: soc/amd/cezanne/data_fabric: Add register bitslice struct ...................................................................... soc/amd/cezanne/data_fabric: Add register bitslice struct Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/69068 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/include/soc/data_fabric.h 1 file changed, 43 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 1808df3..0a89971 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -12,4 +12,31 @@ #define NUM_NB_MMIO_REGS 8 +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 2; /* [ 3.. 2] */ + uint32_t fabric_id : 10; /* [13.. 4] */ + uint32_t : 2; /* [15..14] */ + uint32_t np : 1; /* [16..16] */ + uint32_t : 15; /* [31..17] */ + }; + uint32_t raw; +}; + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t : 1; /* [ 1.. 1] */ + uint32_t reg_num : 9; /* [10.. 2] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + #endif /* AMD_CEZANNE_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff Gerrit-Change-Number: 69068 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common
by Fred Reitberger (Code Review) 03 Nov '22

03 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69067 ) Change subject: soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common ...................................................................... soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common The data_fabric_set_mmio_np function is effectively identical, so move it to common code. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/data_fabric.c M src/soc/amd/cezanne/include/soc/data_fabric.h M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/data_fabric.c M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/data_fabric.c M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/morgana/chip.c M src/soc/amd/morgana/data_fabric.c M src/soc/amd/morgana/include/soc/data_fabric.h M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/data_fabric.c M src/soc/amd/picasso/include/soc/data_fabric.h 17 files changed, 111 insertions(+), 480 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index e4aa704..efef2f1 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c index 5dc0f99..6a34a07 100644 --- a/src/soc/amd/cezanne/data_fabric.c +++ b/src/soc/amd/cezanne/data_fabric.c @@ -1,102 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 27444be..1808df3 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -12,6 +12,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_CEZANNE_DATA_FABRIC_H */ diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 0fcee36..f1a067f 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -2,7 +2,9 @@ #include <amdblocks/data_fabric.h> #include <amdblocks/pci_devs.h> +#include <arch/hpet.h> #include <console/console.h> +#include <cpu/x86/lapic_def.h> #include <device/pci_ops.h> #include <soc/data_fabric.h> #include <soc/pci_devs.h> @@ -82,3 +84,89 @@ } return -1; } + +void data_fabric_set_mmio_np(void) +{ + /* + * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. + * + * AGESA has already programmed the NB MMIO routing, however nothing + * is yet marked as non-posted. + * + * If there exists an overlapping routing base/limit pair, trim its + * base or limit to avoid the new NP region. If any pair exists + * completely within HPET-LAPIC range, remove it. If any pair surrounds + * HPET-LAPIC, it must be split into two regions. + * + * TODO(b/156296146): Remove the settings from AGESA and allow coreboot + * to own everything. If not practical, consider erasing all settings + * and have coreboot reprogram them. At that time, make the source + * below more flexible. + * * Note that the code relies on the granularity of the HPET and + * LAPIC addresses being sufficiently large that the shifted limits + * +/-1 are always equivalent to the non-shifted values +/-1. + */ + + unsigned int i; + int reg; + uint32_t base, limit, ctrl; + const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; + + data_fabric_print_mmio_conf(); + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + /* Adjust all registers that overlap */ + ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) + continue; /* not enabled */ + + base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); + limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); + + if (base > np_top || limit < np_bot) + continue; /* no overlap at all */ + + if (base >= np_bot && limit <= np_top) { + data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ + continue; + } + + if (base < np_bot && limit > np_top) { + /* Split the configured region */ + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + reg = data_fabric_find_unused_mmio_reg(); + if (reg < 0) { + /* Although a pair could be freed later, this condition is + * very unusual and deserves analysis. Flag an error and + * leave the topmost part unconfigured. */ + printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); + continue; + } + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); + continue; + } + + /* If still here, adjust only the base or limit */ + if (base <= np_bot) + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + else + data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); + } + + reg = data_fabric_find_unused_mmio_reg(); + if (reg < 0) { + printk(BIOS_ERR, "cannot configure region as NP\n"); + return; + } + + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), + (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP + | DF_MMIO_WE | DF_MMIO_RE); + + data_fabric_print_mmio_conf(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 604c24e..5cc7f48 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -45,5 +45,6 @@ void data_fabric_print_mmio_conf(void); void data_fabric_disable_mmio_reg(unsigned int reg); int data_fabric_find_unused_mmio_reg(void); +void data_fabric_set_mmio_np(void); #endif /* AMD_BLOCK_DATA_FABRIC_H */ diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index b0b90ee..9e9ee9e 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -2,13 +2,13 @@ /* TODO: Update for Glinda */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/glinda/data_fabric.c b/src/soc/amd/glinda/data_fabric.c index 822d5a9..3bc0b6d 100644 --- a/src/soc/amd/glinda/data_fabric.c +++ b/src/soc/amd/glinda/data_fabric.c @@ -3,103 +3,10 @@ /* TODO: Update for Glinda */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index 4abbb3d..0bb9561 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -14,6 +14,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_GLINDA_DATA_FABRIC_H */ diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 99e33ce..83a485f 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -2,13 +2,13 @@ /* TODO: Check if this is still correct */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/mendocino/data_fabric.c b/src/soc/amd/mendocino/data_fabric.c index f1ee4df..2569da8 100644 --- a/src/soc/amd/mendocino/data_fabric.c +++ b/src/soc/amd/mendocino/data_fabric.c @@ -1,105 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index c7727bb..a73bc42 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -12,6 +12,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_MENDOCINO_DATA_FABRIC_H */ diff --git a/src/soc/amd/morgana/chip.c b/src/soc/amd/morgana/chip.c index 086211e..13d2638 100644 --- a/src/soc/amd/morgana/chip.c +++ b/src/soc/amd/morgana/chip.c @@ -2,13 +2,13 @@ /* TODO: Update for Morgana */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/morgana/data_fabric.c b/src/soc/amd/morgana/data_fabric.c index 2f72e3a..6c02d21 100644 --- a/src/soc/amd/morgana/data_fabric.c +++ b/src/soc/amd/morgana/data_fabric.c @@ -3,103 +3,10 @@ /* TODO: Update for Morgana */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/morgana/include/soc/data_fabric.h b/src/soc/amd/morgana/include/soc/data_fabric.h index eba4cd8..c210e47 100644 --- a/src/soc/amd/morgana/include/soc/data_fabric.h +++ b/src/soc/amd/morgana/include/soc/data_fabric.h @@ -14,6 +14,4 @@ #define NUM_NB_MMIO_REGS 8 -void data_fabric_set_mmio_np(void); - #endif /* AMD_MORGANA_DATA_FABRIC_H */ diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 37e62e2..fc30af9 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/data_fabric.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <drivers/i2c/designware/dw_i2c.h> #include <soc/acpi.h> #include <soc/cpu.h> -#include <soc/data_fabric.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index ddc280b..a251158 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -1,102 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi_device.h> -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> #include <console/console.h> -#include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/data_fabric.h> -#include <soc/iomap.h> -#include <types.h> - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "cannot configure region as NP\n"); - return; - } - - data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); - - data_fabric_print_mmio_conf(); -} static const char *data_fabric_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 5533433..054ca89 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -49,6 +49,4 @@ #define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ + D18F0_DRAM_LIMIT0) -void data_fabric_set_mmio_np(void); - #endif /* AMD_PICASSO_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Gerrit-Change-Number: 69067 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: cpu/x86: Set up cpu_info storage using MSR
by Marc Jones (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Arthur Heymans. Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68913 ) Change subject: cpu/x86: Set up cpu_info storage using MSR ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38d3c84ef757c0b322ec0d387f57043147cb447 Gerrit-Change-Number: 68913 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Nov 2022 19:46:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: soc/amd/*/data_fabric: Use common device ops
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69174 ) Change subject: soc/amd/*/data_fabric: Use common device ops ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf Gerrit-Change-Number: 69174 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 19:44:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/common/data_fabric: Make common device ops
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69173 ) Change subject: soc/amd/common/data_fabric: Make common device ops ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: this could be squashed with the next patch, but either way works -- To view, visit https://review.coreboot.org/c/coreboot/+/69173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12053389a12081ddd81912a647bb532b31062093 Gerrit-Change-Number: 69173 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 19:43:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/amd/mendocino/data_fabric.c: Make function more generic
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69172 ) Change subject: soc/amd/mendocino/data_fabric.c: Make function more generic ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d Gerrit-Change-Number: 69172 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 19:42:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022