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Change subject: mb/google/nissa/var/craask: Modify DPTF related settings
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68523/comment/2476abf5_fa6ba2e3
PS3, Line 154: .time_window_min = 28 * MSECS_PER_SEC,
> Update patchset 6 to set pl2.time_window_min/max to 1 * MSECS_PER_SEC.
Thanks Tyler. Vidya could you please confirm whether this is correct?
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Change subject: mb/google/nissa/var/craask: Modify DPTF related settings
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68523/comment/80640325_e8cab8fe
PS3, Line 154: .time_window_min = 28 * MSECS_PER_SEC,
> Should this really be 0? That seems strange. I thought it would make more sense to round to 1 ms? […]
Update patchset 6 to set pl2.time_window_min/max to 1 * MSECS_PER_SEC.
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Change subject: mb/google: Probe p-sensor only for selected variants
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69191/comment/54c17933_d0aa597b
PS2, Line 12:
Can you mention why this is necessary - we want to be able to select the legacy driver per-variant.
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Change subject: drivers/i2c/sx9324: Add support for Linux's SX9324 driver
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69192/comment/894b78e6_06da4634
PS3, Line 16:
I think this could do with slightly more explanation. I.e. we want a single firmware build which can work with both kernel drivers by specifying both sets of properties, which is useful during the transition phase. And maybe mention the kernel versions in which the old driver was removed and the new driver added.
https://review.coreboot.org/c/coreboot/+/69192/comment/630bd5c7_ec2ef985
PS3, Line 18: TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch
This is not true, since the new properties will be added to the ACPI tables with zero values.
File src/drivers/i2c/sx9324/Kconfig:
https://review.coreboot.org/c/coreboot/+/69192/comment/13a3ef32_ce982c76
PS3, Line 13: Board may use the legacy sx932x linux driver.
Could you add a few more details, similar to what I suggested for the commit message?
File src/drivers/i2c/sx9324/sx9324.c:
https://review.coreboot.org/c/coreboot/+/69192/comment/1996fe41_3bbeeff7
PS3, Line 72: cs_idle_sleep
int_comp_resistor
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Hello build bot (Jenkins), Tarun Tuli, Jason Nien, Reka Norman, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: drivers/i2c/sx9324: Add support for Linux's SX9324 driver
......................................................................
drivers/i2c/sx9324: Add support for Linux's SX9324 driver
SX9324 driver is updated per Linux's documentation found at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Doc…
Supporting logic for the deprecated SX932x driver is hence guarded by
DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
This patch by itself does not introduce functional changes to any board.
BUG=b:242662878
TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy
SX932x driver are identical w/ and w/o this patch
Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b
Signed-off-by: Victor Ding <victording(a)google.com>
---
M src/drivers/i2c/sx9324/Kconfig
M src/drivers/i2c/sx9324/chip.h
M src/drivers/i2c/sx9324/registers.h
M src/drivers/i2c/sx9324/sx9324.c
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/dedede/Kconfig.name
M src/mainboard/google/zork/Kconfig.name
7 files changed, 201 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69192/4
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Change subject: mb/google/brask: Disable PCH USB2 phy power gating for moli
......................................................................
mb/google/brask: Disable PCH USB2 phy power gating for moli
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for moli board. Please refer Intel doc#723158 for
more information.
BUG=b:257373742
TEST=Verify the build for moli board
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: I457d410501be996f0f29ec622e1829f1581c4970
---
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Change subject: mb/google/brask: Disable PCH USB2 phy power gating for moli
......................................................................
Patch Set 4: Code-Review+1
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Hello build bot (Jenkins), Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Eric Peers, Tim Van Patten, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held,
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Change subject: common/acpi/dptc: Implement DTTS Proposal
......................................................................
common/acpi/dptc: Implement DTTS Proposal
DTTS indicated Dynamic Thermal Table Switching.
The proposal would like to develop the schematic
for switching 6 thermal table by lid status,
machine body mode and temperature.
After entering the OS, the thermal table would be table A.
If the “Motion” or “Lid-status changement” is detected.
The thermal table would switch to laptop mode or lid-close
mode. Once the higher environment temperatures are detected,
the thermal table would switch to the corresponding power
throttle table(B, D or F). Based on these table switching
mechanisms, no matter how the end-user uses Chromebook,
they could enjoy more humanized thermal designs.
Release Over Over Release
Temp. Temp. Temp. Temp.
--------------------------------------------------------
Desktop mode Table A Table B 50C 45C
Lid open (Default)
--------------------------------------------------------
Desktop mode Table C Table D 55C 50C
Lid close
--------------------------------------------------------
Laptop mode Table E Table F 45C 40C
--------------------------------------------------------
On the proposal, the transmission rules are list below:
1. Table A is the default table after booting.
2. A, C, E can switch to each other.
3. B, D, F can switch to each other.
4. A and B, C and D, E and F can switch to each other.
5. Assume Table A is current table. When the temperature
reach 50C, than the table is switched from A to B.
6. Based on 4. The current table is B. When the temperature
is downgrade below 45C, the table is switched form B to A.
7. Based on 4 an 5, the same rule is for C and D, E and F.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622
---
M src/mainboard/google/skyrim/dsdt.asl
A src/mainboard/google/skyrim/variants/winterhold/DTTS.asl
2 files changed, 160 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68471/29
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