coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: Documentation/mb/starlabs: De-deplicate the building instructions
by build bot (Jenkins) (Code Review) 04 Nov '22

04 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68585 ) Change subject: Documentation/mb/starlabs: De-deplicate the building instructions ...................................................................... Patch Set 7: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20301b3041a62eb416ed61a84544ec4e5cc66c1e Gerrit-Change-Number: 68585 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Nov 2022 08:51:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/cper.h: Add CPER Memory Error Section definitions
by Shuming Chu (Shuming) (Code Review) 04 Nov '22

04 Nov '22

Hello Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69198 to look at the new patch set (#2). Change subject: include/cper.h: Add CPER Memory Error Section definitions ...................................................................... include/cper.h: Add CPER Memory Error Section definitions Add Memory Error Section definitions from UEFI Specification rev 2.10 appendix N.2.5. The structure defined here may be used for machine check handling. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b --- M src/include/cper.h 1 file changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69198/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b Gerrit-Change-Number: 69198 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
by build bot (Jenkins) (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68893 ) Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime ...................................................................... Patch Set 6: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162374): https://review.coreboot.org/c/coreboot/+/68893/comment/728d19fd_01f53133 PS6, Line 8: Possible repeated word: 'are' File src/cpu/x86/mp_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162374): https://review.coreboot.org/c/coreboot/+/68893/comment/520ad2f8_6f7d64b4 PS6, Line 490: if (!cpu->enabled) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/68893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f Gerrit-Change-Number: 68893 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 08:40:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/cper.h: Add CPER Memory Error Section definitions
by Shuming Chu (Shuming) (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tim Chu. Hello Tim Chu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69198 to review the following change. Change subject: include/cper.h: Add CPER Memory Error Section definitions ...................................................................... include/cper.h: Add CPER Memory Error Section definitions Add Memory Error Section definitions from UEFI Specification rev 2.10 appendix N.2.5. The structure defined here may be used for machine check handling. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b --- M src/include/cper.h 1 file changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69198/1 diff --git a/src/include/cper.h b/src/include/cper.h index 576e1d8..8eccd0e 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -505,4 +505,38 @@ x86err->validation |= count << I32X64SEC_VALID_CTXNUM_SH; } +/* UEFI Spec, Appendix N.2.5 Memory Error Types */ +enum cper_err_code { + CPER_UNDEFINED = 0, + CPER_ERR_SINGLE_BIT_ECC = 2, + CPER_ERR_MULTI_BIT_ECC = 3, + CPER_ERR_MEM_PARITY_ERR = 8, + CPER_ERR_MEM_SCRUB_CE_ERR = 13, + CPER_ERR_MEM_SCRUB_UCE_ERR = 14, +}; + +/* UEFI Spec, Appendix N.2.5 Memory Error Section */ +struct cper_memory_section { + u64 valid_bits; + u64 err_sts; // Fix later to struct + u64 phys_addr; + u64 phys_addr_mask; + u16 node; + u16 card; + u16 module; + u16 bank; + u16 device; + u16 row; + u16 column; + u16 bit_position; /* bit position of error */ + u64 requestor_id; + u64 responder_id; + u64 target_id; + enum cper_err_code mem_err_type; + u8 extended; + u16 rank_number; + u16 card_handle; + u16 module_handle; +} __packed; + #endif /* _CPER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b Gerrit-Change-Number: 69198 Gerrit-PatchSet: 1 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Hello build bot (Jenkins), Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68893 to look at the new patch set (#6). Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime ...................................................................... [WIP]cpu/mp_init: Detect the number of CPUs are runtime On some systems the only way to find out what CPUs are are present is by in initializing them and seeing which one checks in. TESTED with qemu reporting a too high number of CPUs. Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c 2 files changed, 62 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/68893/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe9d3d4838dad46cd0c7b6d30b905cbd258f17f Gerrit-Change-Number: 68893 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/mp_init.c: Only enable CPUs once they execute code
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68892 to look at the new patch set (#6). Change subject: cpu/mp_init.c: Only enable CPUs once they execute code ...................................................................... cpu/mp_init.c: Only enable CPUs once they execute code On some systems the BSP cannot know how many CPUs are present in the system. A typical use case is a multi socket system. Setting the enable flag only on CPUs that actually exist makes it more flexible. Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/68892/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8 Gerrit-Change-Number: 68892 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Use existing code to create cpu struct device
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Elyes Haouas, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64341 to look at the new patch set (#9). Change subject: cpu/x86/mp_init.c: Use existing code to create cpu struct device ...................................................................... cpu/x86/mp_init.c: Use existing code to create cpu struct device Change-Id: I80baadd405b31d6be2fdbb894b0f4b7c775da6f8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c 1 file changed, 17 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/64341/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/64341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80baadd405b31d6be2fdbb894b0f4b7c775da6f8 Gerrit-Change-Number: 64341 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/system76/adl-p: Add Darter Pro 8
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65301 ) Change subject: mb/system76/adl-p: Add Darter Pro 8 ...................................................................... Patch Set 16: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 1 / 14 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133603 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133602 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133601 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133600 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133599 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133598 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133597 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133595 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133593 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133592 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133591 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133590 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133589 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133588 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/65301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc84d6cc3aec7149d9b538305288bbe2b56d53e4 Gerrit-Change-Number: 65301 Gerrit-PatchSet: 16 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 08:30:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Implement SOC Die lock down configuration
by Subrata Banik (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, Ravishankar Sarawadi, Kapil Porwal, Ivy Jian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68430 ) Change subject: soc/intel/meteorlake: Implement SOC Die lock down configuration ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68430/comment/a3070737_963fe08c PS2, Line 13: Able to build and boot rex to OS. > would appreciate if you can add a more specific test line apart from just booting to OS. > > I guess the S0ix is what being blocked without this CL? @Ravi ping? can u please update the commit msg ? Patchset: PS2: > I've cherry-picked this CL to try, most of time are able to boot to OS. Also observed some system hang in kernel/UI within several reboot iterations, but these are known issue even without this CL. I agree, lets mark this resolve now. Thanks Ivy -- To view, visit https://review.coreboot.org/c/coreboot/+/68430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02 Gerrit-Change-Number: 68430 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 08:17:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/i2c/sx9324: Add support for Linux's SX9324 driver
by Victor Ding (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, Jason Nien, Reka Norman, Martin Roth. Victor Ding has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69192 ) Change subject: drivers/i2c/sx9324: Add support for Linux's SX9324 driver ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69192/comment/20f3c18c_80033cfe PS3, Line 16: > I think this could do with slightly more explanation. I.e. […] Done https://review.coreboot.org/c/coreboot/+/69192/comment/faf8125a_27e6ce00 PS3, Line 18: TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch > This is not true, since the new properties will be added to the ACPI tables with zero values. Done File src/drivers/i2c/sx9324/Kconfig: https://review.coreboot.org/c/coreboot/+/69192/comment/be177cb1_282b6b47 PS3, Line 13: Board may use the legacy sx932x linux driver. > Could you add a few more details, similar to what I suggested for the commit message? Done File src/drivers/i2c/sx9324/sx9324.c: https://review.coreboot.org/c/coreboot/+/69192/comment/f7f4d9f2_ebc52903 PS3, Line 72: cs_idle_sleep > int_comp_resistor Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Gerrit-Change-Number: 69192 Gerrit-PatchSet: 6 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 08:08:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2022