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Change subject: [WIP]cpu/mp_init: Detect the number of CPUs are runtime
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162387):
https://review.coreboot.org/c/coreboot/+/68893/comment/3da95d91_307ee224
PS7, Line 8:
Possible repeated word: 'are'
File src/cpu/x86/mp_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162387):
https://review.coreboot.org/c/coreboot/+/68893/comment/80f0a1a4_fb4b15b8
PS7, Line 490: if (!cpu->enabled) {
braces {} are not necessary for any arm of this statement
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Tim Wawrzynczak, Shuming Chu (Shuming), TangYiwei,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64343
to look at the new patch set (#13).
Change subject: cpu/x86: Add function to get logical CPU number based on lapicid
......................................................................
cpu/x86: Add function to get logical CPU number based on lapicid
Change-Id: I67caba8270bc385f64ad5b3f0f287cb77486f2c2
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/cpu.c
M src/include/cpu/cpu.h
M src/soc/intel/alderlake/acpi.c
3 files changed, 23 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/64343/13
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Change subject: mb/google/brask: Disable PCH USB2 phy power gating for moli
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Thank Zhuohao and Subrata's prompt support. Moli is waiting this CL for FSI firmware qualification. Not sure someone could vote one more +2 to make this CL to land on chromium? Thanks a lot.
Hopefully Tarun will do that.
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Change subject: nb/amd/agesa/family14: Use generic allocation functions for northbridge
......................................................................
Patch Set 13: -Code-Review
(1 comment)
Patchset:
PS13:
It was dead code indeed.
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Change subject: mb/google/brask: Disable PCH USB2 phy power gating for moli
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Thank Zhuohao and Subrata's prompt support. Moli is waiting this CL for FSI firmware qualification. Not sure someone could vote one more +2 to make this CL to land on chromium? Thanks a lot.
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Change subject: lib/coreboot_table: Simplify API to set up lb_serial
......................................................................
Patch Set 12:
(1 comment)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/68768/comment/2575ffef_bdec3288
PS11, Line 498: lb_add_serial
> That's outside the scope here.
But this is the patch that renamed uart_fill_lb to lb_add_serial instead lf lb_serial.
Anyway like you said, it's just a local function that doesn't matter.
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Change subject: lib/coreboot_table: Simplify API to set up lb_serial
......................................................................
Patch Set 12: Code-Review+2
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Change subject: drivers/i2c/sx9324: Add support for Linux's SX9324 driver
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc: Use a more qualified path for "../../chip.h"
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/69061/comment/1889f959_fb74772f
PS2, Line 6: ../chip.h
this refer to what ?
'find -type f -name "chip.h" |grep xeon_sp' gives :
src/soc/intel/xeon_sp/cpx/chip.h
src/soc/intel/xeon_sp/skx/chip.h
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