coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by EricKY Cheng (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Martin Roth, Tim Van Patten, Eric Peers, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Implement DTTS Proposal ...................................................................... Patch Set 30: (1 comment) Patchset: PS30: I found that I will get 3 body detection events continuously during boot without body status change. I need some time to modify the switch behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 30 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 11:00:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib: Fix AMD MP2 BUFFER id
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69165 ) Change subject: commonlib: Fix AMD MP2 BUFFER id ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133671 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133670 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133669 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133668 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133667 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133666 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133665 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133664 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133663 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133662 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133661 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133660 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133659 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133658 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133657 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133656 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6213ac99bc5c64fd5dcd681c7922eafa011fc0 Gerrit-Change-Number: 69165 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 10:31:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Add wifi sar table
by Tyler Wang (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, Kangheui Won, Reka Norman, Tim Wawrzynczak, Nick Vaccaro, Eric Lai. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68660 ) Change subject: mb/google/nissa/var/craask: Add wifi sar table ...................................................................... Patch Set 7: (1 comment) This change is ready for review. File src/mainboard/google/brya/variants/craask/variants.c: https://review.coreboot.org/c/coreboot/+/68660/comment/456dca49_9ddde7b4 PS6, Line 8: enum { > We have FW config for it. https://chrome-internal-review.googlesource. […] Done. Use fw_config to separate use and unuse SAR table case. -- To view, visit https://review.coreboot.org/c/coreboot/+/68660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Gerrit-Change-Number: 68660 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 10:30:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meterolake: Remove PM Enery Report WA
by Subrata Banik (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, Ravishankar Sarawadi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69042 ) Change subject: soc/intel/meterolake: Remove PM Enery Report WA ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69042/comment/ad6da0f9_0c9361bd PS1, Line 9: Pm PM https://review.coreboot.org/c/coreboot/+/69042/comment/3a0753c6_4a05e6e6 PS1, Line 9: boottime boot time https://review.coreboot.org/c/coreboot/+/69042/comment/98a0b6a3_ae5d52dd PS1, Line 13: build/boot Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression. -- To view, visit https://review.coreboot.org/c/coreboot/+/69042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Gerrit-Change-Number: 69042 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 10:21:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common: add units to soc_power_limits_config elements
by Sean Rhodes (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Felix Singer, Jeremy Soller, Nick Vaccaro, Jonathon Hall, Michael Niewöhner, Piotr Król, Tim Crawford, Nico Huber, Tarun Tuli, Michał Żygowski, Dtrain Hsu, Subrata Banik, Kapil Porwal. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69206 ) Change subject: soc/intel/common: add units to soc_power_limits_config elements ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/starlabs/lite/devtree.c: https://review.coreboot.org/c/coreboot/+/69206/comment/ecc34692_2a269acc PS1, Line 43: cfg->tcc_offset = 5; nit: Alignment -- To view, visit https://review.coreboot.org/c/coreboot/+/69206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f954742c525e220f61d0fa5c74f4c75fd9648ef Gerrit-Change-Number: 69206 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 10:09:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common: add units to soc_power_limits_config elements
by Dtrain Hsu (Code Review) 04 Nov '22

04 Nov '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69206 ) Change subject: soc/intel/common: add units to soc_power_limits_config elements ...................................................................... soc/intel/common: add units to soc_power_limits_config elements Rename some elements of soc_power_limits_config and add units. - tdp_pl1_override to tdp_pl1_override_watts - tdp_pl2_override to tdp_pl2_override_watts - tdp_psyspl2 to tdp_psyspl2_watts - tdp_psyspl3 to tdp_psyspl3_watts - tdp_pl4 to tdp_pl4_watts - psys_pmax to psys_pmax_watts BUG=None TEST=Build and boot kinox to ChromeOS Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I9f954742c525e220f61d0fa5c74f4c75fd9648ef --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c M src/mainboard/google/brya/variants/craask/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/kinox/overridetree.cb M src/mainboard/google/brya/variants/moli/overridetree.cb M src/mainboard/google/brya/variants/zydron/overridetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/blipper/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/dedede/variants/haboki/overridetree.cb M src/mainboard/google/dedede/variants/kracko/overridetree.cb M src/mainboard/google/dedede/variants/lalala/overridetree.cb M src/mainboard/google/dedede/variants/lantis/overridetree.cb M src/mainboard/google/dedede/variants/madoo/overridetree.cb M src/mainboard/google/dedede/variants/magolor/overridetree.cb M src/mainboard/google/dedede/variants/metaknight/overridetree.cb M src/mainboard/google/dedede/variants/sasukette/overridetree.cb M src/mainboard/google/dedede/variants/shotzo/overridetree.cb M src/mainboard/google/dedede/variants/storo/overridetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/glados/variants/caroline/overridetree.cb M src/mainboard/google/glados/variants/cave/overridetree.cb M src/mainboard/google/glados/variants/chell/overridetree.cb M src/mainboard/google/glados/variants/glados/overridetree.cb M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb M src/mainboard/google/hatch/variants/kindred/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/mainboard.c M src/mainboard/google/puff/variants/dooly/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/drobit/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/mainboard/intel/adlrvp/ramstage.c M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/starlabs/lite/devtree.c M src/mainboard/starlabs/starbook/variants/cml/devtree.c M src/mainboard/starlabs/starbook/variants/kbl/devtree.c M src/mainboard/starlabs/starbook/variants/tgl/devtree.c M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl-p/variants/darp8/overridetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/chipset_pch_s.cb M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/skylake/chip.c 121 files changed, 448 insertions(+), 427 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/69206/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index ab8787c..9587b91 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -93,8 +93,8 @@ # PL1 override 25W # PL2 override 44W register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 44, + .tdp_pl1_override_watts = 25, + .tdp_pl2_override_watts = 44, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 84eb3cf..4bbad71 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -60,9 +60,9 @@ # PL1, PL2 override 35W, PL4 override 43W register "power_limits_config" = "{ - .tdp_pl1_override = 35, - .tdp_pl2_override = 35, - .tdp_pl4 = 43, + .tdp_pl1_override_watts = 35, + .tdp_pl2_override_watts = 35, + .tdp_pl4_watts = 43, }" # ISL95857 VR diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index a45127c..a8399ed 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -35,7 +35,7 @@ # PL2 override 91W register "power_limits_config" = "{ - .tdp_pl2_override = 91, + .tdp_pl2_override_watts = 91, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index bfcc046..bf904ab 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -12,8 +12,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index d22f574..3fb1854 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -27,8 +27,8 @@ register "SendVrMbxCmd" = "2" register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 211ad4b..b166fcd 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -8,14 +8,14 @@ subsystemid 0x1558 0x14a1 inherit device ref system_agent on register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, - .psys_pmax = 65, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, + .psys_pmax_watts = 65, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, - .psys_pmax = 65, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, + .psys_pmax_watts = 65, }" register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "true" diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index faed00d..0a04ccb 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -88,9 +88,9 @@ register "tcc_offset" = "10" # TCC of 90 register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ - .tdp_pl1_override = 30, - .tdp_pl2_override = 60, - .tdp_pl4 = 90, + .tdp_pl1_override_watts = 30, + .tdp_pl2_override_watts = 60, + .tdp_pl4_watts = 90, }" device domain 0 on diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c index 4d30b8e..2f40e48 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c @@ -76,13 +76,13 @@ settings->pl2.min_power = limits[brask_idx].pl2_min_power; settings->pl2.max_power = limits[brask_idx].pl2_max_power; - if (soc_config->tdp_pl2_override != 0) { - settings->pl2.max_power = soc_config->tdp_pl2_override * 1000; + if (soc_config->tdp_pl2_override_watts != 0) { + settings->pl2.max_power = soc_config->tdp_pl2_override_watts * 1000; settings->pl2.min_power = settings->pl2.max_power; } - if (soc_config->tdp_pl4 == 0) - soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brask_idx].pl4_power, + if (soc_config->tdp_pl4_watts == 0) + soc_config->tdp_pl4_watts = DIV_ROUND_UP(limits[brask_idx].pl4_power, MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1(mW) (%u, %u) PL2(mW) (%u, %u) PL4 (%u)\n", @@ -90,7 +90,7 @@ settings->pl1.max_power, settings->pl2.min_power, settings->pl2.max_power, - soc_config->tdp_pl4); + soc_config->tdp_pl4_watts); } void variant_update_psys_power_limits(const struct cpu_power_limits *limits, @@ -121,7 +121,7 @@ conf = config_of_soc(); soc_config = &conf->power_limits_config[intel_idx]; - soc_config->tdp_pl4 = 0; + soc_config->tdp_pl4_watts = 0; pl2_default = DIV_ROUND_UP(limits[brask_idx].pl2_max_power, MILLIWATTS_TO_WATTS); rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); @@ -136,7 +136,7 @@ /* Limit PL2 if the adapter is with lower capability */ pl2 = (psyspl2 > pl2_default) ? pl2_default : psyspl2; - soc_config->tdp_pl4 = psyspl2; + soc_config->tdp_pl4_watts = psyspl2; } else { /* Input type is barrel jack */ volts_mv = config_psys->bj_volts_mv; @@ -145,14 +145,14 @@ } /* voltage unit is milliVolts and current is in milliAmps */ - soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); - conf->platform_pmax = soc_config->psys_pmax; + soc_config->psys_pmax_watts = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); + conf->platform_pmax = soc_config->psys_pmax_watts; - soc_config->tdp_pl2_override = pl2; - soc_config->tdp_psyspl2 = psyspl2; + soc_config->tdp_pl2_override_watts = pl2; + soc_config->tdp_psyspl2_watts = psyspl2; printk(BIOS_INFO, "Overriding PL2 (%u) PsysPL2 (%u) Psys_Pmax (%u)\n", - soc_config->tdp_pl2_override, - soc_config->tdp_psyspl2, - soc_config->psys_pmax); + soc_config->tdp_pl2_override_watts, + soc_config->tdp_psyspl2_watts, + soc_config->psys_pmax_watts); } diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index 9c2d4aa..ec8850c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -35,7 +35,7 @@ settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; - soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + soc_config->tdp_pl4_watts = DIV_ROUND_UP(limits[i].pl4_power, MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c b/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c index 9c2d4aa..ec8850c 100644 --- a/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c @@ -35,7 +35,7 @@ settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; - soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + soc_config->tdp_pl4_watts = DIV_ROUND_UP(limits[i].pl4_power, MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index c77787f..3f03d9c9 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -107,15 +107,15 @@ register "cnvi_bt_audio_offload" = "1" register "power_limits_config[ADL_N_041_6W_CORE]" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 12, - .tdp_pl4 = 78, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 12, + .tdp_pl4_watts = 78, }" register "power_limits_config[ADL_N_021_6W_CORE]" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 12, - .tdp_pl4 = 78, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 12, + .tdp_pl4_watts = 78, }" device domain 0 on diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index c28dd28..02acedd 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -75,15 +75,15 @@ }" register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 43, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 43, + .tdp_pl4_watts = 105, }" register "power_limits_config[ADL_P_682_28W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 43, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 43, + .tdp_pl4_watts = 105, }" device domain 0 on diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 8356320..18ee6c7 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -66,7 +66,7 @@ }" register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ - .tdp_pl1_override = 30, + .tdp_pl1_override_watts = 30, }" register "tcc_offset" = "6" diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 8f1bf8e..fdf93fc 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -35,10 +35,10 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3 register "tcc_offset" = "0" # TCC of 100C register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ - .tdp_pl1_override = 55, + .tdp_pl1_override_watts = 55, }" register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ - .tdp_pl1_override = 64, + .tdp_pl1_override_watts = 64, }" device domain 0 on device ref dtt on diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb index f8a14be..25a217e 100644 --- a/src/mainboard/google/brya/variants/zydron/overridetree.cb +++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb @@ -75,15 +75,15 @@ }" register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 43, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 43, + .tdp_pl4_watts = 105, }" register "power_limits_config[ADL_P_682_28W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 43, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 43, + .tdp_pl4_watts = 105, }" device domain 0 on diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2124dc4..8041729 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -167,8 +167,8 @@ register "dptf_enable" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "10" # TCC of 90C diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb index 7bfc875..476fd67 100644 --- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb +++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb @@ -60,8 +60,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "10" # TCC of 95C diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 0104ab5..dcee802 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -65,8 +65,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "20" # TCC of 85C diff --git a/src/mainboard/google/dedede/variants/haboki/overridetree.cb b/src/mainboard/google/dedede/variants/haboki/overridetree.cb index e1dd8ef..0479174 100644 --- a/src/mainboard/google/dedede/variants/haboki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/haboki/overridetree.cb @@ -36,8 +36,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "20" # TCC of 85C diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 4bde501..5a3c688 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -59,8 +59,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "20" # TCC of 85C diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb index 8ae9116..aea4979 100644 --- a/src/mainboard/google/dedede/variants/lalala/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb @@ -57,8 +57,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 12, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 12, }" register "tcc_offset" = "15" # TCC of 90C diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index 8d4176b..5a41bbf 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -73,8 +73,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 15, }" # Enable Acoustic noise mitigation and set slew rate to 1/4 diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 319a859..0d43ea7 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -55,8 +55,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "10" # TCC of 95C diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 90ee04f..8236c68 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -96,8 +96,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 12, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 12, }" register "tcc_offset" = "15" # TCC of 90C diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 623595f..301af29 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -65,8 +65,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 12, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 12, }" device domain 0 on diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 1cda193..ae0c15b 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -84,8 +84,8 @@ }" # Camera register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "10" # TCC of 95C diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb index 079bc18..9efff77 100644 --- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb @@ -41,8 +41,8 @@ register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 25, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 25, }" register "tcc_offset" = "5" # TCC of 100C diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 8aba2c8..0da6abe 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -85,8 +85,8 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 20, }" register "tcc_offset" = "10" # TCC of 95C diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index a9de097..8713be3 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -42,9 +42,9 @@ register "s0ix_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 51, - .psys_pmax = 140, + .tdp_pl1_override_watts = 25, + .tdp_pl2_override_watts = 51, + .psys_pmax_watts = 140, }" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 1e9ffd9..e6c42fa 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -223,8 +223,8 @@ register "dptf_enable" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 15, }" register "tcc_offset" = "10" diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 15be049..54af61b 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -115,7 +115,7 @@ pl2 = FIZZ_PL2_U22; if ((1 << sku) & u42_mask) pl2 = FIZZ_PL2_U42; - conf->tdp_psyspl3 = conf->tdp_pl4 = 0; + conf->tdp_psyspl3_watts = conf->tdp_pl4_watts = 0; /* If we can't get charger info or not PD charger, assume barrel jack */ if (rv != 0 || type != USB_CHG_TYPE_PD) { @@ -128,18 +128,18 @@ /* Detected TypeC. Base on max value of adapter */ watts = ((u32)volts_mv * current_ma) / 1000000; psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + conf->tdp_psyspl3_watts = SET_PSYSPL2(psyspl2); /* set max possible time window */ conf->tdp_psyspl3_time = FIZZ_MAX_TIME_WINDOW; /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = FIZZ_MIN_DUTYCYCLE; if ((1 << sku) & u42_mask) - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + conf->tdp_pl4_watts = SET_PSYSPL2(psyspl2); } - conf->tdp_pl2_override = pl2; + conf->tdp_pl2_override_watts = pl2; /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); + conf->tdp_psyspl2_watts = SET_PSYSPL2(psyspl2); } static uint8_t read_oem_id_from_gpio(void) diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 5ecc77b..a09ac5b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -300,8 +300,8 @@ }" register "power_limits_config" = "{ - .tdp_psyspl2 = 90, - .psys_pmax = 120, + .tdp_psyspl2_watts = 90, + .psys_pmax_watts = 120, }" register "tcc_offset" = "6" # TCC of 94C diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index bfa260e..2a86ef7 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -18,7 +18,7 @@ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader register "power_limits_config" = "{ - .psys_pmax = 151, + .psys_pmax_watts = 151, }" device domain 0 on diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 9a3e619..77ec9df 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -75,7 +75,7 @@ # PL2 override 25W register "power_limits_config" = "{ - .tdp_pl2_override = 25, + .tdp_pl2_override_watts = 25, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb index 0e6d5e7..59f4775 100644 --- a/src/mainboard/google/glados/variants/caroline/overridetree.cb +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -28,7 +28,7 @@ # PL2 override 15W register "power_limits_config" = "{ - .tdp_pl2_override = 15, + .tdp_pl2_override_watts = 15, }" # Send an extra VR mailbox command for the supported MPS IMVP8 model diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb index bd3c139..a997795 100644 --- a/src/mainboard/google/glados/variants/cave/overridetree.cb +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -13,7 +13,7 @@ # PL2 override 15W register "power_limits_config" = "{ - .tdp_pl2_override = 15, + .tdp_pl2_override_watts = 15, }" # Send an extra VR mailbox command for the supported MPS IMVP8 model diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb index ad3ae39..f59e188 100644 --- a/src/mainboard/google/glados/variants/chell/overridetree.cb +++ b/src/mainboard/google/glados/variants/chell/overridetree.cb @@ -17,7 +17,7 @@ # PL2 override 15W register "power_limits_config" = "{ - .tdp_pl2_override = 15, + .tdp_pl2_override_watts = 15, }" # Send an extra VR mailbox command for the supported MPS IMVP8 model diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb index 3a0fdd4..f5ec2c3 100644 --- a/src/mainboard/google/glados/variants/glados/overridetree.cb +++ b/src/mainboard/google/glados/variants/glados/overridetree.cb @@ -17,7 +17,7 @@ # PL2 override 15W register "power_limits_config" = "{ - .tdp_pl2_override = 15, + .tdp_pl2_override_watts = 15, }" # Send an extra VR mailbox command for the supported MPS IMVP8 model diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 312e822..eb52d71 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 976d829..cdb1761 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -32,8 +32,8 @@ # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 64, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 64, }" register "Device4Enable" = "1" # Enable eDP device diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 1f795b4..d5012f9 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index c935620..0a565cf 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 64, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 64, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 129bb26..e033abe 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 13, - .tdp_pl2_override = 64, + .tdp_pl1_override_watts = 13, + .tdp_pl2_override_watts = 64, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 900cfca..72d3f02 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index fdb03a3..4e7a842 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6dd94e0..e78093c 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 8, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 8, + .tdp_pl2_override_watts = 51, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 0edea30..b67c228 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -25,8 +25,8 @@ register "FastPkgCRampDisableSa" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 44, + .tdp_pl1_override_watts = 25, + .tdp_pl2_override_watts = 44, }" # Intel Common SoC Config diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 8480147..4fbe687 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index b7f6ff2..d55fd71 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 64, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 64, }" register "SerialIoDevMode" = "{ diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index abf53b47..12d58fa 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -47,8 +47,8 @@ # be reached when RAPL PL1 is set to 10W. # Set RAPL PL2 to 15W. register "power_limits_config" = "{ - .tdp_pl1_override = 10, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 10, + .tdp_pl2_override_watts = 15, }" # Minimum SLP S3 assertion width 28ms. diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d26f6bd..b8c91d3 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -57,9 +57,9 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 15, - .psys_pmax = 45, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 15, + .psys_pmax_watts = 45, }" register "tcc_offset" = "10" diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index b439e30..5a9c740 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -31,5 +31,5 @@ soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - soc_conf->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override_watts = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index db4aeeb..df9afde 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -241,8 +241,8 @@ # PL2 override 15W for KBL-Y register "power_limits_config" = "{ - .tdp_pl2_override = 15, - .psys_pmax = 45, + .tdp_pl2_override_watts = 15, + .psys_pmax_watts = 45, }" register "tcc_offset" = "10" # TCC of 90C diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 8583518..70d3469 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -261,7 +261,7 @@ register "tcc_offset" = "3" # TCC of 97C register "power_limits_config" = "{ - .psys_pmax = 101, + .psys_pmax_watts = 101, }" device cpu_cluster 0 on diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index b703d40..1e08e93 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -283,7 +283,7 @@ soc_conf = &cfg->power_limits_config; /* Update PL2 based on SKU. */ - soc_conf->tdp_pl2_override = get_pl2(pl2_id); + soc_conf->tdp_pl2_override_watts = get_pl2(pl2_id); /* Overwrite settings for different projects based on OEM ID*/ oem_index = find_sku_mapping(read_oem_id()); diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b8a1812..b7de5f3 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -263,8 +263,8 @@ # PL2 override 15W for KBL-Y register "power_limits_config" = "{ - .tdp_pl2_override = 15, - .psys_pmax = 45, + .tdp_pl2_override_watts = 15, + .psys_pmax_watts = 45, }" register "tcc_offset" = "10" # TCC of 90C diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 03336f2..643b72a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -50,9 +50,9 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 18, - .psys_pmax = 45, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 18, + .psys_pmax_watts = 45, }" register "tcc_offset" = "10" diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index eff5cf5..c3aee1c 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -32,5 +32,5 @@ soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - soc_conf->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override_watts = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index c6c2d3d..c05ae0e 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -222,8 +222,8 @@ # PL2 override 18W for AML-Y register "power_limits_config" = "{ - .tdp_pl2_override = 18, - .psys_pmax = 45, + .tdp_pl2_override_watts = 18, + .psys_pmax_watts = 45, }" register "tcc_offset" = "10" # TCC of 90C diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 5c34792..d80faab 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -242,8 +242,8 @@ # PL2 override 15W for KBL-Y register "power_limits_config" = "{ - .tdp_pl2_override = 15, - .psys_pmax = 45, + .tdp_pl2_override_watts = 15, + .psys_pmax_watts = 45, }" register "tcc_offset" = "10" # TCC of 90C diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index b4f3609..9ec2dce 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -2,8 +2,8 @@ register "tcc_offset" = "5" # TCC of 95C register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" # Auto-switch between X4 NVMe and X2 NVMe. diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 976d829..cdb1761 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -32,8 +32,8 @@ # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 64, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 64, }" register "Device4Enable" = "1" # Enable eDP device diff --git a/src/mainboard/google/puff/variants/baseboard/mainboard.c b/src/mainboard/google/puff/variants/baseboard/mainboard.c index e0c3440..7b24b87 100644 --- a/src/mainboard/google/puff/variants/baseboard/mainboard.c +++ b/src/mainboard/google/puff/variants/baseboard/mainboard.c @@ -103,8 +103,8 @@ u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; + conf->tdp_psyspl3_watts = 0; + conf->tdp_pl4_watts = 0; if (rv == 0 && type == USB_CHG_TYPE_PD) { /* Detected USB-PD. Base on max value of adapter */ @@ -119,13 +119,13 @@ else pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; - conf->tdp_psyspl3 = psyspl2; + conf->tdp_psyspl3_watts = psyspl2; /* set max possible time window */ conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; /* set minimum duty cycle */ conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */ - conf->tdp_pl4 = psyspl2; + conf->tdp_pl4_watts = psyspl2; } else { /* * Input type is barrel jack, from the SKU matrix: @@ -143,10 +143,10 @@ } } /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); + conf->psys_pmax_watts = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - conf->tdp_pl2_override = pl2; - conf->tdp_psyspl2 = psyspl2; + conf->tdp_pl2_override_watts = pl2; + conf->tdp_psyspl2_watts = psyspl2; } void variant_ramstage_init(void) diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index 8533f02..73b8875 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -9,8 +9,8 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 49, + .tdp_pl1_override_watts = 25, + .tdp_pl2_override_watts = 49, }" # Auto-switch between X4 NVMe and X2 NVMe. diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index 25778f9..e193d5d 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -2,8 +2,8 @@ register "tcc_offset" = "5" # TCC of 95C register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" # Auto-switch between X4 NVMe and X2 NVMe. diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 1ac9414..5277003 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -2,8 +2,8 @@ register "tcc_offset" = "5" # TCC of 95C register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" # Auto-switch between X4 NVMe and X2 NVMe. diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 50c6d0b..5d6406e 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -2,8 +2,8 @@ register "tcc_offset" = "5" # TCC of 95C register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" # Auto-switch between X4 NVMe and X2 NVMe. diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index cf60462..7fe94a2 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, }" # Auto-switch between X4 NVMe and X2 NVMe. diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index a66cecf..f94cbd4 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -57,8 +57,8 @@ # be reached when RAPL PL1 is set to 12W. # Set RAPL PL2 to 15W. register "power_limits_config" = "{ - .tdp_pl1_override = 12, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 12, + .tdp_pl2_override_watts = 15, }" # Enable Audio Clock and Power gating diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 1eecbb3..8151591 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -57,8 +57,8 @@ # be reached when RAPL PL1 is set to 12W. # Set RAPL PL2 to 15W. register "power_limits_config" = "{ - .tdp_pl1_override = 12, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 12, + .tdp_pl2_override_watts = 15, }" # Enable Audio Clock and Power gating diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 3dfb96b..f25edbd 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -57,8 +57,8 @@ # be reached when RAPL PL1 is set to 12W. # Set RAPL PL2 to 15W. register "power_limits_config" = "{ - .tdp_pl1_override = 12, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 12, + .tdp_pl2_override_watts = 15, }" # Enable Audio Clock and Power gating diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 4e29eb5..b4a71e6 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -54,8 +54,8 @@ # be reached when RAPL PL1 is set to 12W. # Set RAPL PL2 to 15W. register "power_limits_config" = "{ - .tdp_pl1_override = 12, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 12, + .tdp_pl2_override_watts = 15, }" # Enable Audio Clock and Power gating diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 51d28b8..bcd58f9 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -57,8 +57,8 @@ # be reached when RAPL PL1 is set to 12W. # Set RAPL PL2 to 15W. register "power_limits_config" = "{ - .tdp_pl1_override = 12, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 12, + .tdp_pl2_override_watts = 15, }" # Enable Audio Clock and Power gating diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index c0aebd5..3291b85 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -31,9 +31,9 @@ register "dptf_enable" = "1" register "satapwroptimize" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 51, - .psys_pmax = 140, + .tdp_pl1_override_watts = 25, + .tdp_pl2_override_watts = 51, + .psys_pmax_watts = 140, }" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 903bcc6..4992b1d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -39,9 +39,9 @@ register "SlowSlewRateForSa" = "2" register "SlowSlewRateForFivr" = "2" register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - .psys_pmax = 136, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, + .psys_pmax_watts = 136, }" register "Device4Enable" = "1" # Enable eDP device diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 9f3987e..0c8d7e0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -274,24 +274,24 @@ register "external_phy_gated" = "1" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 38, - .tdp_pl4 = 71, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 38, + .tdp_pl4_watts = 71, }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 60, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 60, + .tdp_pl4_watts = 105, }" register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 35, - .tdp_pl4 = 66, + .tdp_pl1_override_watts = 9, + .tdp_pl2_override_watts = 35, + .tdp_pl4_watts = 66, }" register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 40, - .tdp_pl4 = 83, + .tdp_pl1_override_watts = 9, + .tdp_pl2_override_watts = 40, + .tdp_pl4_watts = 83, }" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 810e12d..6c7ab97 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -65,9 +65,9 @@ register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 18, - .tdp_pl2_override = 51, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 18, + .tdp_pl2_override_watts = 51, + .tdp_pl4_watts = 105, }" device domain 0 on diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index f8059df..523d37f 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -12,9 +12,9 @@ register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 28, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 9, + .tdp_pl2_override_watts = 28, + .tdp_pl4_watts = 105, }" register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # Type-C port 1 diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index cacfbc8..8a38602 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -1,14 +1,14 @@ chip soc/intel/tigerlake register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - .tdp_pl4 = 71, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, + .tdp_pl4_watts = 71, }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 51, + .tdp_pl4_watts = 105, }" register "tcc_offset" = "5" # TCC of 95 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d469ca0..3398095 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -3,14 +3,14 @@ register "DdiPort2Hpd" = "0" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 18, - .tdp_pl2_override = 51, - .tdp_pl4 = 71, + .tdp_pl1_override_watts = 18, + .tdp_pl2_override_watts = 51, + .tdp_pl4_watts = 71, }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 18, - .tdp_pl2_override = 51, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 18, + .tdp_pl2_override_watts = 51, + .tdp_pl4_watts = 105, }" register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Cl diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 3ffc35b..ee20821 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -49,7 +49,7 @@ settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; - soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + soc_config->tdp_pl4_watts = DIV_ROUND_UP(limits[i].pl4_power, MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 6ab391e..882fb76 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -58,8 +58,8 @@ # PL1 override: 7.5W setting gives a run-time 6W actual # Set RAPL PL2 to 15W. register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 15, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 15, }" # Enable Audio Clock and Power gating diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fdd1a78..1a7c41a 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -125,8 +125,8 @@ # Add PL1 and PL2 values register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 20, }" # Enable S0ix diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index df35e8a..c255dd4 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -99,7 +99,7 @@ # PL2 override 60W register "power_limits_config" = "{ - .tdp_pl2_override = 60, + .tdp_pl2_override_watts = 60, }" device domain 0 on diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 8695396..dfb60ba 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -152,7 +152,7 @@ # PL2 override 25W register "power_limits_config" = "{ - .tdp_pl2_override = 25, + .tdp_pl2_override_watts = 25, }" device domain 0 on diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index deb9f38..4767307 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -148,7 +148,7 @@ # PL2 override 25W register "power_limits_config" = "{ - .tdp_pl2_override = 25, + .tdp_pl2_override_watts = 25, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7cf13ec..85d0904 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -183,7 +183,7 @@ # PL2 override 25W register "power_limits_config" = "{ - .tdp_pl2_override = 25, + .tdp_pl2_override_watts = 25, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1af05c4..1bdf790 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -122,14 +122,14 @@ # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 38, - .tdp_pl4 = 71, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 38, + .tdp_pl4_watts = 71, }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 60, - .tdp_pl4 = 105, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 60, + .tdp_pl4_watts = 105, }" #HD Audio diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ad1a45d..910c17c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -126,14 +126,14 @@ # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 35, - .tdp_pl4 = 66, + .tdp_pl1_override_watts = 9, + .tdp_pl2_override_watts = 35, + .tdp_pl4_watts = 66, }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 40, - .tdp_pl4 = 83, + .tdp_pl1_override_watts = 9, + .tdp_pl2_override_watts = 40, + .tdp_pl4_watts = 83, }" #HD Audio diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 002f07e..1793338 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -56,7 +56,7 @@ # Vendor set Psys Pmax to 30W register "power_limits_config" = "{ - .psys_pmax = 30, + .psys_pmax_watts = 30, }" # TODO diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 39c2e33..faf7f85 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -146,7 +146,7 @@ # PL2 override 25W register "power_limits_config" = "{ - .tdp_pl2_override = 25, + .tdp_pl2_override_watts = 25, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index b979740..a38309f 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 20, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 20, }" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index 9270313..882c626 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -3,8 +3,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 28, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 28, }" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 94b79f9..e4be3d3 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -143,7 +143,7 @@ # PL2 override 25W register "power_limits_config" = "{ - .tdp_pl2_override = 25, + .tdp_pl2_override_watts = 25, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b2cb360..2be84f8 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -145,8 +145,8 @@ # PL1 override 25W # PL2 override 44W register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 44, + .tdp_pl1_override_watts = 25, + .tdp_pl2_override_watts = 44, }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c index d3f8100..52f1c63 100644 --- a/src/mainboard/starlabs/lite/devtree.c +++ b/src/mainboard/starlabs/lite/devtree.c @@ -28,18 +28,18 @@ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: disable_turbo(); - soc_conf->tdp_pl1_override = 6; - soc_conf->tdp_pl2_override = 10; + soc_conf->tdp_pl1_override_watts = 6; + soc_conf->tdp_pl2_override_watts = 10; cfg->tcc_offset = 15; break; case PP_BALANCED: - soc_conf->tdp_pl1_override = 10; - soc_conf->tdp_pl2_override = 15; + soc_conf->tdp_pl1_override_watts = 10; + soc_conf->tdp_pl2_override_watts = 15; cfg->tcc_offset = 10; break; case PP_PERFORMANCE: - soc_conf->tdp_pl1_override = 10; - soc_conf->tdp_pl2_override = 20; + soc_conf->tdp_pl1_override_watts = 10; + soc_conf->tdp_pl2_override_watts = 20; cfg->tcc_offset = 5; break; } diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c index 95a5d44..ea81217 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c @@ -20,18 +20,18 @@ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: disable_turbo(); - soc_conf->tdp_pl1_override = 15; - soc_conf->tdp_pl2_override = 15; + soc_conf->tdp_pl1_override_watts = 15; + soc_conf->tdp_pl2_override_watts = 15; cfg->tcc_offset = 20; break; case PP_BALANCED: - soc_conf->tdp_pl1_override = 17; - soc_conf->tdp_pl2_override = 20; + soc_conf->tdp_pl1_override_watts = 17; + soc_conf->tdp_pl2_override_watts = 20; cfg->tcc_offset = 15; break; case PP_PERFORMANCE: - soc_conf->tdp_pl1_override = 20; - soc_conf->tdp_pl2_override = 25; + soc_conf->tdp_pl1_override_watts = 20; + soc_conf->tdp_pl2_override_watts = 25; cfg->tcc_offset = 10; break; } diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c index 898519e..1aafb8f 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c @@ -19,17 +19,17 @@ /* Update PL1 & PL2 based on CMOS settings */ switch (get_uint_option("power_profile", 0)) { case 1: - soc_conf->tdp_pl1_override = 17; - soc_conf->tdp_pl2_override = 20; + soc_conf->tdp_pl1_override_watts = 17; + soc_conf->tdp_pl2_override_watts = 20; break; case 2: - soc_conf->tdp_pl1_override = 20; - soc_conf->tdp_pl2_override = 25; + soc_conf->tdp_pl1_override_watts = 20; + soc_conf->tdp_pl2_override_watts = 25; break; default: disable_turbo(); - soc_conf->tdp_pl1_override = 15; - soc_conf->tdp_pl2_override = 15; + soc_conf->tdp_pl1_override_watts = 15; + soc_conf->tdp_pl2_override_watts = 15; break; } diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c index 1c280c4..ebab9c3 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c @@ -27,24 +27,24 @@ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: disable_turbo(); - soc_conf_2core->tdp_pl1_override = 15; - soc_conf_4core->tdp_pl1_override = 15; - soc_conf_2core->tdp_pl2_override = 15; - soc_conf_4core->tdp_pl2_override = 15; + soc_conf_2core->tdp_pl1_override_watts = 15; + soc_conf_4core->tdp_pl1_override_watts = 15; + soc_conf_2core->tdp_pl2_override_watts = 15; + soc_conf_4core->tdp_pl2_override_watts = 15; cfg->tcc_offset = 20; break; case PP_BALANCED: - soc_conf_2core->tdp_pl1_override = 15; - soc_conf_4core->tdp_pl1_override = 15; - soc_conf_2core->tdp_pl2_override = 25; - soc_conf_4core->tdp_pl2_override = 25; + soc_conf_2core->tdp_pl1_override_watts = 15; + soc_conf_4core->tdp_pl1_override_watts = 15; + soc_conf_2core->tdp_pl2_override_watts = 25; + soc_conf_4core->tdp_pl2_override_watts = 25; cfg->tcc_offset = 15; break; case PP_PERFORMANCE: - soc_conf_2core->tdp_pl1_override = 28; - soc_conf_4core->tdp_pl1_override = 28; - soc_conf_2core->tdp_pl2_override = 40; - soc_conf_4core->tdp_pl2_override = 40; + soc_conf_2core->tdp_pl1_override_watts = 28; + soc_conf_4core->tdp_pl1_override_watts = 28; + soc_conf_2core->tdp_pl2_override_watts = 40; + soc_conf_4core->tdp_pl2_override_watts = 40; cfg->tcc_offset = 10; break; } diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 4f16bbd..083a599 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 90, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 90, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb index 4a554ad..889e62c 100644 --- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb @@ -2,9 +2,9 @@ # HACK: Limit PL4 to PL2 to prevent power-off when system is booted on # battery power. This seems to only happen with the i7 units. register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 56, - .tdp_pl4 = 56, // FIXME: Set to 65 + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 56, + .tdp_pl4_watts = 56, // FIXME: Set to 65 }" # GPE configuration diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index b46dac0..abfe816 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 125, - .tdp_pl2_override = 160, + .tdp_pl1_override_watts = 125, + .tdp_pl2_override_watts = 160, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index da86024..50e67bf 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index c02a6ec..e5b4dbf 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 90, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 90, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index e26fe62..a018347 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -15,12 +15,12 @@ # CPU (soc/intel/tigerlake/cpu.c) # Power limits register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 109, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 109, }" register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 109, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 109, }" # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 6322394..7ff1c6b 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -4,8 +4,8 @@ # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 77ba265..27ce192 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index bb75616..e4ff66b 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 78, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 78, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 7350dcd..4c9abbd 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 90, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 90, }" # Enable Enhanced Intel SpeedStep diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index 01593cb..4906529 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -15,12 +15,12 @@ # CPU (soc/intel/tigerlake/cpu.c) # Power limits register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 90, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 90, }" register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 90, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 90, }" # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index 8e05677..c265c95 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -1,12 +1,12 @@ chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 28, - .tdp_pl2_override = 40, + .tdp_pl1_override_watts = 28, + .tdp_pl2_override_watts = 40, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 28, - .tdp_pl2_override = 40, + .tdp_pl1_override_watts = 28, + .tdp_pl2_override_watts = 40, }" # GPE configuration diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 1b4249c..4d4bace 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -1,12 +1,12 @@ chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 28, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 28, + .tdp_pl2_override_watts = 51, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 28, - .tdp_pl2_override = 51, + .tdp_pl1_override_watts = 28, + .tdp_pl2_override_watts = 51, }" # GPE configuration diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index 3be5b5c..31392fa 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -1,12 +1,12 @@ chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" # GPE configuration diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 63a9016..cda68e0 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -11,8 +11,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, + .tdp_pl1_override_watts = 20, + .tdp_pl2_override_watts = 30, }" # Enable Enhanced Intel SpeedStep diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 2b9d380..4f0f637 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -3,91 +3,91 @@ device cpu_cluster 0 on end register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - .tdp_pl4 = 123, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 55, + .tdp_pl4_watts = 123, }" register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ - .tdp_pl1_override = 28, - .tdp_pl2_override = 64, - .tdp_pl4 = 90, + .tdp_pl1_override_watts = 28, + .tdp_pl2_override_watts = 64, + .tdp_pl4_watts = 90, }" register "power_limits_config[ADL_P_682_28W_CORE]" = "{ - .tdp_pl1_override = 28, - .tdp_pl2_override = 64, - .tdp_pl4 = 140, + .tdp_pl1_override_watts = 28, + .tdp_pl2_override_watts = 64, + .tdp_pl4_watts = 140, }" register "power_limits_config[ADL_P_442_482_45W_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 95, - .tdp_pl4 = 125, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 95, + .tdp_pl4_watts = 125, }" register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 115, - .tdp_pl4 = 215, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 115, + .tdp_pl4_watts = 215, }" register "power_limits_config[ADL_M_282_12W_CORE]" = "{ - .tdp_pl1_override = 12, - .tdp_pl2_override = 35, + .tdp_pl1_override_watts = 12, + .tdp_pl2_override_watts = 35, }" register "power_limits_config[ADL_M_282_15W_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 45, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 45, }" register "power_limits_config[ADL_M_242_CORE]" = "{ - .tdp_pl1_override = 9, - .tdp_pl2_override = 30, - .tdp_pl4 = 68, + .tdp_pl1_override_watts = 9, + .tdp_pl2_override_watts = 30, + .tdp_pl4_watts = 68, }" register "power_limits_config[ADL_N_081_7W_CORE]" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 25, - .tdp_pl4 = 78, + .tdp_pl1_override_watts = 7, + .tdp_pl2_override_watts = 25, + .tdp_pl4_watts = 78, }" register "power_limits_config[ADL_N_081_15W_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 35, - .tdp_pl4 = 83, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 35, + .tdp_pl4_watts = 83, }" register "power_limits_config[ADL_N_041_6W_CORE]" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 25, - .tdp_pl4 = 78, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 25, + .tdp_pl4_watts = 78, }" register "power_limits_config[ADL_N_021_6W_CORE]" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 25, - .tdp_pl4 = 78, + .tdp_pl1_override_watts = 6, + .tdp_pl2_override_watts = 25, + .tdp_pl4_watts = 78, }" register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 115, - .tdp_pl4 = 210, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 115, + .tdp_pl4_watts = 210, }" register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ - .tdp_pl1_override = 28, - .tdp_pl2_override = 64, - .tdp_pl4 = 126, + .tdp_pl1_override_watts = 28, + .tdp_pl2_override_watts = 64, + .tdp_pl4_watts = 126, }" register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - .tdp_pl4 = 114, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 55, + .tdp_pl4_watts = 114, }" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index a2337d6..40b627d 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -3,93 +3,93 @@ device cpu_cluster 0 on end register "power_limits_config[ADL_S_882_35W_CORE]" = "{ - .tdp_pl1_override = 35, - .tdp_pl2_override = 106, - .tdp_pl4 = 177, + .tdp_pl1_override_watts = 35, + .tdp_pl2_override_watts = 106, + .tdp_pl4_watts = 177, }" register "power_limits_config[ADL_S_882_65W_CORE]" = "{ - .tdp_pl1_override = 65, - .tdp_pl2_override = 202, - .tdp_pl4 = 311, + .tdp_pl1_override_watts = 65, + .tdp_pl2_override_watts = 202, + .tdp_pl4_watts = 311, }" register "power_limits_config[ADL_S_882_125W_CORE]" = "{ - .tdp_pl1_override = 125, - .tdp_pl2_override = 241, - .tdp_pl4 = 359, + .tdp_pl1_override_watts = 125, + .tdp_pl2_override_watts = 241, + .tdp_pl4_watts = 359, }" register "power_limits_config[ADL_S_882_150W_CORE]" = "{ - .tdp_pl1_override = 150, - .tdp_pl2_override = 241, - .tdp_pl4 = 359, + .tdp_pl1_override_watts = 150, + .tdp_pl2_override_watts = 241, + .tdp_pl4_watts = 359, }" register "power_limits_config[ADL_S_842_35W_CORE]" = "{ - .tdp_pl1_override = 35, - .tdp_pl2_override = 99, - .tdp_pl4 = 140, + .tdp_pl1_override_watts = 35, + .tdp_pl2_override_watts = 99, + .tdp_pl4_watts = 140, }" register "power_limits_config[ADL_S_842_65W_CORE]" = "{ - .tdp_pl1_override = 65, - .tdp_pl2_override = 180, - .tdp_pl4 = 260, + .tdp_pl1_override_watts = 65, + .tdp_pl2_override_watts = 180, + .tdp_pl4_watts = 260, }" register "power_limits_config[ADL_S_842_125W_CORE]" = "{ - .tdp_pl1_override = 125, - .tdp_pl2_override = 190, - .tdp_pl4 = 280, + .tdp_pl1_override_watts = 125, + .tdp_pl2_override_watts = 190, + .tdp_pl4_watts = 280, }" register "power_limits_config[ADL_S_642_125W_CORE]" = "{ - .tdp_pl1_override = 125, - .tdp_pl2_override = 150, - .tdp_pl4 = 230, + .tdp_pl1_override_watts = 125, + .tdp_pl2_override_watts = 150, + .tdp_pl4_watts = 230, }" register "power_limits_config[ADL_S_602_35W_CORE]" = "{ - .tdp_pl1_override = 35, - .tdp_pl2_override = 74, - .tdp_pl4 = 112, + .tdp_pl1_override_watts = 35, + .tdp_pl2_override_watts = 74, + .tdp_pl4_watts = 112, }" register "power_limits_config[ADL_S_602_65W_CORE]" = "{ - .tdp_pl1_override = 65, - .tdp_pl2_override = 117, - .tdp_pl4 = 176, + .tdp_pl1_override_watts = 65, + .tdp_pl2_override_watts = 117, + .tdp_pl4_watts = 176, }" register "power_limits_config[ADL_S_402_60W_CORE]" = "{ - .tdp_pl1_override = 60, - .tdp_pl2_override = 89, - .tdp_pl4 = 125, + .tdp_pl1_override_watts = 60, + .tdp_pl2_override_watts = 89, + .tdp_pl4_watts = 125, }" register "power_limits_config[ADL_S_402_58W_CORE]" = "{ - .tdp_pl1_override = 58, - .tdp_pl2_override = 89, - .tdp_pl4 = 125, + .tdp_pl1_override_watts = 58, + .tdp_pl2_override_watts = 89, + .tdp_pl4_watts = 125, }" register "power_limits_config[ADL_S_402_35W_CORE]" = "{ - .tdp_pl1_override = 35, - .tdp_pl2_override = 69, - .tdp_pl4 = 98, + .tdp_pl1_override_watts = 35, + .tdp_pl2_override_watts = 69, + .tdp_pl4_watts = 98, }" register "power_limits_config[ADL_S_202_46W_CORE]" = "{ - .tdp_pl1_override = 46, - .tdp_pl2_override = 46, - .tdp_pl4 = 57, + .tdp_pl1_override_watts = 46, + .tdp_pl2_override_watts = 46, + .tdp_pl4_watts = 57, }" register "power_limits_config[ADL_S_202_35W_CORE]" = "{ - .tdp_pl1_override = 35, - .tdp_pl2_override = 35, - .tdp_pl4 = 44, + .tdp_pl1_override_watts = 35, + .tdp_pl2_override_watts = 35, + .tdp_pl4_watts = 44, }" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 7051f51..db94d52 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -347,10 +347,10 @@ const struct soc_power_limits_config *soc_config; soc_config = &config->power_limits_config; /* Set PsysPmax if it is available from DT */ - if (soc_config->psys_pmax) { - printk(BIOS_DEBUG, "psys_pmax = %dW\n", soc_config->psys_pmax); + if (soc_config->psys_pmax_watts) { + printk(BIOS_DEBUG, "psys_pmax_watts = %dW\n", soc_config->psys_pmax_watts); /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = soc_config->psys_pmax * 8; + tconfig->PsysPmax = soc_config->psys_pmax_watts * 8; } /* Unlock upper 8 bytes of RTC RAM */ diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 3f18126..9917172 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -19,21 +19,21 @@ struct soc_power_limits_config { /* PL1 Override value in Watts */ - uint16_t tdp_pl1_override; + uint16_t tdp_pl1_override_watts; /* PL2 Override value in Watts */ - uint16_t tdp_pl2_override; + uint16_t tdp_pl2_override_watts; /* SysPL2 Value in Watts */ - uint16_t tdp_psyspl2; + uint16_t tdp_psyspl2_watts; /* SysPL3 Value in Watts */ - uint16_t tdp_psyspl3; + uint16_t tdp_psyspl3_watts; /* SysPL3 window size */ uint32_t tdp_psyspl3_time; /* SysPL3 duty cycle */ uint32_t tdp_psyspl3_dutycycle; /* PL4 Value in Watts */ - uint16_t tdp_pl4; + uint16_t tdp_pl4_watts; /* Estimated maximum platform power in Watts */ - uint16_t psys_pmax; + uint16_t psys_pmax_watts; }; /* Configure power limits for turbo mode */ diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index dce174b..ed203d3 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -128,8 +128,8 @@ /* Set long term power limit to TDP */ limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); + tdp_pl1 = ((conf->tdp_pl1_override_watts == 0) ? + tdp : (conf->tdp_pl1_override_watts * power_unit)); printk(BIOS_INFO, "CPU PL1 = %u Watts\n", tdp_pl1 / power_unit); limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); @@ -142,8 +142,8 @@ /* Set short term power limit to 1.25 * TDP if no config given */ limit.hi = 0; - tdp_pl2 = (conf->tdp_pl2_override == 0) ? - (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); + tdp_pl2 = (conf->tdp_pl2_override_watts == 0) ? + (tdp * 125) / 100 : (conf->tdp_pl2_override_watts * power_unit); printk(BIOS_INFO, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; @@ -157,12 +157,12 @@ MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; /* Set PsysPl2 */ - if (conf->tdp_psyspl2) { + if (conf->tdp_psyspl2_watts) { limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); limit.hi = 0; printk(BIOS_INFO, "CPU PsysPL2 = %u Watts\n", - conf->tdp_psyspl2); - limit.hi |= (conf->tdp_psyspl2 * power_unit) & + conf->tdp_psyspl2_watts); + limit.hi |= (conf->tdp_psyspl2_watts * power_unit) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; @@ -170,12 +170,12 @@ } /* Set PsysPl3 */ - if (conf->tdp_psyspl3) { + if (conf->tdp_psyspl3_watts) { limit = rdmsr(MSR_PL3_CONTROL); limit.lo = 0; printk(BIOS_INFO, "CPU PsysPL3 = %u Watts\n", - conf->tdp_psyspl3); - limit.lo |= (conf->tdp_psyspl3 * power_unit) & + conf->tdp_psyspl3_watts); + limit.lo |= (conf->tdp_psyspl3_watts * power_unit) & PKG_POWER_LIMIT_MASK; /* Enable PsysPl3 */ limit.lo |= PKG_POWER_LIMIT_EN; @@ -191,11 +191,11 @@ } /* Set Pl4 */ - if (conf->tdp_pl4) { + if (conf->tdp_pl4_watts) { limit = rdmsr(MSR_VR_CURRENT_CONFIG); limit.lo = 0; - printk(BIOS_INFO, "CPU PL4 = %u Watts\n", conf->tdp_pl4); - limit.lo |= (conf->tdp_pl4 * power_unit) & + printk(BIOS_INFO, "CPU PL4 = %u Watts\n", conf->tdp_pl4_watts); + limit.lo |= (conf->tdp_pl4_watts * power_unit) & PKG_POWER_LIMIT_MASK; wrmsr(MSR_VR_CURRENT_CONFIG, limit); } diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 0962a7c..6910bad 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -4,13 +4,13 @@ #FIXME: update values for MTL and enable override in systemagent.c register "power_limits_config[MTL_P_POWER_LIMITS_2]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 55, + .tdp_pl1_override_watts = 15, + .tdp_pl2_override_watts = 55, }" register "power_limits_config[MTL_P_POWER_LIMITS_1]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 115, + .tdp_pl1_override_watts = 45, + .tdp_pl2_override_watts = 115, }" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d120d1e..1421361 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -234,10 +234,10 @@ config_t *confg = config_of_soc(); soc_confg = &confg->power_limits_config; /* Set PsysPmax if it is available from DT */ - if (soc_confg->psys_pmax) { + if (soc_confg->psys_pmax_watts) { /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = soc_confg->psys_pmax * 8; - printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); + tconfig->PsysPmax = soc_confg->psys_pmax_watts * 8; + printk(BIOS_DEBUG, "psys_pmax_watts = %d\n", tconfig->PsysPmax); } params->GraphicsConfigPtr = (u32) vbt_data; -- To view, visit https://review.coreboot.org/c/coreboot/+/69206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f954742c525e220f61d0fa5c74f4c75fd9648ef Gerrit-Change-Number: 69206 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
by Sumeet R Pawnikar (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, John Zhao, Kapil Porwal, Tim Wawrzynczak. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67789 ) Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87110bc10b98a27a8f274680597b15a1df488824 Gerrit-Change-Number: 67789 Gerrit-PatchSet: 10 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 10:02:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya : Set EPP value for Vell board
by Sridhar Siricilla (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Gaggery Tsai, Kedar J. Karanje, Tarun Tuli, Jérémy Compostella, Tim Wawrzynczak, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68900 ) Change subject: mb/google/brya : Set EPP value for Vell board ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68900/comment/c1bf4712_414dab27 PS3, Line 11: TEST=Verified code build for Vell board > I have update the PLT KPI details in the CL's commit. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae Gerrit-Change-Number: 68900 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 10:00:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brask: Disable PCH USB2 phy power gating for moli
by Scott Chao (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: YH Lin, Tarun Tuli, Nick Vaccaro, Casper Chang. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69193 ) Change subject: mb/google/brask: Disable PCH USB2 phy power gating for moli ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457d410501be996f0f29ec622e1829f1581c4970 Gerrit-Change-Number: 69193 Gerrit-PatchSet: 5 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 09:55:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h>
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69030 ) Change subject: mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133654 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133653 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133652 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133651 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133650 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133649 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133648 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133647 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133646 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133645 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133644 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133643 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133641 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133640 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133639 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccb7f28a2c913ae0983bf224a03610d7fdd13c68 Gerrit-Change-Number: 69030 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 09:45:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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