coreboot-gerrit November 2022

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[S] Change in coreboot[master]: UPSTREAM: cbfstool: Fix possible memory leak
by Rizwan Qureshi (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: V Sowmya, Shahina Shaik, Haribalaraman Ramasubramanian, Sridhar Siricilla, Balaji Manigandan. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69220 ) Change subject: UPSTREAM: cbfstool: Fix possible memory leak ...................................................................... Patch Set 1: (1 comment) File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/69220/comment/ae5b6c40_64b8d03e PS1, Line 774: goto done; you need to set "ret" before jumping from here. -- To view, visit https://review.coreboot.org/c/coreboot/+/69220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e Gerrit-Change-Number: 69220 Gerrit-PatchSet: 1 Gerrit-Owner: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 13:34:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69032 ) Change subject: soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h> Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/bootblock/update_descriptor.c M src/soc/intel/apollolake/report_platform.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/sgx.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/timer/timer.c M src/soc/intel/elkhartlake/bootblock/report_platform.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/jasperlake/bootblock/report_platform.c M src/soc/intel/meteorlake/bootblock/report_platform.c M src/soc/intel/meteorlake/cpu.c M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/romstage/report_platform.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/tigerlake/bootblock/report_platform.c M src/soc/intel/tigerlake/lpm.c 23 files changed, 72 insertions(+), 58 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index edc3ca8..2be7546 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -6,16 +6,16 @@ * Chapter number: 2, 14 */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/bootblock.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/alderlake/bootblock/update_descriptor.c b/src/soc/intel/alderlake/bootblock/update_descriptor.c index dbb152c..9c8ce9c 100644 --- a/src/soc/intel/alderlake/bootblock/update_descriptor.c +++ b/src/soc/intel/alderlake/bootblock/update_descriptor.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <arch/cpu.h> #include <arch/mmio.h> #include <cf9_reset.h> #include <commonlib/region.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <fmap.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c index 31a6458..2e73f4a 100644 --- a/src/soc/intel/apollolake/report_platform.c +++ b/src/soc/intel/apollolake/report_platform.c @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/romstage.h> +#include <device/pci_ops.h> #include <soc/pci_devs.h> +#include <soc/romstage.h> static struct { u32 cpuid; diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 26de1cb..4e8dc68 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -1,19 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpi_pm.h> #include <bootstate.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> - #include <soc/device_nvs.h> #include <soc/gpio.h> +#include <soc/iosf.h> #include <soc/lpc.h> #include <soc/msr.h> #include <soc/nvs.h> @@ -21,7 +21,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> -#include <soc/iosf.h> #define SHOW_PATTRS 1 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 1dffd2d..6784eb9 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <acpi/acpi_pm.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <intelblocks/acpi_wake_source.h> #include <fsp/util.h> +#include <intelblocks/acpi_wake_source.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index 7e044be..5dbe196 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -1,17 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> -#include <device/pci.h> -#include <string.h> +#include <cpu/cpu.h> #include <cpu/intel/haswell/haswell.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> +#include <device/pci.h> +#include <device/pci_ops.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/systemagent.h> +#include <string.h> /* FIXME: Needs an update */ static struct { diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index fe36271..c062746 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/bootblock.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 99cf23f..f0903ff 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -2,16 +2,17 @@ #include <acpi/acpi_pm.h> #include <acpi/acpigen.h> -#include <arch/cpu.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <console/console.h> -#include <cpu/intel/turbo.h> -#include <cpu/intel/msr.h> +#include <cpu/cpu.h> #include <cpu/intel/common/common.h> +#include <cpu/intel/msr.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/smm.h> -#include <intelblocks/acpi.h> #include <intelblocks/acpi_wake_source.h> +#include <intelblocks/acpi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <intelblocks/sgx.h> @@ -19,7 +20,6 @@ #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/pm.h> -#include <cpu/x86/lapic.h> #define CPUID_6_EAX_ISST (1 << 7) diff --git a/src/soc/intel/common/block/acpi/sgx.c b/src/soc/intel/common/block/acpi/sgx.c index 7d9073d..4d2bab5 100644 --- a/src/soc/intel/common/block/acpi/sgx.c +++ b/src/soc/intel/common/block/acpi/sgx.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <intelblocks/acpi.h> #include <intelblocks/sgx.h> diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 4898066..1c7a173 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <assert.h> #include <acpi/acpigen.h> +#include <assert.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <arch/cpu.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1d30a8d..f051061 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,17 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> -#include <console/console.h> #include <cbfs.h> #include <commonlib/region.h> +#include <console/console.h> +#include <cpu/cpu.h> #include <fmap.h> +#include <intelbasecode/debug_feature.h> #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> -#include <intelbasecode/debug_feature.h> -#include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> +#include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> #include <timestamp.h> diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 0d201a5..88d1bf2 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <cpu/x86/tsc.h> #include <intelblocks/msr.h> diff --git a/src/soc/intel/elkhartlake/bootblock/report_platform.c b/src/soc/intel/elkhartlake/bootblock/report_platform.c index cc3462d..40816bb 100644 --- a/src/soc/intel/elkhartlake/bootblock/report_platform.c +++ b/src/soc/intel/elkhartlake/bootblock/report_platform.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index 2188009..2a1a13b 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/bootblock.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index 0d2fe43..357d038 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/bootblock.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 72d0d83..63f1771 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/bootblock.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 00caaa5..55ab15c 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -1,25 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> +#include <assert.h> #include <console/console.h> -#include <device/pci.h> +#include <cpu/cpu.h> +#include <cpu/intel/common/common.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/turbo.h> -#include <cpu/intel/common/common.h> +#include <device/pci.h> #include <fsp/api.h> +#include <intelblocks/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> -#include <intelblocks/acpi.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> -#include <assert.h> bool cpu_soc_is_in_untrusted_mode(void) { diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index d54a74a..3002322f 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -3,7 +3,7 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <device/device.h> #include <soc/QuarkNcSocId.h> diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c index ab5b0d1..3b4e367 100644 --- a/src/soc/intel/quark/romstage/report_platform.c +++ b/src/soc/intel/quark/romstage/report_platform.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/romstage.h> diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 9ae0bb6..5824630 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpi_pm.h> +#include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <arch/cpu.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <console/console.h> -#include <intelblocks/acpi.h> +#include <cpu/cpu.h> #include <intelblocks/acpi_wake_source.h> +#include <intelblocks/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <soc/cpu.h> diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 3cfac5e..ce250ad 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/pch.h> diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index af7a96a..1ecaf77 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -6,14 +6,14 @@ * Chapter number: 2, 4, 5, 6 */ -#include <arch/cpu.h> -#include <device/pci_ops.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/bootblock.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/tigerlake/lpm.c b/src/soc/intel/tigerlake/lpm.c index 0dd725a..fe4f43d 100644 --- a/src/soc/intel/tigerlake/lpm.c +++ b/src/soc/intel/tigerlake/lpm.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <arch/cpu.h> -#include <device/device.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> +#include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/lpm.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/69032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Gerrit-Change-Number: 69032 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69145 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling ...................................................................... drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB and prints EWL type 3 primarily associated with MRC training failures. Change-Id: Ibd5b521bafd457505db4147c5d3fe41364a09045 Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69145 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/drivers/ocp/ewl/Kconfig A src/drivers/ocp/ewl/Makefile.inc A src/drivers/ocp/ewl/ewl.c A src/drivers/ocp/ewl/ocp_ewl.h 4 files changed, 92 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, approved diff --git a/src/drivers/ocp/ewl/Kconfig b/src/drivers/ocp/ewl/Kconfig new file mode 100644 index 0000000..3c3b82d --- /dev/null +++ b/src/drivers/ocp/ewl/Kconfig @@ -0,0 +1,5 @@ +config OCP_EWL + bool + default n + help + It implements checking FSP Enhanced Warning Log Hob. diff --git a/src/drivers/ocp/ewl/Makefile.inc b/src/drivers/ocp/ewl/Makefile.inc new file mode 100644 index 0000000..43112e9 --- /dev/null +++ b/src/drivers/ocp/ewl/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_OCP_EWL) += ewl.c diff --git a/src/drivers/ocp/ewl/ewl.c b/src/drivers/ocp/ewl/ewl.c new file mode 100644 index 0000000..d70a23f --- /dev/null +++ b/src/drivers/ocp/ewl/ewl.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/soc_util.h> +#include <lib.h> +#include "ocp_ewl.h" + +static void process_ewl_type3(EWL_ENTRY_HEADER *header, EWL_ENTRY_MEMORY_LOCATION memory_location) +{ + /* Treat warning as type 3, collect basic information and print to serial log */ + EWL_ENTRY_TYPE3 *basic_warning; + basic_warning = (EWL_ENTRY_TYPE3 *)header; + printk(BIOS_ERR, "Major Warning Code = 0x%02x, Minor Warning Code = 0x%02x,\n", + basic_warning->Context.MajorWarningCode, + basic_warning->Context.MinorWarningCode); + printk(BIOS_ERR, "Major Checkpoint: 0x%02x\n", basic_warning->Context.MajorCheckpoint); + printk(BIOS_ERR, "Minor Checkpoint: 0x%02x\n", basic_warning->Context.MinorCheckpoint); + + if (memory_location.Socket != 0xff) + printk(BIOS_ERR, "Socket %d\n", memory_location.Socket); + if (memory_location.Channel != 0xff) + printk(BIOS_ERR, "Channel %d\n", memory_location.Channel); + if (memory_location.Dimm != 0xff) + printk(BIOS_ERR, "Dimm %d\n", memory_location.Dimm); + if (memory_location.Rank != 0xff) + printk(BIOS_ERR, "Rank %d\n", memory_location.Rank); +} + +void get_ewl(void) +{ + const EWL_PRIVATE_DATA *hob = get_ewl_hob(); + int offset = 0; + bool type3_flag = 0; + EWL_ENTRY_HEADER *warning_header; + printk(BIOS_DEBUG, "Number of EWL entries %d\n", hob->numEntries); + while (offset < hob->status.Header.FreeOffset) { + warning_header = (EWL_ENTRY_HEADER *) &(hob->status.Buffer[offset]); + if (warning_header->Type == EwlType3) { + printk(BIOS_ERR, "EWL type: %d\n", warning_header->Type); + if (warning_header->Size != sizeof(EWL_ENTRY_TYPE3)) { + printk(BIOS_ERR, "EWL type3 size mismatch!\n"); + return; + } + EWL_ENTRY_TYPE3 *type3; + type3 = (EWL_ENTRY_TYPE3 *)warning_header; + process_ewl_type3(warning_header, type3->MemoryLocation); + type3_flag = 1; + } else { + printk(BIOS_DEBUG, "EWL type: %d size:%d severity level:%d\n", + warning_header->Type, + warning_header->Size, + warning_header->Severity); + hexdump(&(hob->status.Buffer[offset]), warning_header->Size); + } + offset += warning_header->Size; + } + if (type3_flag) + die("Memory Training Error!\n"); +} diff --git a/src/drivers/ocp/ewl/ocp_ewl.h b/src/drivers/ocp/ewl/ocp_ewl.h new file mode 100644 index 0000000..38d5286d --- /dev/null +++ b/src/drivers/ocp/ewl/ocp_ewl.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __OCP_EWL_H +#define __OCP_EWL_H + +#include <soc/soc_util.h> + +void get_ewl(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd5b521bafd457505db4147c5d3fe41364a09045 Gerrit-Change-Number: 69145 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69144 ) Change subject: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function ...................................................................... soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69144 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c 3 files changed, 31 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 0cd267b..7e18b92 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -5,7 +5,7 @@ subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c ddr.c +romstage-y += romstage.c ddr.c soc_util.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 5ce3928..c4e2a7d 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -5,11 +5,13 @@ #include <hob_iiouds.h> #include <hob_memmap.h> +#include <hob_enhancedwarningloglib.h> const struct SystemMemoryMapHob *get_system_memory_map(void); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); int soc_get_stack_for_port(int port); +const EWL_PRIVATE_DATA *get_ewl_hob(void); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index cd1e06d..2a8b6c9 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -9,6 +9,20 @@ #include <soc/soc_util.h> #include <soc/util.h> +const EWL_PRIVATE_DATA *get_ewl_hob(void) +{ + size_t hob_size; + static const EWL_PRIVATE_DATA *hob; + const uint8_t ewl_id_hob_guid[16] = FSP_HOB_EWLID_GUID; + + if (hob != NULL) + return hob; + + hob = fsp_find_extension_hob_by_guid(ewl_id_hob_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + return hob; +} + const struct SystemMemoryMapHob *get_system_memory_map(void) { size_t hob_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/69144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Gerrit-Change-Number: 69144 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69143 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M ...................................................................... soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may contain several warnings/errors related to core, uncore and memory, etc. mainboard can override it in its romstage.c for its own Enhanced Warning Log check. Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 2 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 90689af..a2adfed 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -9,4 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); void save_dimm_info(void); +void mainboard_ewl_check(void); + #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index b1c7b3b..d001d61 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -15,6 +15,7 @@ fsp_memory_init(false); printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); + mainboard_ewl_check(); unlock_pam_regions(); @@ -31,3 +32,4 @@ } __weak void save_dimm_info(void) { } +__weak void mainboard_ewl_check(void) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/69143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Gerrit-Change-Number: 69143 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69089 ) Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM ...................................................................... soc/mediatek/mt8188: Disable input-gating for big-core SRAM The input-gating is an experimental feature (but unfortunately default enabled) and would lead to crash on MT8188, so we have to disable it in the firmware stage. BUG=b:233720142 TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69089 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/cpu_input_gating.c A src/soc/mediatek/mt8188/include/soc/cpu_input_gating.h M src/soc/mediatek/mt8188/soc.c 4 files changed, 51 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index fc56eb3..52fc861 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += ../common/auxadc.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c +ramstage-y += cpu_input_gating.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c diff --git a/src/soc/mediatek/mt8188/cpu_input_gating.c b/src/soc/mediatek/mt8188/cpu_input_gating.c new file mode 100644 index 0000000..10f6338 --- /dev/null +++ b/src/soc/mediatek/mt8188/cpu_input_gating.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/cpu_input_gating.h> + +#define CPU6_IG_EN_REG (MCUSYS_BASE + 0x3308) +#define CPU7_IG_EN_REG (MCUSYS_BASE + 0x3b08) +#define DISABLE_CPU_IG 0xfc000001 + +void disable_cpu_input_gating(void) +{ + write32p(CPU6_IG_EN_REG, DISABLE_CPU_IG); + write32p(CPU7_IG_EN_REG, DISABLE_CPU_IG); +} diff --git a/src/soc/mediatek/mt8188/include/soc/cpu_input_gating.h b/src/soc/mediatek/mt8188/include/soc/cpu_input_gating.h new file mode 100644 index 0000000..fe07457 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/cpu_input_gating.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_MT8188_CPU_INPUT_GATING_H +#define SOC_MEDIATEK_MT8188_CPU_INPUT_GATING_H + +void disable_cpu_input_gating(void); + +#endif /* SOC_MEDIATEK_MT8188_CPU_INPUT_GATING_H */ diff --git a/src/soc/mediatek/mt8188/soc.c b/src/soc/mediatek/mt8188/soc.c index bcbea03..c63b5ca 100644 --- a/src/soc/mediatek/mt8188/soc.c +++ b/src/soc/mediatek/mt8188/soc.c @@ -3,6 +3,7 @@ #include <bootmem.h> #include <console/console.h> #include <device/device.h> +#include <soc/cpu_input_gating.h> #include <soc/devapc.h> #include <soc/dfd.h> #include <soc/dpm.h> @@ -27,6 +28,9 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + + disable_cpu_input_gating(); + dapc_init(); mcupm_init(); sspm_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 13 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69088 ) Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver ...................................................................... soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver When enabling cpufreq-hw driver, it is required for MCUPM to access secure registers. Therefore, we enable side-band to allow MCUPM to access the secure registers. BUG=b:236331463 TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/devapc.h 2 files changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 1fe3cf8..afb39d5 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1550,7 +1550,10 @@ static void infra_init(uintptr_t base) { - /* Default APC setting */ + /* Side-band */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), MCUPM_SEC, SECURE_TRANS); + + /* TODO: Setup SCP, SSPM and MCUPM permissions in APC . */ set_infra_ao_apc(base); } diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h index e0b0f00..3cbce5c 100644 --- a/src/soc/mediatek/mt8188/include/soc/devapc.h +++ b/src/soc/mediatek/mt8188/include/soc/devapc.h @@ -17,6 +17,8 @@ AO_APC_CON = 0x00F00, }; +DEFINE_BIT(MCUPM_SEC, 1) + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 13 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/include/gpio_defs.h: Add comment for accuracy
by Fred Reitberger (Code Review) 04 Nov '22

04 Nov '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69209 ) Change subject: soc/amd/common/include/gpio_defs.h: Add comment for accuracy ...................................................................... soc/amd/common/include/gpio_defs.h: Add comment for accuracy The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times slightly. Time PCO Others 1mS 0.915mS 1.220mS 2mS 2.013mS 2.684mS Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/69209/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 187be51..718a45c 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -113,6 +113,7 @@ #define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT) #define GPIO_TIMEBASE_61uS 0 +/* The next value is only 183uS on Picasso. It is 244uS on Cezanne and later SoCs */ #define GPIO_TIMEBASE_183uS (1 << 4) #define GPIO_TIMEBASE_15560uS (1 << 7) #define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS) -- To view, visit https://review.coreboot.org/c/coreboot/+/69209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Gerrit-Change-Number: 69209 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: vboot: Introduce handy vboot reboot functions
by Jakub Czapiga (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Julius Werner, Fred Reitberger, Yu-Ping Wu, Felix Held. Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69208 ) Change subject: vboot: Introduce handy vboot reboot functions ...................................................................... vboot: Introduce handy vboot reboot functions This patch groups vboot context, recovery reason and subcode saving, and reboot calls into two handy functions: - vboot_save_and_reboot() - save context and reboot - vboot_fail_and_reboot() - store recovery reason and call function above Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 --- M src/security/vboot/vboot_common.c M src/security/vboot/vboot_common.h M src/security/vboot/vboot_logic.c M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/intel/common/block/cse/cse.c 5 files changed, 64 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/69208/1 diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index c557f25..c9e61d0 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -11,6 +11,11 @@ void vboot_save_data(struct vb2_context *ctx) { + if (!verification_should_run() && !(ENV_ROMSTAGE && CONFIG(VBOOT_EARLY_EC_SYNC)) + && (ctx->flags + & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | VB2_CONTEXT_SECDATA_KERNEL_CHANGED))) + die("TPM writeback in " ENV_STRING "?"); + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED && (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { printk(BIOS_INFO, "Saving secdata firmware\n"); @@ -64,3 +69,20 @@ vboot_platform_prepare_reboot(); board_reset(); } + +void vboot_save_and_reboot(struct vb2_context *ctx, uint8_t subcode) +{ + printk(BIOS_INFO, "vboot: reboot requested (%#x)\n", subcode); + vboot_save_data(ctx); + vboot_reboot(); +} + +void vboot_fail_and_reboot(uint8_t reason, uint8_t subcode) +{ + struct vb2_context *ctx = vboot_get_context(); + + if (reason) + vb2api_fail(ctx, reason, subcode); + + vboot_save_and_reboot(ctx, subcode); +} diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 512da0e..382bcaa 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -20,6 +20,16 @@ */ void vboot_reboot(void); +/* + * Save vboot data and reboot device. Subcode will only be printed. To store + * failure reason and subcode vb2api_fail() should be called before this + * function or vboot_fail_and_reboot() should be used instead. + */ +void vboot_save_and_reboot(struct vb2_context *ctx, uint8_t subcode); + +/* Call vb2api_fail() with reason and subcode, save vboot data and reboot. */ +void vboot_fail_and_reboot(uint8_t reason, uint8_t subcode); + /* Allow the platform to do any clean up work when vboot requests a reboot. */ void vboot_platform_prepare_reboot(void); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2230b5ab..b09e953 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -327,30 +327,22 @@ goto verstage_main_exit; } - printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - vboot_save_data(ctx); - vboot_reboot(); + vboot_save_and_reboot(ctx, rv); } /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); rv = vb2api_fw_phase2(ctx); - if (rv) { - printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - vboot_save_data(ctx); - vboot_reboot(); - } + if (rv) + vboot_save_and_reboot(ctx, rv); /* Try that slot (verify its keyblock and preamble) */ printk(BIOS_INFO, "Phase 3\n"); timestamp_add_now(TS_VERIFY_SLOT_START); rv = vb2api_fw_phase3(ctx); timestamp_add_now(TS_VERIFY_SLOT_END); - if (rv) { - printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - vboot_save_data(ctx); - vboot_reboot(); - } + if (rv) + vboot_save_and_reboot(ctx, rv); printk(BIOS_INFO, "Phase 4\n"); rv = vboot_locate_firmware(ctx, &fw_body); @@ -360,21 +352,16 @@ rv = hash_body(ctx, &fw_body); vboot_save_data(ctx); - if (rv) { - printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - vboot_reboot(); - } + if (rv) + vboot_save_and_reboot(ctx, rv); /* Only extend PCRs once on boot. */ if (!(ctx->flags & VB2_CONTEXT_S3_RESUME)) { timestamp_add_now(TS_TPMPCR_START); rv = extend_pcrs(ctx); if (rv) { - printk(BIOS_WARNING, - "Failed to extend TPM PCRs (%#x)\n", rv); - vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv); - vboot_save_data(ctx); - vboot_reboot(); + printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv); + vboot_fail_and_reboot(VB2_RECOVERY_RO_TPM_U_ERROR, rv); } timestamp_add_now(TS_TPMPCR_END); } @@ -385,9 +372,7 @@ rv = antirollback_lock_space_firmware(); if (rv) { printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv); - vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0); - vboot_save_data(ctx); - vboot_reboot(); + vboot_fail_and_reboot(VB2_RECOVERY_RO_TPM_L_ERROR, rv); } timestamp_add_now(TS_TPMLOCK_END); @@ -395,12 +380,8 @@ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) { rv = antirollback_lock_space_mrc_hash(MRC_REC_HASH_NV_INDEX); if (rv) { - printk(BIOS_INFO, "Failed to lock rec hash space(%x)\n", - rv); - vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_REC_HASH_L_ERROR, - 0); - vboot_save_data(ctx); - vboot_reboot(); + printk(BIOS_INFO, "Failed to lock rec hash space(%x)\n", rv); + vboot_fail_and_reboot(VB2_RECOVERY_RO_TPM_REC_HASH_L_ERROR, 0); } } diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 0dc3314..d927079 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -42,11 +42,8 @@ return; } - vb2api_fail(ctx, VB2_RECOVERY_RO_UNSPECIFIED, (int)subcode); - vboot_save_data(ctx); - svc_debug_print("Rebooting into recovery\n"); - vboot_reboot(); + vboot_fail_and_reboot(VB2_RECOVERY_RO_UNSPECIFIED, (int)subcode); } static uint32_t check_cmos_recovery(void) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c2c94ec..47ba064 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -931,15 +931,9 @@ "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1), me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); - if (CONFIG(VBOOT)) { - struct vb2_context *ctx = vboot_get_context(); - if (ctx == NULL) - goto failure; - vb2api_fail(ctx, VB2_RECOVERY_INTEL_CSE_LITE_SKU, reason); - vboot_save_data(ctx); - vboot_reboot(); - } -failure: + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(VB2_RECOVERY_INTEL_CSE_LITE_SKU, reason); + die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 Gerrit-Change-Number: 69208 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: vboot: Add VBOOT_CBFS_INTEGRATION support
by Jakub Czapiga (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Jakub Czapiga, Matt DeVillier, Fred Reitberger, Felix Held. Hello Hung-Te Lin, build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Julius Werner, Eric Lai, Fred Reitberger, Yu-Ping Wu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66909 to look at the new patch set (#21). Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support ...................................................................... vboot: Add VBOOT_CBFS_INTEGRATION support This patch introduces support signing and verification of firmware slots using CBFS metadata hash verification method for faster initial verification. To have complete verification, CBFS_VERIFICATION should also be enabled, as metadata hash covers only files metadata, not their contents. This patch also adapts mainboards and SoCs to new vboot reset requirements. TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca --- M src/include/cbfs_glue.h M src/lib/cbfs.c M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/cherry/Makefile.inc M src/mainboard/google/corsola/Makefile.inc M src/mainboard/google/geralt/Makefile.inc M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c M src/soc/mediatek/mt8173/Makefile.inc 12 files changed, 117 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/66909/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/66909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Gerrit-Change-Number: 66909 Gerrit-PatchSet: 21 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022