Attention is currently required from: Andrey Petrov.
Hello Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69223
to look at the new patch set (#2).
Change subject: mp_service_ppi: Use struct device to fill in buffer
......................................................................
mp_service_ppi: Use struct device to fill in buffer
Now the CPU topology is filled in struct device during mp_init.
Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
3 files changed, 20 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/69223/2
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Change subject: cpu: Add SPDX license headers to Makefiles
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/cpu/amd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68979/comment/879bef70_a8339e09
PS1, Line 1: ## SPDX-License-Identifier: GPL-2.0-only
> nit: I think these files could use one empty line after SPDX comment to make them more eye-appealing
+1
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68595 )
Change subject: payloads: Make PAYLOAD_NONE a bool outside of the choice
......................................................................
payloads: Make PAYLOAD_NONE a bool outside of the choice
Instead of having the config option PAYLOADS_NONE inside the choice of
payloads, make that a separate choice that enables the payload menu.
If the no_payload option is selected, this hides the other options
and keeps them out of the saved config file and config.h
Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Change-Id: I932c65630261a5b39809abf4dfbda5bf932c6684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68595
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sean Rhodes <sean(a)starlabs.systems>
---
M payloads/Kconfig
1 file changed, 30 insertions(+), 10 deletions(-)
Approvals:
build bot (Jenkins): Verified
Sean Rhodes: Looks good to me, approved
diff --git a/payloads/Kconfig b/payloads/Kconfig
index 2e627d7..2a2773a 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -1,15 +1,8 @@
menu "Payload"
-config NO_DEFAULT_PAYLOAD
- bool
-
-choice
- prompt "Add a payload"
- default PAYLOAD_NONE if NO_DEFAULT_PAYLOAD || !ARCH_X86
- default PAYLOAD_SEABIOS if ARCH_X86
-
config PAYLOAD_NONE
- bool "None"
+ bool "Don't add a payload"
+ default y if !ARCH_X86
help
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
@@ -18,6 +11,11 @@
For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.
+if !PAYLOAD_NONE
+choice
+ prompt "Payload to add"
+ default PAYLOAD_SEABIOS if ARCH_X86
+
config PAYLOAD_ELF
bool "An ELF executable payload"
help
@@ -58,7 +56,7 @@
prompt "Payload compression algorithm"
default COMPRESSED_PAYLOAD_LZMA
default COMPRESSED_PAYLOAD_NONE if PAYLOAD_LINUX || PAYLOAD_LINUXBOOT || PAYLOAD_FIT
- depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
+ depends on !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
help
Choose the compression algorithm for the chosen payloads.
You can choose between None, LZMA, or LZ4.
@@ -178,4 +176,7 @@
source "payloads/external/*/Kconfig.secondary"
endmenu # "Secondary Payloads"
+
+endif # !PAYLOAD_NONE
+
endmenu
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Change subject: Docs: Add SPDX headers to Makefiles
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
File Documentation/Makefile:
https://review.coreboot.org/c/coreboot/+/68957/comment/f1b750ef_949725d1
PS2, Line 1: ## SPDX-License-Identifier: GPL-2.0-only
nit: Using one # would be consistent with the existing comments.
File Documentation/Makefile.sphinx:
https://review.coreboot.org/c/coreboot/+/68957/comment/73498b69_d7892728
PS2, Line 1: ## SPDX-License-Identifier: GPL-2.0-only
Ditto
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69037 )
Change subject: cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/cpu/intel/common/hyperthreading.c:
https://review.coreboot.org/c/coreboot/+/69037/comment/fd6ebc20_c6d03e19
PS2, Line 4: #include <cpu/cpu.h>
not sure if you want to reorder this one too to have it in alphabetic order
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 )
Change subject: common/acpi/dptc: Implement DTTS Proposal
......................................................................
Patch Set 30:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68471/comment/421dc49c_8aa31a32
PS30, Line 9: DTTS indicated Dynamic Thermal Table Switching.
: The proposal would like to develop the schematic
: for switching 6 thermal table by lid status,
: machine body mode and temperature.
: After entering the OS, the thermal table would be table A.
: If the “Motion” or “Lid-status changement” is detected.
: The thermal table would switch to laptop mode or lid-close
: mode. Once the higher environment temperatures are detected,
: the thermal table would switch to the corresponding power
: throttle table(B, D or F). Based on these table switching
: mechanisms, no matter how the end-user uses Chromebook,
: they could enjoy more humanized thermal designs.
Please reflow for 72 characters per line, and add a blank line between paragraphs.
https://review.coreboot.org/c/coreboot/+/68471/comment/314f318a_ecc45747
PS30, Line 39: Table
table
https://review.coreboot.org/c/coreboot/+/68471/comment/4366f625_742066d3
PS30, Line 39: 5. Assume Table A is current table. When the temperature
Maybe start a new paragraph, saying it’s an example.
https://review.coreboot.org/c/coreboot/+/68471/comment/72ecd019_76daab1d
PS30, Line 40: reach
reaches
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Change subject: drivers/i2c/sx9324: Add support for Linux's SX9324 driver
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69192/comment/cf5821ef_a5032d54
PS6, Line 26: TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy
nit: do you mind including what board(s)/platform(s) you verified the SSDT on
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Change subject: src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR
......................................................................
Patch Set 3: Code-Review+2
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