coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505
by Kyösti Mälkki (Code Review) 17 Nov '22

17 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69759 ) Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505 ...................................................................... [NOTFORMERGE] aopen,smm,i82801,e7505 Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/romstage.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c A src/southbridge/intel/i82801dx/early_init.c D src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 20 files changed, 301 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/69759/1 diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 999ea4d..b33bf03 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -4,4 +4,3 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select SSE2 - select NO_SMM diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 5d60d21..752656c 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,5 +1,6 @@ subdirs-y += ../common ramstage-y += model_f2x_init.c +ramstage-y += mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index a228229..2fc7360 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -2,9 +2,6 @@ #include <device/device.h> #include <cpu/cpu.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/mtrr.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/common/common.h> #include <cpu/x86/cache.h> @@ -32,36 +29,3 @@ .ops = &cpu_dev_ops, .id_table = cpu_table, }; - -/* Parallel MP initialization support. */ -static void pre_mp_init(void) -{ - const void *patch = intel_microcode_find(); - intel_microcode_load_unlocked(patch); - - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static int get_cpu_count(void) -{ - return CONFIG_MAX_CPUS; -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - *microcode = intel_microcode_find(); - *parallel = !intel_ht_supported(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_microcode_info = get_microcode_info, -}; - -void mp_init_cpus(struct bus *cpu_bus) -{ - mp_init_with_smm(cpu_bus, &mp_ops); -} diff --git a/src/cpu/intel/model_f2x/mp_init.c b/src/cpu/intel/model_f2x/mp_init.c new file mode 100644 index 0000000..c8d38c5 --- /dev/null +++ b/src/cpu/intel/model_f2x/mp_init.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/intel/common/common.h> +#include <cpu/x86/legacy_save_state.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/mp.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <types.h> + +/* Parallel MP initialization support. */ +static void pre_mp_init(void) +{ + const void *patch = intel_microcode_find(); + intel_microcode_load_unlocked(patch); + + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + return CONFIG_MAX_CPUS; +} + +static void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = intel_microcode_find(); + *parallel = !intel_ht_supported(); +} + +static void pre_mp_smm_init(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ + smm_initiate_relocation(); +} + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + smm_open(); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + *smm_save_state_size = sizeof(legacy_smm_state_save_area_t); + printk(BIOS_DEBUG, "Save state size: 0x%zx bytes\n", *smm_save_state_size); +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +{ + legacy_smm_state_save_area_t *save_state; + u32 smbase = staggered_smbase; + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + save_state->smbase = smbase; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", save_state->smm_revision); + printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase); +} + +static void post_mp_init(void) +{ + smm_close(); + + /* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */ + global_smi_enable(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = pre_mp_smm_init, + /* .per_cpu_smm_trigger = smm_initiate_relocation, using default */ + .relocation_handler = relocation_handler, + .post_mp_init = post_mp_init, +}; + +void mp_init_cpus(struct bus *cpu_bus) +{ + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); +} diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index 4a54bc0..408ed7f 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -10,5 +10,7 @@ select NO_ECAM_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE + #select SMM_ASEG + select SMM_TSEG endif diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index b429c70..ed596c9 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -7,6 +7,11 @@ #ifndef NORTHBRIDGE_INTEL_E7505_E7505_H #define NORTHBRIDGE_INTEL_E7505_E7505_H +#include <types.h> + +size_t northbridge_get_tseg_size(void); +uintptr_t northbridge_get_tseg_base(void); + /************ D0:F0 ************/ // Register offsets #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ @@ -28,8 +33,6 @@ #define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ #define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ #define CKDIS 0x8C /* Clock disable register, 8 bit */ -#define SMRAMC 0x9D -#define ESMRAMC 0x9E #define APSIZE 0xB4 #define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ #define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ @@ -38,6 +41,22 @@ #define DVNP 0xE0 /* Device Not Present, 16 bit */ #define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ +#define SMRAMC 0x9D +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define G_SMRAME (1 << 3) +#define D_LCK (1 << 4) +#define D_CLS (1 << 5) +#define D_OPEN (1 << 6) + +#define ESMRAMC 0x9E +#define T_EN (1 << 0) +#define TSEG_SZ_128K (0 << 1) +#define TSEG_SZ_256K (1 << 1) +#define TSEG_SZ_512K (2 << 1) +#define TSEG_SZ_1M (3 << 1) +#define TSEG_SZ_MASK TSEG_SZ_1M +#define H_SMRAME (1 << 7) + // CAS# Latency bits in the DRAM Timing (DRT) register #define DRT_CAS_2_5 (0<<4) #define DRT_CAS_2_0 (1<<4) diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b1ac3d1..8b2577a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -6,34 +6,90 @@ #include <device/pci_ops.h> #include <arch/romstage.h> #include <cbmem.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <program_loading.h> #include "e7505.h" -void *cbmem_top_chipset(void) +#define HOST_BRIDGE PCI_DEV(0, 0, 0) + +static uintptr_t top_of_low_ram(void) { - const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; /* This is at 128 MiB boundary. */ - tolm = pci_read_config16(mch, TOLM) >> 11; + tolm = pci_read_config16(HOST_BRIDGE, TOLM) >> 11; tolm <<= 27; - - return (void *)tolm; + return tolm; } -void northbridge_write_smram(u8 smram); - -void northbridge_write_smram(u8 smram) +size_t northbridge_get_tseg_size(void) { - const pci_devfn_t mch = PCI_DEV(0, 0, 0); - pci_write_config8(mch, SMRAMC, smram); + const uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); + + if (!(esmramc & T_EN)) + return 0; + + switch ((esmramc & TSEG_SZ_MASK) >> 1) { + case 0: + return 128 * KiB; + case 1: + return 256 * KiB; + case 2: + return 512 *KiB; + case 3: + default: + return 1 * MiB; + } +} + +uintptr_t northbridge_get_tseg_base(void) +{ + uintptr_t tolm = top_of_low_ram(); + + /* subtract TSEG size */ + tolm -= northbridge_get_tseg_size(); + return tolm; +} + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); +} + +void *cbmem_top_chipset(void) +{ + return (void *)northbridge_get_tseg_base(); +} + +void smm_open(void) +{ + /* Set D_OPEN */ + pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG); +} + +void smm_close(void) +{ + /* Clear D_OPEN */ + pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG); +} + +void smm_lock(void) +{ + /* + * LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + + pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* * Choose to NOT set ROM as WP cacheable here. * Timestamps indicate the CPU this northbridge code is @@ -43,11 +99,6 @@ pcf->skip_common_mtrr = 1; - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); + /* Cache RAM as WB from 0 -> TOLM. */ + postcar_frame_add_mtrr(pcf, top_of_low_ram(), CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08ac122..cc7f85d 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -42,6 +42,9 @@ ram_resource_kb(dev, idx++, 0, tolmk); mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); + uintptr_t tseg_memory_base = northbridge_get_tseg_base(); + size_t tseg_memory_size = northbridge_get_tseg_size(); + mmio_resource_kb(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB); ASSERT(tom == remapbase); upper_ram_end(dev, idx++, remaplimit); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 5387d4d..2b81d37 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1687,6 +1687,8 @@ return !!(dword & DRC_DONE); } +#define HOST_BRIDGE PCI_DEV(0, 0, 0) + void sdram_initialize(void) { static const struct mem_controller memctrl[] = { @@ -1714,5 +1716,9 @@ timestamp_add_now(TS_INITRAM_END); } + + if (CONFIG(SMM_TSEG)) + pci_write_config8(HOST_BRIDGE, ESMRAMC, TSEG_SZ_1M | T_EN); + printk(BIOS_DEBUG, "SDRAM is up.\n"); } diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index df10f9d..d997ee1 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -8,10 +8,9 @@ void mainboard_romstage_entry(void) { - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* FIXME: Keep until flashed bootblock has these. */ i82801dx_early_init(); + i82801dx_lpc_setup(); sdram_initialize(); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 20926e5..8309d12 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -56,7 +56,7 @@ */ smi_en = 0; /* reset SMI enables */ - smi_en |= TCO_EN; + // smi_en |= TCO_EN; smi_en |= APMC_EN; if (CONFIG(DEBUG_PERIODIC_SMI)) smi_en |= PERIODIC_EN; diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 98c1a47..391a59f 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -3,7 +3,9 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index c352e3e..5db4537 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -2,6 +2,11 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += early_init.c + ramstage-y += i82801dx.c ramstage-y += ac97.c ramstage-y += fadt.c @@ -10,8 +15,6 @@ ramstage-y += usb.c ramstage-y += usb2.c -romstage-y += early_smbus.c - -bootblock-y += bootblock.c +smm-y += smihandler.c endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index 6cda0a8..cbc12dd 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -3,9 +3,16 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include "i82801dx.h" + void bootblock_early_southbridge_init(void) { /* Set FWH IDs for 2 MB flash part. */ if (CONFIG_ROM_SIZE == 0x200000) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111); + + + /* Setup decode ports and LPC I/F enables. */ + i82801dx_early_init(); + i82801dx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801dx/early_init.c b/src/southbridge/intel/i82801dx/early_init.c new file mode 100644 index 0000000..2ed7aa3 --- /dev/null +++ b/src/southbridge/intel/i82801dx/early_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/smbus_host.h> +#include <device/pci_ops.h> +#include "i82801dx.h" + +void i82801dx_early_init(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + pci_write_config32(dev, GPIO_BASE, GPIOBASE_ADDR | 1); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + if (ENV_RAMINIT) + enable_smbus(); +} + +void i82801dx_lpc_setup(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. + * We also need to set the value for LPC I/F Enables Register. + */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); +} diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c deleted file mode 100644 index 76ef1b8..0000000 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/smbus_host.h> -#include "i82801dx.h" - -void i82801dx_early_init(void) -{ - enable_smbus(); -} diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index e12b2ca..fdb7fb3 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -1,20 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <acpi/acpi.h> -#include <version.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0x0 /* ACPI mode only */ -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x0 -#define ACPI_DISABLE 0xAA -#define ACPI_ENABLE 0x55 -#define S4_BIOS 0x77 -#define GNVS_UPDATE 0xea +#include <cpu/x86/smm.h> +#include <device/pci_ops.h> void acpi_fill_fadt(acpi_fadt_t *fadt) { @@ -24,9 +12,8 @@ if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->pstate_cnt = PST_CONTROL; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; } fadt->pm1a_evt_blk = pmbase; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 7946bd5..4c1366e 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -1,26 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. - * fb1 code is what we want, fb2 structure is needed however. - * so we need to get fb1 code for 82801dbm into fb2 structure. - */ -/* What I did: took the 80801er stuff from fb2, verify it against the - * db stuff in fb1, and made sure it was right. - */ - #ifndef I82801DX_H #define I82801DX_H #include <acpi/acpi.h> - -#if !defined(__ASSEMBLER__) - #include <device/device.h> void i82801dx_enable(struct device *dev); void i82801dx_early_init(void); - -#endif +void i82801dx_lpc_setup(void); #define DEBUG_PERIODIC_SMIS 0 @@ -54,8 +42,7 @@ #define PCICMD 0x04 #define PMBASE 0x40 -#define PMBASE_ADDR 0x0400 -#define DEFAULT_PMBASE PMBASE_ADDR +#define DEFAULT_PMBASE 0x0400 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E @@ -153,8 +140,8 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 -#define TCOBASE 0x60 /* TCO Base Address Register */ -#define TCO1_CNT 0x08 /* TCO1 Control Register */ +/* TCO1 Control Register */ +#define TCO1_CNT 0x68 #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index c844735..d914335 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -4,6 +4,7 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -22,20 +23,6 @@ typedef struct southbridge_intel_i82801dx_config config_t; /** - * Enable ACPI I/O range. - * - * @param dev PCI device with ACPI and PM BAR's - */ -static void i82801dx_enable_acpi(struct device *dev) -{ - /* Set ACPI base address (I/O space). */ - pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - - /* Enable ACPI I/O range decode and ACPI power management. */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); -} - -/** * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers @@ -155,12 +142,6 @@ outl(reg32, pmbase + 0x04); } -static void gpio_init(struct device *dev) -{ - /* This should be done in romstage.c already */ - pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); -} static void i82801dx_rtc_init(struct device *dev) { @@ -182,6 +163,15 @@ pci_write_config8(dev, RTC_CONF, 0x04); } +static void i82801dx_set_acpi_mode(struct device *dev) +{ + if (!acpi_is_wakeup_s3()) { + apm_control(APM_CNT_ACPI_DISABLE); + } else { + apm_control(APM_CNT_ACPI_ENABLE); + } +} + static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) { u16 reg16; @@ -197,17 +187,6 @@ pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(struct device *dev) -{ - /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. - * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. - * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. - * We also need to set the value for LPC I/F Enables Register. - */ - pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN, 0x300F); -} - /* ICH4 does not mention HPET in the docs, but * all ICH3 and ICH4 do have HPETs built in. */ @@ -247,7 +226,6 @@ static void lpc_init(struct device *dev) { - i82801dx_enable_acpi(dev); /* IO APIC initialization. */ i82801dx_enable_ioapic(dev); @@ -259,9 +237,6 @@ /* Setup power options. */ i82801dx_power_options(dev); - /* Set the state of the GPIO lines. */ - gpio_init(dev); - /* Initialize the real time clock. */ i82801dx_rtc_init(dev); @@ -271,13 +246,12 @@ /* Initialize ISA DMA. */ isa_dma_init(); - /* Setup decode ports and LPC I/F enables. */ - i82801dx_lpc_decode_en(dev); - /* Initialize the High Precision Event Timers */ enable_hpet(dev); setup_i8259(); + + i82801dx_set_acpi_mode(dev); } static void i82801dx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c new file mode 100644 index 0000000..050567a --- /dev/null +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/pmutil.h> +#include "i82801dx.h" + +void southbridge_smi_monitor(void) +{ +} + +void southbridge_finalize_all(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: sb/intel/i82801dx: Improve LPC device early init
by Kyösti Mälkki (Code Review) 17 Nov '22

17 Nov '22

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69671 ) Change subject: sb/intel/i82801dx: Improve LPC device early init ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Please check https://review.coreboot. […] Locally, I was actually building with fallback/normal method so bootblock change did not get build-test here locally. I don't think I did out-of-order cherry-picking either, so I am not sure how jenkins was happy with this before. Seems as if jenkins did CHROMEOS=y build only https://qa.coreboot.org/job/coreboot-gerrit/222382/ -- To view, visit https://review.coreboot.org/c/coreboot/+/69671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Gerrit-Change-Number: 69671 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:29:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX
by Arthur Heymans (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69743 to look at the new patch set (#4). Change subject: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX ...................................................................... arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX Clang generated code uses this for zero initialized variables. Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/eabi_compat.c 1 file changed, 37 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69743/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Gerrit-Change-Number: 69743 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: sb/intel/i82801dx/bootblock.c: Include "i82801dx.h"
by Kyösti Mälkki (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Arthur Heymans, Elyes Haouas. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69717 ) Change subject: sb/intel/i82801dx/bootblock.c: Include "i82801dx.h" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58ff31ab98c4310478cf3bbe8aecce4000ac8205 Gerrit-Change-Number: 69717 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:23:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Update ME HFSTS register definition
by Rizwan Qureshi (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Paul Menzel. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69286 ) Change subject: soc/intel/alderlake: Update ME HFSTS register definition ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69286/comment/f01ed25a_98123245 PS4, Line 15: TEST= build and boot nivviks platform > nit: no space. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 5 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:11:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Update ME HFSTS register definition
by Rizwan Qureshi (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Rizwan Qureshi, Paul Menzel. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Sridhar Siricilla, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69286 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Update ME HFSTS register definition ...................................................................... soc/intel/alderlake: Update ME HFSTS register definition Update Alder Lake CSME HFSTS registers definitions as per Intel doc #627331 revision 1.0.0, section 3.4.8. Follow up CLs will use the bit definitions for performing various checks. TEST=build and boot nivviks platform Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 --- M src/soc/intel/alderlake/include/soc/me.h M src/soc/intel/alderlake/me.c 2 files changed, 26 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/69286/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 5 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchsc...
by Tyler Wang (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli. Hello Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69749 to look at the new patch set (#2). Change subject: mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen ...................................................................... mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen BUG=b:235919755 Test=Check error message "Exposing GPIOs in Power Resource and _CRS" not show in firmware log. Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I21a47adde48555098d041b94d483cad308bdb717 --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/69749/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a47adde48555098d041b94d483cad308bdb717 Gerrit-Change-Number: 69749 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX
by build bot (Jenkins) (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69743 ) Change subject: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX ...................................................................... Patch Set 3: (5 comments) File src/arch/arm/eabi_compat.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163919): https://review.coreboot.org/c/coreboot/+/69743/comment/413e820e_7ff9bf82 PS3, Line 29: __attribute((alias ("__aeabi_memcpy"))); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163919): https://review.coreboot.org/c/coreboot/+/69743/comment/11de851e_44b00a46 PS3, Line 32: __attribute((alias ("__aeabi_memcpy"))); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163919): https://review.coreboot.org/c/coreboot/+/69743/comment/ccb71614_1569f37e PS3, Line 49: __attribute((alias ("__aeabi_memclr"))); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163919): https://review.coreboot.org/c/coreboot/+/69743/comment/229fbfba_c99f5c22 PS3, Line 52: __attribute((alias ("__aeabi_memclr"))); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163919): https://review.coreboot.org/c/coreboot/+/69743/comment/a96f381e_98d2d2e3 PS3, Line 58: __aeabi_memset (dest, n, 0); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/69743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Gerrit-Change-Number: 69743 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:08:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchsc...
by Tyler Wang (Code Review) 17 Nov '22

17 Nov '22

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69749 ) Change subject: mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen ...................................................................... mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen BUG=b:235919755 Test=Check error message "Exposing GPIOs in Power Resource and _CRS" not appear in firmware log. Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I21a47adde48555098d041b94d483cad308bdb717 --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/69749/1 diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 6db23d4..0687bf5 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -202,6 +202,7 @@ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "12" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x40 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a47adde48555098d041b94d483cad308bdb717 Gerrit-Change-Number: 69749 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: google/*/*/sdram_configs.c: Add function argument
by Arthur Heymans (Code Review) 17 Nov '22

17 Nov '22

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69748 ) Change subject: google/*/*/sdram_configs.c: Add function argument ...................................................................... google/*/*/sdram_configs.c: Add function argument A function declaration without a prototype is deprecated in all versions of C. Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/foster/sdram_configs.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/nyan/sdram_configs.c M src/mainboard/google/nyan_big/sdram_configs.c M src/mainboard/google/nyan_blaze/sdram_configs.c M src/mainboard/google/smaug/sdram_configs.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/sdram_configs.c 9 files changed, 22 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/69748/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158 Gerrit-Change-Number: 69748 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022