coreboot-gerrit November 2022

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[S] Change in coreboot[master]: cpu/x86/Kconfig: Drop unused Kconfig symbol
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69336 ) Change subject: cpu/x86/Kconfig: Drop unused Kconfig symbol ...................................................................... cpu/x86/Kconfig: Drop unused Kconfig symbol Change-Id: Id50ebecdaddcce426b15d535afcc3e755f2c5a35 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69336 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/cpu/x86/Kconfig 1 file changed, 13 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 1852e78..2253e18 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -159,13 +159,6 @@ This option determines the size of the stack within the SMM handler modules. -config SMM_STUB_STACK_SIZE - hex - default 0x400 - help - This option determines the size of the stack within the SMM handler - modules. - endif config SMM_LAPIC_REMAP_MITIGATION -- To view, visit https://review.coreboot.org/c/coreboot/+/69336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id50ebecdaddcce426b15d535afcc3e755f2c5a35 Gerrit-Change-Number: 69336 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/amd/pi/Kconfig: Drop unused Kconfig symbol
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69333 ) Change subject: nb/amd/pi/Kconfig: Drop unused Kconfig symbol ...................................................................... nb/amd/pi/Kconfig: Drop unused Kconfig symbol Change-Id: I713b3fed3fc6d55139badec93a67943dd93ced2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69333 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/northbridge/amd/pi/Kconfig 1 file changed, 14 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 6ae1c3a..61d368c 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -37,8 +37,4 @@ hex default 0xc0000 -config NUM_OF_IOAPICS - int - default 3 - endif # NORTHBRIDGE_AMD_PI -- To view, visit https://review.coreboot.org/c/coreboot/+/69333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I713b3fed3fc6d55139badec93a67943dd93ced2a Gerrit-Change-Number: 69333 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common/block/sgx/Kconfig: Add missing default symbol
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69332 ) Change subject: soc/intel/common/block/sgx/Kconfig: Add missing default symbol ...................................................................... soc/intel/common/block/sgx/Kconfig: Add missing default symbol default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE value is missing by accident for SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB. Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69332 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/sgx/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 92959ff..d9f941d 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -30,6 +30,7 @@ default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB default 128 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB default 64 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB + default 32 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB choice prompt "PRMRR size" -- To view, visit https://review.coreboot.org/c/coreboot/+/69332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4 Gerrit-Change-Number: 69332 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/pi/def_callouts.c: Fix log messages
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69623 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/common/pi/def_callouts.c: Fix log messages ...................................................................... soc/amd/common/pi/def_callouts.c: Fix log messages It is no longer necessary to explicitly add "Warning" in front of BIOS_WARNING message. Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/pi/def_callouts.c 1 file changed, 19 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/pi/def_callouts.c b/src/soc/amd/common/pi/def_callouts.c index 223abe3..ee70951 100644 --- a/src/soc/amd/common/pi/def_callouts.c +++ b/src/soc/amd/common/pi/def_callouts.c @@ -147,7 +147,7 @@ AGESA_STATUS __weak platform_PcieSlotResetControl(uint32_t Func, uintptr_t Data, void *ConfigPtr) { - printk(BIOS_WARNING, "Warning - AGESA callout: %s not supported\n", + printk(BIOS_WARNING, "AGESA callout: %s not supported\n", __func__); return AGESA_UNSUPPORTED; } @@ -231,7 +231,7 @@ AGESA_STATUS agesa_WaitForAllApsFinished(uint32_t Func, uintptr_t Data, void *ConfigPtr) { - printk(BIOS_WARNING, "Warning - AGESA callout: %s not supported\n", + printk(BIOS_WARNING, "AGESA callout: %s not supported\n", __func__); AGESA_STATUS Status = AGESA_UNSUPPORTED; @@ -240,7 +240,7 @@ AGESA_STATUS agesa_IdleAnAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) { - printk(BIOS_WARNING, "Warning - AGESA callout: %s no supported\n", + printk(BIOS_WARNING, "AGESA callout: %s not supported\n", __func__); AGESA_STATUS Status = AGESA_UNSUPPORTED; -- To view, visit https://review.coreboot.org/c/coreboot/+/69623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e Gerrit-Change-Number: 69623 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69324 ) Change subject: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode As per Intel doc #627331 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, 1 and 2 are already checked. Add a check for 3 as well. Also add logs for each individual criteria so it's easy to tell why the overall Manufacturing Mode is set or not. BUG=b:255462682 TEST=On a nivviks which has not gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO After: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO [DEBUG] ME: FPFs Committed : NO [DEBUG] ME: Manufacturing Vars Locked : NO On an anahera which has gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES After: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES [DEBUG] ME: FPFs Committed : YES [DEBUG] ME: Manufacturing Vars Locked : YES Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69324 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/me.c 1 file changed, 76 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index a965807..4937ced 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -102,11 +102,25 @@ base, limit); } - /* If EOM is disabled, but CSE RO is not write protected, log error */ + /* + * If manufacturing mode is disabled, but CSE RO is not write protected, + * log error. + */ if (!mfg_mode && !cse_ro_wp_en) printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); } +static bool is_manuf_mode(union me_hfsts1 hfsts1, union me_hfsts6 hfsts6) +{ + /* + * ME manufacturing mode is disabled if the descriptor is locked, fuses + * are programmed and manufacturing variables are locked. + */ + return !((hfsts1.fields.mfg_mode == 0) && + (hfsts6.fields.fpf_soc_lock == 1) && + (hfsts6.fields.manuf_lock == 1)); +} + static void dump_me_status(void *unused) { union me_hfsts1 hfsts1; @@ -115,6 +129,7 @@ union me_hfsts4 hfsts4; union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; + bool manuf_mode; if (!is_cse_enabled()) return; @@ -133,19 +148,19 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); - /* - * Lock Descriptor, and Fuses must be programmed on a - * production system to indicate ME Manufacturing mode is disabled. - */ + manuf_mode = is_manuf_mode(hfsts1, hfsts6); printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - ((hfsts1.fields.mfg_mode == 0) && - (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); + manuf_mode ? "YES" : "NO"); /* * The SPI Protection Mode bit reflects SPI descriptor * locked(0) or unlocked(1). */ printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", hfsts1.fields.mfg_mode ? "NO" : "YES"); + printk(BIOS_DEBUG, "ME: FPFs Committed : %s\n", + hfsts6.fields.fpf_soc_lock ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Vars Locked : %s\n", + hfsts6.fields.manuf_lock ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", @@ -180,7 +195,7 @@ hfsts6.fields.txt_support ? "YES" : "NO"); if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) - log_me_ro_write_protection_info(!!hfsts1.fields.mfg_mode); + log_me_ro_write_protection_info(manuf_mode); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/69324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Gerrit-Change-Number: 69324 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Update ME HFSTS register definition
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69286 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Update ME HFSTS register definition ...................................................................... soc/intel/alderlake: Update ME HFSTS register definition Update Alder Lake CSME HFSTS registers definitions as per Intel doc #627331 revision 1.0.0, section 3.4.8. Follow up CLs will use the bit definitions for performing various checks. TEST=build and boot nivviks platform Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69286 Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/include/soc/me.h M src/soc/intel/alderlake/me.c 2 files changed, 30 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/me.h b/src/soc/intel/alderlake/include/soc/me.h index 8eea095..e094af6 100644 --- a/src/soc/intel/alderlake/include/soc/me.h +++ b/src/soc/intel/alderlake/include/soc/me.h @@ -35,11 +35,9 @@ struct { u32 reserved_0: 4; u32 fw_sku: 3; - u32 reserved_7: 2; - u32 reserved_9: 2; - u32 resered_11: 3; - u32 resered_14: 16; - u32 reserved_30: 2; + u32 reserved_7_10: 4; + u32 rpmc_status: 3; + u32 resered_14_31: 18; } __packed fields; }; #endif /* _ALDERLAKE_ME_H_ */ diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index 31b09da..a965807 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -23,7 +23,8 @@ uint32_t me_power_gate : 1; uint32_t ipu_needed : 1; uint32_t forced_safe_boot : 1; - uint32_t rsvd1 : 2; + uint32_t rsvd1 : 1; + uint32_t cse_to_be_disabled : 1; uint32_t listener_change : 1; uint32_t status_data : 8; uint32_t current_pmevent : 4; @@ -58,10 +59,7 @@ uint32_t acm_done_sts : 1; uint32_t timeout_count : 7; uint32_t scrtm_indicator : 1; - uint32_t inc_boot_guard_acm : 4; - uint32_t inc_key_manifest : 4; - uint32_t inc_boot_policy : 4; - uint32_t rsvd0 : 2; + uint32_t rsvd0 : 14; uint32_t start_enforcement : 1; } __packed fields; }; @@ -78,9 +76,8 @@ uint32_t error_enforce_policy : 2; uint32_t measured_boot : 1; uint32_t verified_boot : 1; - uint32_t boot_guard_acmsvn : 4; - uint32_t kmsvn : 4; - uint32_t bpmsvn : 4; + uint32_t rsvd1 : 11; + uint32_t manuf_lock : 1; uint32_t key_manifest_id : 4; uint32_t boot_policy_status : 1; uint32_t error : 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 6 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/starlabs/starbook/kbl: Drop redundant option code
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69522 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/kbl: Drop redundant option code ...................................................................... mb/starlabs/starbook/kbl: Drop redundant option code Commit 9bbc039c457774dbeb44ea37ecc6507144d49b61 ("soc/intel/skylake: Hook up FSP hyper-threading setting to option API") already hooks up the `hyper_threading` CMOS option in SoC code, so there's no need to do it from mainboard code. Change-Id: I602452266a8465cced12454f800ea023f382ba6f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69522 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/kbl/romstage.c 1 file changed, 20 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c index 098f753..72fe9ed 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c @@ -19,8 +19,4 @@ mem_cfg->MemorySpdPtr00 = spd_cbfs_map(6); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; - - const uint8_t ht = get_uint_option("hyper_threading", - mupd->FspmConfig.HyperThreading); - mupd->FspmConfig.HyperThreading = ht; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I602452266a8465cced12454f800ea023f382ba6f Gerrit-Change-Number: 69522 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Fix CMOS options
by Felix Held (Code Review) 17 Nov '22

17 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69491 ) Change subject: mb/supermicro/x11-lga1151-series: Fix CMOS options ...................................................................... mb/supermicro/x11-lga1151-series: Fix CMOS options The `hyper_threading` CMOS option was hooked up to the wrong enumeration and lacked a default value in `cmos.default`. Thus, use the correct enum for the `hyper_threading` option, remove the now-unused "backwards" enum and provide a default value in `cmos.default`. Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69491 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/cmos.default M src/mainboard/supermicro/x11-lga1151-series/cmos.layout 2 files changed, 23 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.default b/src/mainboard/supermicro/x11-lga1151-series/cmos.default index d564953..a93c147 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/cmos.default +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.default @@ -1,3 +1,4 @@ boot_option=Fallback debug_level=Debug +hyper_threading=Enable power_on_after_fail=Enable diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout index 46703e6..07f8233 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout @@ -17,7 +17,7 @@ # ----------------------------------------------------------------- # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 1 hyper_threading # ----------------------------------------------------------------- # coreboot config options: southbridge @@ -38,8 +38,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency -- To view, visit https://review.coreboot.org/c/coreboot/+/69491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936 Gerrit-Change-Number: 69491 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX
by Arthur Heymans (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69743 to look at the new patch set (#5). Change subject: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX ...................................................................... arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX Clang generated code uses this for zero initialized variables. Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/eabi_compat.c 1 file changed, 37 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69743/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Gerrit-Change-Number: 69743 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistent
by Werner Zeh (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Paul Menzel, Jan Samek. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69718 ) Change subject: drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistent ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib63b93d52aad220d17f1f4ee0d47a949933ec26d Gerrit-Change-Number: 69718 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:58:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022