coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Werner Zeh (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Paul Menzel, Jan Samek. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69543 ) Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 4 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:57:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot/vboot_common: Fix vboot_save_data() code exclusion guard
by Jakub Czapiga (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69761 to look at the new patch set (#2). Change subject: vboot/vboot_common: Fix vboot_save_data() code exclusion guard ...................................................................... vboot/vboot_common: Fix vboot_save_data() code exclusion guard Compilers are not optimizing-out code correctly. This patch fixes incorrect behavior by splitting if statement and extracting code to another function, this allowing for better code size optimization and reduction of undefined references. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 --- M src/security/vboot/vboot_common.c 1 file changed, 32 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69761/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Gerrit-Change-Number: 69761 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: google/*/*/sdram_configs.c: Add function argument
by Elyes Haouas (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner, Arthur Heymans, Martin Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69748 ) Change subject: google/*/*/sdram_configs.c: Add function argument ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158 Gerrit-Change-Number: 69748 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:54:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot/vboot_common: Fix vboot_save_data() code exclusion guard
by build bot (Jenkins) (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69761 ) Change subject: vboot/vboot_common: Fix vboot_save_data() code exclusion guard ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163936): https://review.coreboot.org/c/coreboot/+/69761/comment/29b7eb2f_2fc56808 PS1, Line 10: incorrect behavior by spliting if statement and extracting code to 'spliting' may be misspelled - perhaps 'splitting'? -- To view, visit https://review.coreboot.org/c/coreboot/+/69761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Gerrit-Change-Number: 69761 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:52:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot/vboot_logic: Fix hash digest size and padding
by Jakub Czapiga (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner, Yu-Ping Wu. Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69762 ) Change subject: vboot/vboot_logic: Fix hash digest size and padding ...................................................................... vboot/vboot_logic: Fix hash digest size and padding vboot_save_hash() in ChromeOS EC implementation expects hash digest to be of fixed size - maximum supported digest size. If data is not long enough, it should be padded with zeros. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a --- M src/security/vboot/vboot_logic.c 1 file changed, 30 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/69762/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 98a044c..b979328 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -337,10 +337,23 @@ printk(BIOS_INFO, "Phase 4\n"); if (CONFIG(VBOOT_CBFS_INTEGRATION)) { struct vb2_hash *metadata_hash; + rv = vb2api_get_metadata_hash(ctx, &metadata_hash); - if (rv == VB2_SUCCESS) - rv = handle_digest_result(metadata_hash->raw, - vb2_digest_size(metadata_hash->algo)); + + if (rv == VB2_SUCCESS) { + uint8_t hash_digest[VBOOT_MAX_HASH_SIZE]; + const size_t hash_digest_sz = sizeof(hash_digest); + const size_t metadata_hash_digest_sz = + vb2_digest_size(metadata_hash->algo); + + if (metadata_hash_digest_sz > hash_digest_sz) + die("Metadata hash digest size is too big"); + + memset(hash_digest, 0, hash_digest_sz); + memcpy(hash_digest, metadata_hash->raw, metadata_hash_digest_sz); + + rv = handle_digest_result(hash_digest, hash_digest_sz); + } } else { struct region_device fw_body; rv = vboot_locate_firmware(ctx, &fw_body); -- To view, visit https://review.coreboot.org/c/coreboot/+/69762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Gerrit-Change-Number: 69762 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vboot/vboot_common: Fix vboot_save_data() code exclusion guard
by Jakub Czapiga (Code Review) 17 Nov '22

17 Nov '22

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69761 ) Change subject: vboot/vboot_common: Fix vboot_save_data() code exclusion guard ...................................................................... vboot/vboot_common: Fix vboot_save_data() code exclusion guard Compilers are not optimizing-out code correctly. This patch fixes incorrect behavior by spliting if statement and extracting code to another function, this allowing for better code size optimization and reduction of undefined references. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 --- M src/security/vboot/vboot_common.c 1 file changed, 32 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69761/1 diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index dd611d1..3c4957a 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -9,26 +9,33 @@ #include "antirollback.h" -void vboot_save_data(struct vb2_context *ctx) +static void save_secdata(struct vb2_context *ctx) { - if (!verification_should_run() && !(ENV_ROMSTAGE && CONFIG(VBOOT_EARLY_EC_SYNC)) - && (ctx->flags - & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | VB2_CONTEXT_SECDATA_KERNEL_CHANGED))) - die("TPM writeback in " ENV_STRING "?"); - - if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED && - (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED + && (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { printk(BIOS_INFO, "Saving secdata firmware\n"); antirollback_write_space_firmware(ctx); ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; } - if (ctx->flags & VB2_CONTEXT_SECDATA_KERNEL_CHANGED && - (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + if (ctx->flags & VB2_CONTEXT_SECDATA_KERNEL_CHANGED + && (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { printk(BIOS_INFO, "Saving secdata kernel\n"); antirollback_write_space_kernel(ctx); ctx->flags &= ~VB2_CONTEXT_SECDATA_KERNEL_CHANGED; } +} + +void vboot_save_data(struct vb2_context *ctx) +{ + if (!verification_should_run() && !(ENV_ROMSTAGE && CONFIG(VBOOT_EARLY_EC_SYNC))) { + if (ctx->flags + & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED + | VB2_CONTEXT_SECDATA_KERNEL_CHANGED)) + die("TPM writeback in " ENV_STRING "?"); + } else { + save_secdata(ctx); + } if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { printk(BIOS_INFO, "Saving nvdata\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/69761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Gerrit-Change-Number: 69761 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Raul Rangel, Jeff Daly, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Felix Held, Tim Chu. Hello Jeff Daly, Raul Rangel, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Felix Held, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69163 to look at the new patch set (#12). Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/postcar_loader.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/mrc_cache/mrc_cache.c M src/include/cbmem.h M src/lib/imd_cbmem.c M src/lib/prog_loaders.c M src/mainboard/emulation/qemu-power9/mainboard.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/uncore.c M src/soc/qualcomm/common/qclib.c 42 files changed, 68 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69163/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/69163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Gerrit-Change-Number: 69163 Gerrit-PatchSet: 12 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: [NOTFORMERGE] squashed intel pmutil ops
by build bot (Jenkins) (Code Review) 17 Nov '22

17 Nov '22

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[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505
by build bot (Jenkins) (Code Review) 17 Nov '22

17 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69759 ) Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505 ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/e7505/memmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163932): https://review.coreboot.org/c/coreboot/+/69759/comment/244f10cb_c9a15f21 PS1, Line 40: return 512 *KiB; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Nov 2022 12:37:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: [NOTFORMERGE] squashed intel pmutil ops
by Kyösti Mälkki (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69760 ) Change subject: [NOTFORMERGE] squashed intel pmutil ops ...................................................................... [NOTFORMERGE] squashed intel pmutil ops Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/include/arch/io_bitops.h M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/mainboard/asus/p2b/variants/p3b-f/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/samsung/lumpy/smihandler.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/security/intel/txt/romstage.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/quark/reg_access.c M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmclib.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c A src/southbridge/intel/common/tco.c M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/wakeup.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_usb.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 142 files changed, 921 insertions(+), 1,108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69760/1 diff --git a/src/arch/x86/include/arch/io_bitops.h b/src/arch/x86/include/arch/io_bitops.h new file mode 100644 index 0000000..ecf5e97 --- /dev/null +++ b/src/arch/x86/include/arch/io_bitops.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARCH_IO_BITOPS__ +#define __ARCH_IO_BITOPS__ + +#include <arch/io.h> +#include <types.h> + +static inline u32 io_rwc32(const u16 addr) +{ + u32 reg32 = inl(addr); + outl(reg32, addr); + return reg32; +} + +static inline u16 io_rwc16(const u16 addr) +{ + u16 reg16 = inw(addr); + outw(reg16, addr); + return reg16; +} + +static inline u8 io_rwc8(const u16 addr) +{ + u8 reg8 = inb(addr); + outb(reg8, addr); + return reg8; +} + +static inline void io_setbits32(const u16 addr, const u32 mask) +{ + outl(inl(addr) | mask, addr); +} + +static inline void io_setbits16(const u16 addr, const u16 mask) +{ + outw(inw(addr) | mask, addr); +} + +static inline void io_setbits8(const u16 addr, const u8 mask) +{ + outb(inb(addr) | mask, addr); +} + +static inline void io_clrbits32(const u16 addr, const u32 mask) +{ + outl(inl(addr) & ~mask, addr); +} + +static inline void io_clrbits16(const u16 addr, const u16 mask) +{ + outw(inw(addr) & ~mask, addr); +} + +static inline void io_clrbits8(const u8 addr, const u8 mask) +{ + outb(inb(addr) & ~mask, addr); +} + +static inline void io_clrsetbits32(const u16 addr, const u32 clr, const u32 set) +{ + u32 reg = inl(addr); + reg &= ~clr; + reg |= set; + outl(reg , addr); +} + +static inline void io_clrsetbits16(const u16 addr, const u16 clr, const u16 set) +{ + u16 reg = inw(addr); + reg &= ~clr; + reg |= set; + outw(reg , addr); +} + +static inline void io_clrsetbits8(const u16 addr, const u8 clr, const u8 set) +{ + u8 reg = inb(addr); + reg &= ~clr; + reg |= set; + outb(reg , addr); +} + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c index eba9e98..171b193 100644 --- a/src/mainboard/acer/aspire_vn7_572g/mainboard.c +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -126,9 +126,10 @@ /* Clear below events and go back to sleep */ /* Clear ABase PM1_STS - RW/1C set bits */ pmc_clear_pm1_status(); + /* Clear ABase GPE0_STS[127:96] - RW/1C set bits */ - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); + pm_rwc32(GPE0_STS(GPE_STD)); + /* Clear xHCI PM_CS[PME_Status] - RW/1C - and disable xHCI PM_CS[PME_En] */ pci_update_config16(PCH_DEV_XHCI, 0x74, ~0x100, 0x8000); diff --git a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c index d72d976..9acd518 100644 --- a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c +++ b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c @@ -23,7 +23,7 @@ */ void enable_spd(void) { - outb(0x6f, PM_IO_BASE + 0x37); + outb(0x6f, DEFAULT_PMBASE + 0x37); } /* @@ -32,5 +32,5 @@ */ void disable_spd(void) { - outb(0x67, PM_IO_BASE + 0x37); + outb(0x67, DEFAULT_PMBASE + 0x37); } diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 6fa95e8..a1a82ff 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -16,7 +16,6 @@ static u8 mainboard_smi_ec(void) { u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; /* Log this event */ if (cmd) @@ -27,9 +26,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + pm_setbits32(PM1_CNT, (0xf << 10)); break; } diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 9083a87..2f0dbe5 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -44,8 +44,6 @@ static uint8_t mainboard_smi_ec(void) { uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; /* Log this event */ if (cmd) @@ -56,9 +54,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); + pm_setbits32(PM1_CNT, SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); break; } diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 2f42b7d..9eda2c5 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -27,7 +27,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_setbits32(PM1_CNT, (0xf << 10)); break; } diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 05f14af..95b2428 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -26,7 +26,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_setbits32(PM1_CNT, (0xf << 10)); break; } @@ -42,7 +42,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_setbits32(PM1_CNT, (0xf << 10)); } } diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 358a92f..dc28b52 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -18,8 +18,6 @@ static uint8_t mainboard_smi_ec(void) { uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; /* Log this event */ if (cmd) @@ -30,9 +28,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); + pm_setbits32(PM1_CNT, SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); break; } diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 16a1b18..8fd7133 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -25,7 +25,6 @@ static u8 mainboard_smi_ec(void) { u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; /* Log this event */ if (cmd) @@ -36,9 +35,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, get_pmbase() + PM1_CNT); + pm_setbits32(PM1_CNT, (0xf << 10)); break; } diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 2584166..b9e6c5f 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -76,6 +76,6 @@ printk(BIOS_ERR, "EC critical_shutdown"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_setbits32(PM1_CNT, (0xf << 10)); } } diff --git a/src/mainboard/google/stout/smihandler.c b/src/mainboard/google/stout/smihandler.c index f6adbf9..ec7cd9a 100644 --- a/src/mainboard/google/stout/smihandler.c +++ b/src/mainboard/google/stout/smihandler.c @@ -21,7 +21,7 @@ case EC_SMI_LID_CLOSED: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_setbits32(PM1_CNT, (0xf << 10)); break; } diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index e953ccd..88cc159 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -43,8 +43,6 @@ static uint8_t mainboard_smi_ec(void) { uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; /* Log this event */ if (cmd) @@ -55,9 +53,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); + pm_setbits32(PM1_CNT, SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); break; } diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 7f279b2..2f58396 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -21,7 +21,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + pm_setbits32(PM1_CNT, (0xf << 10)); break; } diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 6e6948b..86e01b2 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -16,6 +16,7 @@ #include <cpu/intel/haswell/haswell.h> #include <drivers/intel/gma/opregion.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/tco.h> #include <types.h> #include "chip.h" @@ -403,12 +404,8 @@ /* Enable SCI to ACPI _GPE._L06 */ static void gma_enable_swsci(void) { - u16 reg16; - /* Clear DMISCI status */ - reg16 = inw(get_pmbase() + TCO1_STS); - reg16 &= DMISCI_STS; - outw(reg16, get_pmbase() + TCO1_STS); + tco_write16(TCO1_STS, tco_read16(TCO1_STS) & DMISCI_STS); /* Clear and enable ACPI TCO SCI */ enable_tco_sci(); diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index fb21d35..4d98fd3 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -15,6 +15,7 @@ #include <pc80/vga.h> #include <drivers/intel/gma/opregion.h> #include <types.h> +#include <southbridge/intel/common/tco.h> #include "chip.h" #include "ironlake.h" @@ -117,20 +118,14 @@ /* Enable SCI to ACPI _GPE._L06 */ static void gma_enable_swsci(void) { - u16 reg16; - /* clear DMISCI status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 &= DMISCI_STS; - outw(reg16, DEFAULT_PMBASE + TCO1_STS); + tco_write16(TCO1_STS, tco_read16(TCO1_STS) & DMISCI_STS); /* clear acpi tco status */ - outl(TCOSCI_STS, DEFAULT_PMBASE + GPE0_STS); + pm_write32(GPE0_STS, TCOSCI_STS); /* enable acpi tco scis */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(reg16, DEFAULT_PMBASE + GPE0_EN); + pm_setbits16(GPE0_EN, TCOSCI_EN); } static void gma_func0_init(struct device *dev) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index e3b0b33..aa40ffc 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3110,8 +3110,8 @@ /* Write back the S3 state to PM1_CNT to let the reset CPU know it also needs to take the s3 path. */ if (s3resume) - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) - | (SLP_TYP_S3 << 10)); + pm_write32(PM1_CNT, pm_read32(PM1_CNT) | (SLP_TYP_S3 << 10)); + mchbar_setbits32(0x1af0, 1 << 4); halt(); } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 3eed5cc..7a9c0c0 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -13,6 +13,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/tco.h> #include <types.h> #include "chip.h" @@ -565,20 +566,14 @@ /* Enable SCI to ACPI _GPE._L06 */ static void gma_enable_swsci(void) { - u16 reg16; - - /* Clear DMISCI status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 &= DMISCI_STS; - outw(reg16, DEFAULT_PMBASE + TCO1_STS); + /* clear DMISCI status */ + tco_write16(TCO1_STS, tco_read16(TCO1_STS) & DMISCI_STS); /* Clear ACPI TCO status */ - outl(TCOSCI_STS, DEFAULT_PMBASE + GPE0_STS); + pm_write32(GPE0_STS, TCOSCI_STS); /* Enable ACPI TCO SCIs */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(reg16, DEFAULT_PMBASE + GPE0_EN); + pm_setbits16(GPE0_EN, TCOSCI_EN); } static void gma_func0_init(struct device *dev) diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index e045c9d..cbed419 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -121,7 +121,7 @@ } /* FIXME: Clear SLP_TYP# */ - write_pmbase32(4, read_pmbase32(4) & ~(0x7 << 10)); + pm_write32(4, pm_read32(4) & ~(0x7 << 10)); intel_txt_run_sclean(); diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1c820c2..59e6471 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -163,7 +163,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() config_t *config = config_of_soc(); diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h index 98843d1..4580bfe 100644 --- a/src/soc/intel/alderlake/include/soc/pm.h +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -162,7 +162,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 9389322..80391ac 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -229,8 +229,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -250,12 +250,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 811c762..d601f93 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -98,7 +98,7 @@ const struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); - fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; + fadt->pm_tmr_blk = get_pmbase() + PM1_TMR; fadt->pm_tmr_len = 4; diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index c1dee0c..312dc59 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -244,7 +244,4 @@ /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); -/* STM Support */ -uint16_t get_pmbase(void); - #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index f474553..5c6622c 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -79,7 +79,7 @@ uint32_t soc_get_smi_status(uint32_t generic_sts) { if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) { - uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + uint16_t pm1_sts = pm_read16(PM1_STS); /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) @@ -154,8 +154,8 @@ { uintptr_t pmc_bar0 = soc_read_pmc_base(); - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); @@ -218,12 +218,6 @@ return rtc_failure; } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - void pmc_soc_set_afterg3_en(const bool on) { const uintptr_t gen_pmcon1 = soc_read_pmc_base() + GEN_PMCON1; diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 3f07a6b..7d2c310 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -9,6 +9,8 @@ #include <soc/lpc.h> #include <soc/spi.h> #include <soc/pm.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> static void program_base_addresses(void) { @@ -38,15 +40,6 @@ pci_write_config32(lpc_dev, GBASE, reg); } -static void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - static void spi_init(void) { void *scs = (void *)(SPI_BASE_ADDRESS + SCS); @@ -105,7 +98,7 @@ /* Early chipset initialization */ program_base_addresses(); - tco_disable(); + tco_timer_disable(); if (CONFIG(ENABLE_BUILTIN_COM1)) byt_config_com1_and_enable(); diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 64154db..2e72028 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -9,7 +9,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); fadt->sci_int = acpi_sci_irq(); diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index dc8a7fa..7757233 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -222,14 +222,15 @@ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 + +#define TCO_RLD 0x00 +#define TCO_STS 0x04 # define SECOND_TO_STS (1 << 17) # define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 +#define TCO1_CNT 0x08 # define TCO_LOCK (1 << 12) # define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 +#define TCO_TMR 0x10 /* I/O ports */ #define RST_CNT 0xcf9 @@ -253,7 +254,6 @@ } __packed; /* Power Management Utility Functions. */ -uint16_t get_pmbase(void); uint32_t clear_smi_status(void); uint16_t clear_pm1_status(void); uint32_t clear_tco_status(void); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index d001660..c64b451 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -12,14 +12,15 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <console/console.h> - +#include <security/vboot/vbnv.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <security/vboot/vbnv.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> -uint16_t get_pmbase(void) +uint16_t lpc_get_pmbase(void) { return pci_read_config16(PCI_DEV(0, PCU_DEV, 0), ABASE) & 0xfff8; } @@ -75,10 +76,7 @@ static uint32_t reset_smi_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl(pmbase + SMI_STS); - outl(smi_sts, pmbase + SMI_STS); - return smi_sts; + return pm_rwc32(SMI_STS); } uint32_t clear_smi_status(void) @@ -88,42 +86,27 @@ void enable_smi(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en |= mask; - outl(smi_en, pmbase + SMI_EN); + pm_setbits32(SMI_EN, mask); } void disable_smi(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en &= ~mask; - outl(smi_en, pmbase + SMI_EN); + pm_clrbits32(SMI_EN, mask); } void enable_pm1_control(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, pmbase + PM1_CNT); + pm_setbits32(PM1_CNT, mask); } void disable_pm1_control(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, pmbase + PM1_CNT); + pm_clrbits32(PM1_CNT, mask); } static uint16_t reset_pm1_status(void) { - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw(pmbase + PM1_STS); - outw(pm1_sts, pmbase + PM1_STS); - return pm1_sts; + return pm_rwc16(PM1_STS); } static uint16_t print_pm1_status(uint16_t pm1_sts) @@ -156,7 +139,7 @@ void enable_pm1(uint16_t events) { - outw(events, get_pmbase() + PM1_EN); + pm_write16(PM1_EN, events); } static uint32_t print_tco_status(uint32_t tco_sts) @@ -176,35 +159,19 @@ return tco_sts; } -static uint32_t reset_tco_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t tco_sts = inl(pmbase + TCO_STS); - uint32_t tco_en = inl(pmbase + TCO1_CNT); - - outl(tco_sts, pmbase + TCO_STS); - return tco_sts & tco_en; -} - uint32_t clear_tco_status(void) { - return print_tco_status(reset_tco_status()); + return print_tco_status(tco_reset_status()); } void enable_gpe(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en |= mask; - outl(gpe0_en, pmbase + GPE0_EN); + pm_setbits32(GPE0_EN, mask); } void disable_gpe(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~mask; - outl(gpe0_en, pmbase + GPE0_EN); + pm_clrbits32(GPE0_EN, mask); } void disable_all_gpe(void) @@ -214,10 +181,7 @@ static uint32_t reset_gpe_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl(pmbase + GPE0_STS); - outl(gpe_sts, pmbase + GPE0_STS); - return gpe_sts; + return pm_rwc32(GPE0_STS); } static uint32_t print_gpe_sts(uint32_t gpe_sts) @@ -269,10 +233,7 @@ static uint32_t reset_alt_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); - outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); - return alt_gpio_smi; + return pm_rwc32(ALT_GPIO_SMI); } static uint32_t print_alt_sts(uint32_t alt_gpio_smi) @@ -352,8 +313,8 @@ int platform_is_resuming(void) { - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(pm_read16(PM1_STS) & WAK_STS)) return 0; - return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; + return acpi_sleep_from_pm1(pm_read32(PM1_CNT)) == ACPI_S3; } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 658da2c..fddc282 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -15,6 +15,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> static struct chipset_power_state power_state; @@ -38,12 +40,14 @@ { struct chipset_power_state *ps = &power_state; - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); - ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); - ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + ps->pm1_sts = pm_read16(PM1_STS); + ps->pm1_en = pm_read16(PM1_EN); + ps->pm1_cnt = pm_read32(PM1_CNT); + ps->gpe0_sts = pm_read32(GPE0_STS); + ps->gpe0_en = pm_read32(GPE0_EN); + + ps->tco_sts = tco_read32(TCO1_STS); + ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); @@ -75,7 +79,7 @@ break; } /* Clear SLP_TYP. */ - outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + pm_write32(PM1_CNT, ps->pm1_cnt & ~SLP_TYP); } if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 20e1590..5f5198c 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -19,6 +19,8 @@ #include <soc/pm.h> #include <soc/nvs.h> #include <soc/device_nvs.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> int southbridge_io_trap_handler(int smif) { @@ -81,13 +83,12 @@ { uint32_t reg32; uint8_t slp_typ; - uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -144,7 +145,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -349,7 +350,7 @@ { uint32_t reg32; - reg32 = inl(get_pmbase() + SMI_EN); + reg32 = pm_read32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 3f3c53f..0e8e51b 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -10,6 +10,7 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/smm.h> +#include <southbridge/intel/common/pmbase.h> /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; @@ -27,10 +28,8 @@ if (CONFIG(ELOG)) southcluster_log_state(); - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); - smi_en = inl(get_pmbase() + SMI_EN); + smi_en = pm_read32(SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; @@ -48,7 +47,6 @@ static void smm_southcluster_route_gpios(void) { void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT); - const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; uint32_t alt_gpio_reg = 0; uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; int i; @@ -67,7 +65,7 @@ } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); - outl(alt_gpio_reg, alt_gpio_smi); + pm_write32(ALT_GPIO_SMI, alt_gpio_reg); } static void smm_southbridge_enable(uint16_t pm1_events) diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 545642f..d811c9f 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -14,6 +14,7 @@ #include <soc/msr.h> #include <soc/pm.h> #include <soc/spi.h> +#include <southbridge/intel/common/tco.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -49,15 +50,6 @@ pci_write_config32(lpc_dev, GBASE, reg); } -static void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - static void spi_init(void) { void *scs = (void *)(SPI_BASE_ADDRESS + SCS); @@ -114,8 +106,9 @@ /* Early chipset initialization */ program_base_addresses(); - tco_disable(); + tco_timer_disable(); } + void bootblock_soc_init(void) { report_fsp_output(); diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 64154db..2e72028 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -9,7 +9,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); fadt->sci_int = acpi_sci_irq(); diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 854d4b5..a7a8a1c 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -144,7 +144,7 @@ } /* Enable gpe bits in GPE0A_EN_REG */ - outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG); + pm_write32(GPE0A_EN_REG, gpe0a_en); #ifdef GPIO_DEBUG printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n", diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 6cb8d55..6bacdef 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -184,14 +184,15 @@ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 + +#define TCO_RLD 0x00 +#define TCO_STS 0x04 # define SECOND_TO_STS (1 << 17) # define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 +#define TCO1_CNT 0x08 # define TCO_LOCK (1 << 12) # define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 +#define TCO_TMR 0x10 #if !defined(__ASSEMBLER__) && !defined(__ACPI__) @@ -212,7 +213,6 @@ struct chipset_power_state *fill_power_state(void); /* Power Management Utility Functions. */ -uint16_t get_pmbase(void); uint32_t clear_smi_status(void); uint16_t clear_pm1_status(void); uint32_t clear_tco_status(void); diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index a69b85d..ca55230 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -5,6 +5,7 @@ #include <soc/pm.h> #include <device/mmio.h> #include <soc/iomap.h> +#include <southbridge/intel/common/pmbase.h> #define SUSPEND_CYCLE 1 #define RESUME_CYCLE 0 @@ -97,8 +98,8 @@ * On S3 resume re-initialize GPIO lines which were * configured for low power during S3 entry. */ - pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_sts = pm_read16(PM1_STS); + pm1_cnt = pm_read32(PM1_CNT); if (pm1_sts & WAK_STS) slp_type = acpi_sleep_from_pm1(pm1_cnt); diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index a880183..b7e57a9 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -11,14 +11,16 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <console/console.h> +#include <security/vboot/vbnv.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> #include <stdint.h> -#include <security/vboot/vbnv.h> -uint16_t get_pmbase(void) +uint16_t lpc_get_pmbase(void) { return pci_read_config16(PCI_DEV(0, PCU_DEV, 0), ABASE) & 0xfff8; } @@ -74,10 +76,7 @@ static uint32_t reset_smi_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl(pmbase + SMI_STS); - outl(smi_sts, pmbase + SMI_STS); - return smi_sts; + return pm_rwc32(SMI_STS); } uint32_t clear_smi_status(void) @@ -87,42 +86,27 @@ void enable_smi(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en |= mask; - outl(smi_en, pmbase + SMI_EN); + pm_setbits32(SMI_EN, mask); } void disable_smi(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en &= ~mask; - outl(smi_en, pmbase + SMI_EN); + pm_clrbits32(SMI_EN, mask); } void enable_pm1_control(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, pmbase + PM1_CNT); + pm_setbits32(PM1_CNT, mask); } void disable_pm1_control(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, pmbase + PM1_CNT); + pm_clrbits32(PM1_CNT, mask); } static uint16_t reset_pm1_status(void) { - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw(pmbase + PM1_STS); - outw(pm1_sts, pmbase + PM1_STS); - return pm1_sts; + return pm_rwc16(PM1_STS); } static uint16_t print_pm1_status(uint16_t pm1_sts) @@ -155,7 +139,7 @@ void enable_pm1(uint16_t events) { - outw(events, get_pmbase() + PM1_EN); + pm_write16(PM1_EN, events); } static uint32_t print_tco_status(uint32_t tco_sts) @@ -175,35 +159,19 @@ return tco_sts; } -static uint32_t reset_tco_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t tco_sts = inl(pmbase + TCO_STS); - uint32_t tco_en = inl(pmbase + TCO1_CNT); - - outl(tco_sts, pmbase + TCO_STS); - return tco_sts & tco_en; -} - uint32_t clear_tco_status(void) { - return print_tco_status(reset_tco_status()); + return print_tco_status(tco_reset_status()); } void enable_gpe(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en |= mask; - outl(gpe0_en, pmbase + GPE0_EN); + pm_setbits32(GPE0_EN, mask); } void disable_gpe(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~mask; - outl(gpe0_en, pmbase + GPE0_EN); + pm_clrbits32(GPE0_EN, mask); } void disable_all_gpe(void) @@ -213,10 +181,7 @@ static uint32_t reset_gpe_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl(pmbase + GPE0_STS); - outl(gpe_sts, pmbase + GPE0_STS); - return gpe_sts; + return pm_rwc32(GPE0_STS); } static uint32_t print_gpe_sts(uint32_t gpe_sts) @@ -268,10 +233,7 @@ static uint32_t reset_alt_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); - outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); - return alt_gpio_smi; + return pm_rwc32(ALT_GPIO_SMI); } static uint32_t print_alt_sts(uint32_t alt_gpio_smi) @@ -351,8 +313,8 @@ int platform_is_resuming(void) { - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(pm_read16(PM1_STS) & WAK_STS)) return 0; - return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; + return acpi_sleep_from_pm1(pm_read32(PM1_CNT)) == ACPI_S3; } diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index a1623e1..b72e78d 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -30,12 +30,13 @@ struct chipset_power_state *fill_power_state(void) { - power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); - power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); - power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + power_state.pm1_sts = pm_read16(PM1_STS); + power_state.pm1_en = pm_read16(PM1_EN); + power_state.pm1_cnt = pm_read32(PM1_CNT); + power_state.gpe0_sts = pm_read32(GPE0_STS); + power_state.gpe0_en = pm_read32(GPE0_EN); + + power_state.tco_sts = tco_read32(TCO1_STS); power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); @@ -74,7 +75,7 @@ } /* Clear SLP_TYP. */ - outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + pm_write32(PM1_CNT, ps->pm1_cnt & ~SLP_TYP); } if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 138dc33..a015700 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -16,6 +16,7 @@ #include <spi-generic.h> #include <stdint.h> #include <soc/gpio.h> +#include <southbridge/intel/common/pmbase.h> #include <smmstore.h> int southbridge_io_trap_handler(int smif) @@ -102,13 +103,12 @@ { uint32_t reg32; uint8_t slp_typ; - uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -175,7 +175,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -317,7 +317,7 @@ { uint32_t reg32; - reg32 = inl(get_pmbase() + SMI_EN); + reg32 = pm_read32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 3f3c53f..c4836d3 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -10,6 +10,7 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/smm.h> +#include <southbridge/intel/common/pmbase.h> /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; @@ -27,10 +28,7 @@ if (CONFIG(ELOG)) southcluster_log_state(); - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); - - smi_en = inl(get_pmbase() + SMI_EN); + smi_en = pm_read32(SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; @@ -48,7 +46,6 @@ static void smm_southcluster_route_gpios(void) { void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT); - const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; uint32_t alt_gpio_reg = 0; uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; int i; @@ -67,6 +64,7 @@ } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); + const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; outl(alt_gpio_reg, alt_gpio_smi); } diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 52fd364..91e384b 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -53,11 +53,12 @@ #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 -#define TCO1_CNT 0x60 + +#define TCO1_CNT 0x00 /* 0x08 ? */ #define TCO_TMR_HLT (1 << 11) -#define TCO1_STS 0x64 +#define TCO1_STS 0x04 #define DMISCI_STS (1 << 9) -#define TCO2_STS 0x66 +#define TCO2_STS 0x06 #define TCO2_STS_SECOND_TO (1 << 1) #define GPE0_REG_MAX 4 @@ -139,7 +140,4 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); -/* STM Support */ -uint16_t get_pmbase(void); - #endif diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index 80c7721..96cf681 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -11,6 +11,7 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/tco.h> static void map_rcba(void) { @@ -95,9 +96,7 @@ RCBA32_OR(GCS, 1 << 5); /* TCO timer halt */ - u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT); - reg16 |= TCO_TMR_HLT; - outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT); + tco_timer_disable(); /* Enable upper 128 bytes of CMOS */ RCBA32_OR(RC, 1 << 2); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 1ddee34..3403440 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -169,10 +169,10 @@ u32 reg32; /* Prepare sleep mode */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = pm_read32(PM1_CNT); reg32 &= ~SLP_TYP; reg32 |= SCI_EN; - outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + pm_write32(PM1_CNT, reg32); /* Set up NMI on errors */ reg8 = inb(0x61); diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 3da6bce..0406659 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -13,11 +13,13 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> +#include <security/vboot/vbnv.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <security/vboot/vbnv.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> #include <stdint.h> #define GPIO_ALT_GPI_SMI_STS 0x50 @@ -65,19 +67,15 @@ */ /* Enable events in PM1 control register */ -void enable_pm1_control(u32 mask) +void enable_pm1_control(uint32_t mask) { - u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, get_pmbase() + PM1_CNT); + pm_setbits32(PM1_CNT, mask); } /* Disable events in PM1 control register */ -void disable_pm1_control(u32 mask) +void disable_pm1_control(uint32_t mask) { - u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, get_pmbase() + PM1_CNT); + pm_clrbits32(PM1_CNT, mask); } /* @@ -87,9 +85,7 @@ /* Clear and return PM1 status register */ static u16 reset_pm1_status(void) { - u16 pm1_sts = inw(get_pmbase() + PM1_STS); - outw(pm1_sts, get_pmbase() + PM1_STS); - return pm1_sts; + return pm_rwc16(PM1_STS); } /* Print PM1 status bits */ @@ -125,7 +121,7 @@ /* Set the PM1 register to events */ void enable_pm1(u16 events) { - outw(events, get_pmbase() + PM1_EN); + pm_write16(PM1_EN, events); } /* @@ -135,9 +131,7 @@ /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(get_pmbase() + SMI_STS); - outl(smi_sts, get_pmbase() + SMI_STS); - return smi_sts; + return pm_rwc32(SMI_STS); } /* Print SMI status bits */ @@ -185,17 +179,13 @@ /* Enable SMI event */ void enable_smi(u32 mask) { - u32 smi_en = inl(get_pmbase() + SMI_EN); - smi_en |= mask; - outl(smi_en, get_pmbase() + SMI_EN); + pm_setbits32(SMI_EN, mask); } /* Disable SMI event */ void disable_smi(u32 mask) { - u32 smi_en = inl(get_pmbase() + SMI_EN); - smi_en &= ~mask; - outl(smi_en, get_pmbase() + SMI_EN); + pm_clrbits32(SMI_EN, mask); } /* @@ -205,12 +195,9 @@ /* Clear GPIO SMI status and return events that are enabled and active */ static u32 reset_alt_smi_status(void) { - u32 alt_sts, alt_en; - /* Low Power variant moves this to GPIO region as dword */ - alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS); - outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS); - alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); + u32 alt_sts = gpio_lp_rwc32(GPIO_ALT_GPI_SMI_STS); + u32 alt_en = gpio_lp_read32(GPIO_ALT_GPI_SMI_EN); /* Only report enabled events */ return alt_sts & alt_en; @@ -241,34 +228,13 @@ /* Enable GPIO SMI events */ void enable_alt_smi(u32 mask) { - u32 alt_en; - - alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); - alt_en |= mask; - outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN); + setbits_gpiobase32(GPIO_ALT_GPI_SMI_EN, mask); } /* * TCO */ -/* Clear TCO status and return events that are enabled and active */ -static u32 reset_tco_status(void) -{ - u32 tcobase = get_pmbase() + 0x60; - u32 tco_sts = inl(tcobase + 0x04); - u32 tco_en = inl(get_pmbase() + 0x68); - - /* Don't clear BOOT_STS before SECOND_TO_STS */ - outl(tco_sts & ~(1 << 18), tcobase + 0x04); - - /* Clear BOOT_STS */ - if (tco_sts & (1 << 18)) - outl(tco_sts & (1 << 18), tcobase + 0x04); - - return tco_sts & tco_en; -} - /* Print TCO status bits */ static u32 print_tco_status(u32 tco_sts) { @@ -302,14 +268,14 @@ /* Print, clear, and return TCO status */ u32 clear_tco_status(void) { - return print_tco_status(reset_tco_status()); + return print_tco_status(tco_reset_status()); } /* Enable TCO SCI */ void enable_tco_sci(void) { /* Clear pending events */ - outl(TCOSCI_STS, get_pmbase() + GPE0_STS(3)); + pm_write32(GPE0_STS(3), TCOSCI_STS); /* Enable TCO SCI events */ enable_gpe(TCOSCI_EN); @@ -322,10 +288,8 @@ /* Clear a GPE0 status and return events that are enabled and active */ static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { - u32 gpe0_sts = inl(get_pmbase() + sts_reg); - u32 gpe0_en = inl(get_pmbase() + en_reg); - - outl(gpe0_sts, get_pmbase() + sts_reg); + u32 gpe0_sts = pm_rwc32(sts_reg); + u32 gpe0_en = pm_read32(en_reg); /* Only report enabled events */ return gpe0_sts & gpe0_en; @@ -384,12 +348,10 @@ /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) { - u16 pmbase = get_pmbase(); - - outl(set1, pmbase + GPE0_EN(GPE_31_0)); - outl(set2, pmbase + GPE0_EN(GPE_63_32)); - outl(set3, pmbase + GPE0_EN(GPE_94_64)); - outl(set4, pmbase + GPE0_EN(GPE_STD)); + pm_write32(GPE0_EN(GPE_31_0), set1); + pm_write32(GPE0_EN(GPE_63_32), set2); + pm_write32(GPE0_EN(GPE_94_64), set3); + pm_write32(GPE0_EN(GPE_STD), set4); } /* Disable all GPE */ @@ -399,31 +361,22 @@ } /* Enable a standard GPE */ -void enable_gpe(u32 mask) +void enable_gpe(uint32_t mask) { - u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); - gpe0_en |= mask; - outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); + pm_setbits32(GPE0_EN(GPE_STD), mask); } /* Disable a standard GPE */ -void disable_gpe(u32 mask) +void disable_gpe(uint32_t mask) { - u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); - gpe0_en &= ~mask; - outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); + pm_clrbits32(GPE0_EN(GPE_STD), mask); } int platform_is_resuming(void) { - if (!(inw(get_pmbase() + PM1_STS) & WAK_STS)) + if (!(pm_read16(PM1_STS) & WAK_STS)) return 0; - return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; + return acpi_sleep_from_pm1(pm_read32(PM1_CNT)) == ACPI_S3; } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index b1ab622..55d9ff7 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -13,6 +13,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> static struct chipset_power_state power_state; @@ -49,7 +51,7 @@ break; } /* Clear SLP_TYP. */ - outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + pm_write32(PM1_CNT, ps->pm1_cnt & ~SLP_TYP); } if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR)) @@ -85,19 +87,21 @@ { struct chipset_power_state *ps = &power_state; - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS); - ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS); - ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); - ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1)); - ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2)); - ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3)); - ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); - ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1)); - ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2)); - ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3)); + ps->pm1_sts = pm_read16(PM1_STS); + ps->pm1_en = pm_read16(PM1_EN); + ps->pm1_cnt = pm_read32(PM1_CNT); + + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); + + ps->gpe0_sts[0] = pm_read32(GPE0_STS(0)); + ps->gpe0_sts[1] = pm_read32(GPE0_STS(1)); + ps->gpe0_sts[2] = pm_read32(GPE0_STS(2)); + ps->gpe0_sts[3] = pm_read32(GPE0_STS(3)); + ps->gpe0_en[0] = pm_read32(GPE0_EN(0)); + ps->gpe0_en[1] = pm_read32(GPE0_EN(1)); + ps->gpe0_en[2] = pm_read32(GPE0_EN(2)); + ps->gpe0_en[3] = pm_read32(GPE0_EN(3)); ps->gen_pmcon1 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_1); ps->gen_pmcon2 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_2); diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/soc/intel/broadwell/pch/smi.c index d7704fd..58b20f0 100644 --- a/src/soc/intel/broadwell/pch/smi.c +++ b/src/soc/intel/broadwell/pch/smi.c @@ -14,17 +14,12 @@ { u32 smi_en; - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); - - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + smi_en = pm_read32(SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } - printk(BIOS_DEBUG, "\n"); - /* Dump and clear status registers */ clear_smi_status(); clear_pm1_status(); diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index a8e2067..1d3723d 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -10,6 +10,7 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <drivers/intel/gma/i915_reg.h> #include <spi-generic.h> #include <elog.h> #include <halt.h> @@ -20,7 +21,8 @@ #include <soc/pm.h> #include <soc/rcba.h> #include <soc/xhci.h> -#include <drivers/intel/gma/i915_reg.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> #include <smmstore.h> int southbridge_io_trap_handler(int smif) @@ -144,13 +146,12 @@ { u32 reg32; u8 slp_typ; - u16 pmbase = get_pmbase(); /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -225,7 +226,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -364,7 +365,7 @@ static void southbridge_smi_mc(void) { - u32 reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = pm_read32(SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -407,7 +408,7 @@ static void southbridge_smi_periodic(void) { - u32 reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = pm_read32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 0b898a8..19e8358 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -147,7 +147,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() const struct soc_intel_cannonlake_config *config; config = config_of_soc(); diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 863d9f9..ff88cf7 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -156,8 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); - #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 7df8d47..6f471ec 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -222,8 +222,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -243,12 +243,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c355c944..25ea538 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -113,7 +113,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() fadt->sci_int = acpi_sci_irq(); diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h index 35cbfb1..2012818 100644 --- a/src/soc/intel/common/block/include/intelblocks/tco.h +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -17,7 +17,7 @@ * and returns the status bits set. */ uint32_t tco_reset_status(void); -uint16_t tco_read_reg(uint16_t tco_reg); -void tco_write_reg(uint16_t tco_reg, uint16_t value); +uint16_t tco_read16(uint16_t tco_reg); +void tco_write16(uint16_t tco_reg, uint16_t value); #endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index ea365d0..0dbd49c 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -124,10 +124,7 @@ static uint32_t pmc_reset_smi_status(void) { - uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); - - return soc_get_smi_status(smi_sts); + return soc_get_smi_status(pm_rwc32(SMI_STS)); } static uint32_t print_smi_status(uint32_t smi_sts) @@ -162,7 +159,7 @@ /* Read events set in PM1_EN register. */ uint16_t pmc_read_pm1_enable(void) { - return inw(ACPI_BASE_ADDRESS + PM1_EN); + return pm_read16(PM1_EN); } uint32_t pmc_clear_smi_status(void) @@ -174,58 +171,48 @@ uint32_t pmc_get_smi_en(void) { - return inl(ACPI_BASE_ADDRESS + SMI_EN); + return pm_read32(SMI_EN); } void pmc_enable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + pm_setbits32(SMI_EN, mask); } void pmc_disable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + pm_clrbits32(SMI_EN, mask); } /* PM1 */ void pmc_enable_pm1(uint16_t events) { - outw(events, ACPI_BASE_ADDRESS + PM1_EN); + pm_write16(PM1_EN, events); } uint32_t pmc_read_pm1_control(void) { - return inl(ACPI_BASE_ADDRESS + PM1_CNT); + return pm_read32(PM1_CNT); } void pmc_write_pm1_control(uint32_t pm1_cnt) { - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + pm_write32(PM1_CNT, pm1_cnt); } void pmc_enable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = pmc_read_pm1_control(); - pm1_cnt |= mask; - pmc_write_pm1_control(pm1_cnt); + pm_setbits32(PM1_CNT, mask); } void pmc_disable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = pmc_read_pm1_control(); - pm1_cnt &= ~mask; - pmc_write_pm1_control(pm1_cnt); + pm_clrbits32(PM1_CNT, mask); } static uint16_t reset_pm1_status(void) { - uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); - return pm1_sts; + return pm_rwc16(PM1_STS); } static uint16_t print_pm1_status(uint16_t pm1_sts) @@ -284,16 +271,12 @@ /* GPE */ static void pmc_enable_gpe(int gpe, uint32_t mask) { - uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); - gpe0_en |= mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); + pm_setbits32(GPE0_EN(gpe), mask); } static void pmc_disable_gpe(int gpe, uint32_t mask) { - uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); - gpe0_en &= ~mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); + pm_clrbits32(GPE0_EN(gpe), mask); } void pmc_enable_std_gpe(uint32_t mask) @@ -322,16 +305,13 @@ /* This is reserved GPE block and specific to chipset */ if (i == GPE_STD) continue; - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); + pm_rwc32(GPE0_STS(i))); } } static uint32_t reset_std_gpe_status(void) { - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - return gpe_sts; + return pm_rwc32(GPE0_STS(GPE_STD)); } static uint32_t print_std_gpe_sts(uint32_t gpe_sts) @@ -423,16 +403,16 @@ memset(ps, 0, sizeof(*ps)); - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + ps->pm1_sts = pm_read16(PM1_STS); + ps->pm1_en = pm_read16(PM1_EN); ps->pm1_cnt = pmc_read_pm1_control(); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); + ps->gpe0_sts[i] = pm_read32(GPE0_STS(i)); + ps->gpe0_en[i] = pm_read32(GPE0_EN(i)); printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); } @@ -480,7 +460,7 @@ return acpi_get_sleep_type() == ACPI_S3; /* Read power state from PMC ABASE */ - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(pm_read16(PM1_STS) & WAK_STS)) return 0; return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; @@ -506,9 +486,9 @@ if (stopwatch_expired(&sw)) return rc; - sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); + sts = pm_read32(GPE0_STS(bank)); if (sts & mask) { - outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + pm_write32(GPE0_STS(bank), mask); rc = 1; } } while (sts & mask); diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1ca8842..7ec8245 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -29,36 +29,45 @@ return TCO_BASE_ADDRESS; } -uint16_t tco_read_reg(uint16_t tco_reg) +uint16_t tco_read16(uint16_t tco_reg) { - uint16_t tcobase; - - tcobase = tco_get_bar(); - - return inw(tcobase + tco_reg); + return io_read16(tco_get_bar() + tco_reg); } -void tco_write_reg(uint16_t tco_reg, uint16_t value) +void tco_write16(uint16_t tco_reg, uint16_t value) { - uint16_t tcobase; + io_write16(tco_get_bar() + tco_reg, value); +} - tcobase = tco_get_bar(); +uint16_t tco_rwc16(uint16_t tco_reg) +{ + return io_rwc16(tco_get_bar() + tco_reg); +} - outw(value, tcobase + tco_reg); +void tco_setbits16(uint16_t tco_reg, uint16_t mask) +{ + io_setbits16(tco_get_bar() + tco_reg, mask); +} + +void tco_clrbits16(uint16_t tco_reg, uint16_t mask) +{ + io_clrbits16(tco_get_bar() + tco_reg, mask); +} + +void tco_clrsetbits16(uint16_t tco_reg, uint16_t clr, uint16_t set) +{ + io_clrsetbits16(tco_get_bar() + tco_reg, clr, set); } void tco_lockdown(void) { - uint16_t tcocnt; const pci_devfn_t dev = PCH_DEV_SMBUS; /* TCO base address lockdown */ pci_or_config32(dev, TCOCTL, TCO_BASE_LOCK); /* TCO Lock down */ - tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_LOCK; - tco_write_reg(TCO1_CNT, tcocnt); + tco_setbits16(TCO1_CNT, TCO_LOCK); } uint32_t tco_reset_status(void) @@ -67,12 +76,12 @@ uint16_t tco2_sts; /* TCO Status 1 register */ - tco1_sts = tco_read_reg(TCO1_STS); - tco_write_reg(TCO1_STS, tco1_sts); + tco1_sts = tco_rwc16(TCO1_STS); + /* First clear only TCO_STS_SECOND_TO here ?? */ /* TCO Status 2 register */ - tco2_sts = tco_read_reg(TCO2_STS); - tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); + tco2_sts = tco_read16(TCO2_STS); + tco_write16(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); return (tco2_sts << 16) | tco1_sts; } @@ -80,24 +89,14 @@ /* Stop TCO timer */ static void tco_timer_disable(void) { - uint16_t tcocnt; - - /* Program TCO timer halt */ - tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - tco_write_reg(TCO1_CNT, tcocnt); + tco_setbits16(TCO1_CNT, TCO_TMR_HLT); } /* Enable and initialize TCO intruder SMI */ static void tco_intruder_smi_enable(void) { - uint16_t tcocnt; - /* Make TCO issue an SMI on INTRD_DET assertion */ - tcocnt = tco_read_reg(TCO2_CNT); - tcocnt &= ~TCO_INTRD_SEL_MASK; - tcocnt |= TCO_INTRD_SEL_SMI; - tco_write_reg(TCO2_CNT, tcocnt); + tco_clrsetbits16(TCO2_CNT, TCO_INTRD_SEL_MASK, TCO_INTRD_SEL_SMI); } /* Enable TCO BAR using SMBUS TCO base to access TCO related register */ diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0a277f0..f5e3e37 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -156,7 +156,7 @@ /* First, disable further SMIs */ pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 99825f1..2d26f94 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -43,7 +43,7 @@ void smihandler_southbridge_mc( const struct smm_save_state_ops *save_state_ops) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = pm_read32(SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index dcf9a5f..dd7d74a 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -41,6 +41,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_TCO select SUPPORT_CPU_UCODE_IN_CBFS select SOUTHBRIDGE_INTEL_COMMON_SMBUS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h index 5b7a75d..de58ef2 100644 --- a/src/soc/intel/denverton_ns/include/soc/soc_util.h +++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h @@ -32,8 +32,6 @@ uint32_t get_tseg_memory(void); uint32_t get_top_of_low_memory(void); uint64_t get_top_of_upper_memory(void); -uint16_t get_pmbase(void); -uint16_t get_tcobase(void); /* * Secure functions. diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 8d670c6..5b61fce 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -68,20 +68,17 @@ static uint32_t reset_smi_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS)); - outl(smi_sts, (uint16_t)(pmbase + SMI_STS)); - return smi_sts; + return pm_rwc32(SMI_STS); } -uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); } +uint32_t clear_smi_status(void) +{ + return print_smi_status(reset_smi_status()); +} void enable_smi(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en |= mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); + pm_setbits32(SMI_EN, mask); } uint8_t *pmc_mmio_regs(void) @@ -98,34 +95,22 @@ void disable_smi(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en &= ~mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); + pm_clrbits32(SMI_EN, mask); } void enable_pm1_control(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt |= mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); + pm_setbits32(PM1_CNT, mask); } void disable_pm1_control(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt &= ~mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); + pm_clrbits32(PM1_CNT, mask); } static uint16_t reset_pm1_status(void) { - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS)); - outw(pm1_sts, (uint16_t)(pmbase + PM1_STS)); - return pm1_sts; + return pm_rwc16(PM1_STS); } static uint16_t print_pm1_status(uint16_t pm1_sts) @@ -146,12 +131,14 @@ return pm1_sts; } -uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); } +uint16_t clear_pm1_status(void) +{ + return print_pm1_status(reset_pm1_status()); +} void enable_pm1(uint16_t events) { - uint16_t pmbase = get_pmbase(); - outw(events, (uint16_t)(pmbase + PM1_EN)); + pm_write16(PM1_EN, events); } static uint32_t print_tco_status(uint32_t tco_sts) @@ -177,40 +164,41 @@ static uint32_t reset_tco_status(void) { - uint16_t tcobase = get_tcobase(); - uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS)); - uint32_t tco_en = inl((uint16_t)(tcobase + TCO1_CNT)); + uint32_t tco_sts = tco_read32(TCO1_STS); + uint32_t tco_en = tco_read32(TCO1_CNT); - outl(tco_sts, (uint16_t)(tcobase + TCO1_STS)); + /* Don't clear BOOT_STS before SECOND_TO_STS */ + tco_write32(TCO_STS, tco_sts & ~(BOOT_STS)); + /* Clear BOOT_STS */ + if (tco_sts & BOOT_STS) + tco_write32(TCO_STS, BOOT_STS); + return tco_sts & tco_en; } -uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); } +uint32_t clear_tco_status(void) +{ + return print_tco_status(reset_tco_status()); +} void enable_gpe(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); + pm_setbits32(GPE0_EN(GPE_STD), mask); } void disable_gpe(uint32_t mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); + pm_clrbits32(GPE0_EN(GPE_STD), mask); } -void disable_all_gpe(void) { disable_gpe(~0); } +void disable_all_gpe(void +{ + disable_gpe(~0); +} static uint32_t reset_gpe_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); - return gpe_sts; + return pm_rwc32(GPE0_STS(GPE_STD)); } static uint32_t print_gpe_sts(uint32_t gpe_sts) @@ -244,6 +232,9 @@ return gpe_sts; } -uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); } +uint32_t clear_gpe_status(void) +{ + return print_gpe_sts(reset_gpe_status()); +} void clear_pmc_status(void) { /* TODO */ } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2f3a5cc..dc65d5a 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -109,14 +109,10 @@ (uint32_t)PCR_SMBUS_GC_NR); /* Halt the TCO timer */ - uint16_t reg16 = inw(tco_base + TCO1_CNT); - reg16 |= TCO_TMR_HLT; - outw(reg16, tco_base + TCO1_CNT); + tco_timer_disable(); /* Clear the Second TCO status bit */ - reg16 = inw(tco_base + TCO2_STS); - reg16 |= TCO2_STS_SECOND_TO; - outw(reg16, tco_base + TCO2_STS); + tco_write16(TCO2_STS, tco_read16(TCO2_STS) | TCO_STS_SECOND_TO); } void mainboard_romstage_entry(void) diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 68e8519..e1ab901 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -78,13 +78,12 @@ { uint32_t reg32; uint8_t slp_typ; - uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl((uint16_t)(pmbase + PM1_CNT)); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = (reg32 >> 10) & 7; @@ -138,7 +137,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl((uint16_t)(pmbase + PM1_CNT)); + reg32 = pm_read32(PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -274,7 +273,7 @@ { uint32_t reg32; - reg32 = inl((uint16_t)(get_pmbase() + SMI_EN)); + reg32 = pm_read32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index e7ed28d..dc48703 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -16,10 +16,7 @@ { uint32_t smi_en; - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); - - smi_en = inl((uint16_t)(get_pmbase() + SMI_EN)); + smi_en = pm_read32(SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index b4c707d..3387ced 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -182,7 +182,7 @@ (uint64_t)(pci_read_config32(dev, TOUUD_LO) & MASK_TOUUD_LO); } -uint16_t get_pmbase(void) +uint16_t lpc_get_pmbase(void) { #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; @@ -197,21 +197,6 @@ return pci_read_config16(dev, PMC_ACPI_BASE) & 0xfff8; } -uint16_t get_tcobase(void) -{ -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; -#else - struct device *dev; -#endif - dev = get_smbus_dev(); - - if (!dev) - return 0; - - return pci_read_config16(dev, TCOBASE) & MASK_TCOBASE; -} - void mmio_andthenor32(void *addr, uint32_t val2and, uint32_t val2or) { uint32_t reg32; diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 091b785..f635c7c 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -146,7 +146,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() config_t *config = config_of_soc(); diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c index cc0bb8f..d4d8d07 100644 --- a/src/soc/intel/elkhartlake/bootblock/bootblock.c +++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c @@ -33,10 +33,10 @@ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); if (CONFIG(SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN)) { - uint16_t reg = tco_read_reg(TCO1_CNT); + uint16_t reg = tco_read16(TCO1_CNT); /* NO_REBOOT is enabled via bit 0 in TCO1_CNT. */ reg |= 0x01; - tco_write_reg(TCO1_CNT, reg); + tco_write16(TCO1_CNT, reg); printk(BIOS_DEBUG, "TCO: Disable reset on second expiration.\n"); } } diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 6a86787..ae105bf 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -155,7 +155,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 76a9cd3..bb14070 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 9781927..190c36b 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -143,7 +143,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() config_t *config = config_of_soc(); diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 05db830..e6e9b02 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -155,8 +155,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); - #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 9297ffd..0f5acdd 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 369eb02..5f2382f 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -146,7 +146,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() config_t *config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index eea875b..e6e9b02 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -155,7 +155,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index f2a4c90..34e0f32 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index 54de566..7e3d08b 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -149,7 +149,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() config_t *config = config_of_soc(); diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h index c486232..ff46b93 100644 --- a/src/soc/intel/meteorlake/include/soc/pm.h +++ b/src/soc/intel/meteorlake/include/soc/pm.h @@ -156,7 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 974f966..29b9df9 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -220,8 +220,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -241,12 +241,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 9e41b31..040835f 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -10,14 +10,22 @@ return current; } +struct device *lpc_dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC); + +uint16_t lpc_get_pmbase(void) +{ + return pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; +} + +uint16_t lpc_get_gpe0base(void) +{ + return pci_read_config32(dev, R_QNC_LPC_GPE0BLK) & B_QNC_LPC_GPE0BLK_MASK; +} + void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK) - & B_QNC_LPC_GPE0BLK_MASK; - uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK) - & B_QNC_LPC_PM1BLK_MASK; + uint16_t pmbase = get_pmbase(); + uint16_t gpe0_base = lpc_get_gpe0base(); fadt->flags |= ACPI_FADT_PLATFORM_CLOCK; @@ -72,10 +80,3 @@ printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl); } - -uint16_t get_pmbase(void) -{ - struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; -} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 7a08c6e..408feb3 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -13,7 +13,5 @@ struct chipset_power_state *get_power_state(void); int fill_power_state(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 604561a..0430f0b 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -65,6 +65,18 @@ return (uint16_t)(gpio_base_address + reg_address); } +uint32_t reg_legacy_gpio_read(uint32_t reg_address) +{ + /* Read the legacy GPIO register */ + return inl(get_legacy_gpio_address(reg_address)); +} + +void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value) +{ + /* Write the legacy GPIO register */ + outl(value, get_legacy_gpio_address(reg_address)); +} + static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) { uint32_t offset; @@ -172,7 +184,7 @@ static void reg_gpe0_write(uint32_t reg_address, uint32_t value) { /* Write the GPE0 register */ - outl(get_gpe0_address(reg_address), value); + outl(value, get_gpe0_address(reg_address)); } static uint32_t reg_gpio_read(uint32_t reg_address) @@ -205,18 +217,6 @@ reg_address); } -uint32_t reg_legacy_gpio_read(uint32_t reg_address) -{ - /* Read the legacy GPIO register */ - return inl(get_legacy_gpio_address(reg_address)); -} - -void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value) -{ - /* Write the legacy GPIO register */ - outl(value, get_legacy_gpio_address(reg_address)); -} - static uint32_t reg_pcie_afe_read(uint32_t reg_address) { /* Read the PCIE AFE register */ diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index a1b3e43..99a02df 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -8,7 +8,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index f0ce146..eefaf9c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -186,7 +186,4 @@ return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); } -/* STM Support */ -uint16_t get_pmbase(void); - #endif diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 61662d2..bf2357c 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -84,10 +84,7 @@ S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP); /* Enable SCI and clear SLP requests. */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); - reg32 &= ~SLP_TYP; - reg32 |= SCI_EN; - outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + pm_clrsetbits32(PM1_CNT, SLP_TYP, SCI_EN); pmc_set_acpi_mode(); diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index fe26ebf..5e97c97 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -224,8 +224,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -243,12 +243,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 573dc5f..abcdd8c 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -146,7 +146,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index cb0781a..56885a5 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -162,7 +162,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 9aca5c2..a308020 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -244,8 +244,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); @@ -265,12 +265,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index b4d6df9..5015df5 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -117,8 +117,6 @@ /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); -uint16_t get_pmbase(void); - void pmc_lock_smi(void); #endif diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index c63285c..0051e04 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -159,12 +159,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 88f24d4..adea2d7 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -36,7 +36,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase() /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ fadt->flags &= ~(ACPI_FADT_SEALED_CASE); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e4e002d..fbc57dd 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -9,6 +9,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/tco.h> /* For DMI bar. */ #include <northbridge/intel/sandybridge/sandybridge.h> @@ -233,7 +234,8 @@ static void pch_generic_setup(void) { RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ + + tco_timer_disable()_2; /* halt timer */ } static void pch_enable_gbe(void) diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 654d44b..47c08e7 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -21,7 +21,7 @@ int i; /* Unlock registers. */ - write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); + pm_setbits16(UPWRC, UPRWC_WR_EN); for (i = 0; i < 14; i++) RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; @@ -53,5 +53,5 @@ pci_write_config32(PCH_XHCI_DEV, 0xe4, 0x00000000); /* Relock registers. */ - write_pmbase16(UPRWC, 0); + pm_write16(UPRWC, 0); } diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 684f830..6001366 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -8,6 +8,7 @@ #include <stdint.h> #include <elog.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> #include "pch.h" void pch_log_state(void) @@ -20,10 +21,12 @@ if (!lpc) return; - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); - tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); + pm1_sts = pm_read16(PM1_STS); + gpe0_sts = pm_read32(GPE0_STS); + gpe0_en = pm_read32(GPE0_EN); + + tco2_sts = tco_read16(TCO2_STS); + gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index f625198..645a6f0 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -1,16 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> #include "chip.h" void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_bd82x6x_config *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7c10c81..a25c970 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -148,7 +148,7 @@ static void pch_power_options(struct device *dev) { u8 reg8; - u16 reg16, pmbase; + u16 reg16; u32 reg32; const char *state; /* Get the chip configuration */ @@ -223,16 +223,14 @@ // Set the board's GPI routing. pch_gpi_routing(dev); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - - outl(config->gpe0_en, pmbase + GPE0_EN); - outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + pm_write32(GPE0_EN, config->gpe0_en); + pm_write16(ALT_GP_SMI_EN, config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 = pm_read32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + pm_write32(PM1_CNT, reg32); /* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(PRSTS); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 2ebec62..097f964 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -464,16 +464,6 @@ #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 -#define TCO1_STS 0x64 -#define TCO1_TIMEOUT (1 << 3) -#define DMISCI_STS (1 << 9) -#define TCO2_STS 0x66 -#define SECOND_TO_STS (1 << 1) -#define TCO1_CNT 0x68 -#define TCO_TMR_HLT (1 << 11) -#define TCO_LOCK (1 << 12) -#define TCO2_CNT 0x6a - #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 6fb27bb..81cdf4c 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> #include <southbridge/intel/common/rcba.h> #include <spi-generic.h> @@ -46,9 +47,10 @@ pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); if (CONFIG(BOOTMEDIA_SMM_BWP)) - write_pmbase16(SMI_EN, read_pmbase16(SMI_EN) | TCO_EN); + pm_setbits16(SMI_EN, TCO_EN); - write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); + /* TCO_Lock */ + tco_lockdown(); post_code(POST_OS_BOOT); } diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2fddfc9..dbbabaa 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -13,70 +13,32 @@ /* LPC PM Base Address Register */ #define PMBASE 0x40 -#define PMSIZE 0x80 u16 lpc_get_pmbase(void) { #ifdef __SIMPLE_DEVICE__ - /* Don't assume PMBASE is still the same */ return pci_read_config16(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xfffc; #else - static u16 pmbase; - - if (pmbase) - return pmbase; - - pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), PMBASE) & 0xfffc; - - return pmbase; + return pci_read_config16(pcidev_on_root(0x1f, 0), PMBASE) & 0xfffc; #endif } -void write_pmbase32(const u8 addr, const u32 val) +#if 0 +u16 get_pmbase(void) { - ASSERT(addr <= (PMSIZE - sizeof(u32))); + static u16 pmbase; + if (pmbase) + return pmbase; - outl(val, lpc_get_pmbase() + addr); + /* Don't assume PMBASE is still the same */ + pmbase = lpc_get_pmbase(); + return pmbase; } - -void write_pmbase16(const u8 addr, const u16 val) -{ - ASSERT(addr <= (PMSIZE - sizeof(u16))); - - outw(val, lpc_get_pmbase() + addr); -} - -void write_pmbase8(const u8 addr, const u8 val) -{ - ASSERT(addr <= (PMSIZE - sizeof(u8))); - - outb(val, lpc_get_pmbase() + addr); -} - -u32 read_pmbase32(const u8 addr) -{ - ASSERT(addr <= (PMSIZE - sizeof(u32))); - - return inl(lpc_get_pmbase() + addr); -} - -u16 read_pmbase16(const u8 addr) -{ - ASSERT(addr <= (PMSIZE - sizeof(u16))); - - return inw(lpc_get_pmbase() + addr); -} - -u8 read_pmbase8(const u8 addr) -{ - ASSERT(addr <= (PMSIZE - sizeof(u8))); - - return inb(lpc_get_pmbase() + addr); -} +#endif int acpi_get_sleep_type(void) { - return acpi_sleep_from_pm1(read_pmbase32(PM1_CNT)); + return acpi_sleep_from_pm1(pm_read32(PM1_CNT)); } /* @@ -85,7 +47,7 @@ */ int platform_is_resuming(void) { - u16 reg16 = read_pmbase16(PM1_STS); + u16 reg16 = pm_read16(PM1_STS); if (!(reg16 & WAK_STS)) return 0; diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h index febcff2..0662b9e 100644 --- a/src/southbridge/intel/common/pmbase.h +++ b/src/southbridge/intel/common/pmbase.h @@ -1,13 +1,124 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __INTEL_COMMON_PMBASE__ +#define __INTEL_COMMON_PMBASE__ + +#include <arch/io.h> +#include <arch/io_bitops.h> +#include <assert.h> #include <stdint.h> +#define PMSIZE 0x80 + u16 lpc_get_pmbase(void); -void write_pmbase32(const u8 addr, const u32 val); -void write_pmbase16(const u8 addr, const u16 val); -void write_pmbase8(const u8 addr, const u8 val); +#if CONFIG(SOUTHBRIDGE_INTEL_I82371EB +#include <southbridge/intel/i82371eb/i82371eb.h> +#define ACPI_BASE_ADDRESS DEFAULT_PMBASE -u32 read_pmbase32(const u8 addr); -u16 read_pmbase16(const u8 addr); -u8 read_pmbase8(const u8 addr); +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX +#include <southbridge/intel/i82801ix/i82801ix.h> +#define ACPI_BASE_ADDRESS DEFAULT_PMBASE +#else +#include <soc/iomap.h> +#endif + +static __always_inline u16 get_pmbase(void) +{ +// return lpc_get_pmbase(); + return ACPI_BASE_ADDRESS; +} + + +static __always_inline void pm_write32(const u16 addr, const u32 val) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + outl(val, get_pmbase() + addr); +} + +static __always_inline void pm_write16(const u16 addr, const u16 val) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + outw(val, get_pmbase() + addr); +} + +static __always_inline void pm_write8(const u16 addr, const u8 val) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + outb(val, get_pmbase() + addr); +} + +static __always_inline u32 pm_read32(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + return inl(get_pmbase() + addr); +} + +static __always_inline u16 pm_read16(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + return inw(get_pmbase() + addr); +} + +static __always_inline u8 pm_read8(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + return inb(get_pmbase() + addr); +} + +static __always_inline u32 pm_rwc32(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + return io_rwc32(get_pmbase() + addr); +} + +static __always_inline u16 pm_rwc16(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + return io_rwc16(get_pmbase() + addr); +} + +static __always_inline void pm_setbits32(const u16 addr, const u32 mask) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + io_setbits32(get_pmbase() + addr, mask); +} + +static __always_inline void pm_setbits8(const u16 addr, const u8 mask) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + io_setbits8(get_pmbase() + addr, mask); +} + +static __always_inline void pm_clrbits8(const u16 addr, const u8 mask) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + io_clrbits8(get_pmbase() + addr, mask); +} + +static __always_inline void pm_clrbits32(const u16 addr, const u32 mask) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + io_clrbits32(get_pmbase() + addr, mask); +} + +static __always_inline void pm_clrsetbits32(const u16 addr, const u32 clr, const u32 set) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + io_clrsetbits32(get_pmbase() + addr, clr, set); +} + +static __always_inline void pm_clrsetbits16(const u16 addr, const u16 clr, const u16 set) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + io_clrsetbits16(get_pmbase() + addr, clr, set); +} + +static __always_inline void pm_clrsetbits8(const u16 addr, const u8 clr, const u8 set) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + io_clrsetbits8(get_pmbase() + addr, clr, set); +} + + +#endif diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c index 34a449b..1bd3686 100644 --- a/src/southbridge/intel/common/pmclib.c +++ b/src/southbridge/intel/common/pmclib.c @@ -11,8 +11,8 @@ static void clear_power_state(void) { - uint32_t pm1_cnt = read_pmbase32(PM1_CNT); - write_pmbase32(PM1_CNT, pm1_cnt & ~SLP_TYP); + uint32_t pm1_cnt = pm_read32(PM1_CNT); + pm_write32(PM1_CNT, pm1_cnt & ~SLP_TYP); } int southbridge_detect_s3_resume(void) diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 8ecb74c..afb8bd1 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -4,24 +4,19 @@ #include <console/console.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> #include <southbridge/intel/common/gpio.h> #include "pmutil.h" void alt_gpi_mask(u16 clr, u16 set) { - u16 alt_gp = read_pmbase16(ALT_GP_SMI_EN); - alt_gp &= ~clr; - alt_gp |= set; - write_pmbase16(ALT_GP_SMI_EN, alt_gp); + pm_clrsetbits16(ALT_GP_SMI_EN, clr, set); } void gpe0_mask(u32 clr, u32 set) { - u32 gpe0 = read_pmbase32(GPE0_EN); - gpe0 &= ~clr; - gpe0 |= set; - write_pmbase32(GPE0_EN, gpe0); + pm_clrsetbits32(GPE0_EN, clr, set); } /** @@ -30,11 +25,7 @@ */ u16 reset_pm1_status(void) { - u16 reg16 = read_pmbase16(PM1_STS); - /* set status bits are cleared by writing 1 to them */ - write_pmbase16(PM1_STS, reg16); - - return reg16; + return pm_rwc16(PM1_STS); } void dump_pm1_status(u16 pm1_sts) @@ -50,7 +41,7 @@ if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); printk(BIOS_SPEW, "\n"); - int reg16 = read_pmbase16(PM1_EN); + int reg16 = pm_read16(PM1_EN); printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); } @@ -60,13 +51,7 @@ */ u32 reset_smi_status(void) { - u32 reg32; - - reg32 = read_pmbase32(SMI_STS); - /* set status bits are cleared by writing 1 to them */ - write_pmbase32(SMI_STS, reg32); - - return reg32; + return pm_rwc32(SMI_STS); } void dump_smi_status(u32 smi_sts) @@ -103,13 +88,13 @@ { u32 reg_h = 0, reg_l; - reg_l = read_pmbase32(GPE0_STS); + reg_l = pm_read32(GPE0_STS); if (GPE0_HAS_64_EVENTS) - reg_h = read_pmbase32(GPE0_STS + 4); + reg_h = pm_read32(GPE0_STS + 4); /* set status bits are cleared by writing 1 to them */ - write_pmbase32(GPE0_STS, reg_l); + pm_write32(GPE0_STS, reg_l); if (GPE0_HAS_64_EVENTS) - write_pmbase32(GPE0_STS + 4, reg_h); + pm_write32(GPE0_STS + 4, reg_h); return (((u64)reg_h) << 32) | reg_l; } @@ -140,26 +125,6 @@ printk(BIOS_DEBUG, "\n"); } -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -u32 reset_tco_status(void) -{ - u32 reg32; - - reg32 = read_pmbase32(TCO1_STS); - /* - * set status bits are cleared by writing 1 to them, but don't - * clear BOOT_STS before SECOND_TO_STS. - */ - write_pmbase32(TCO1_STS, reg32 & ~BOOT_STS); - if (reg32 & BOOT_STS) - write_pmbase32(TCO1_STS, BOOT_STS); - - return reg32; -} - void dump_tco_status(u32 tco_sts) { printk(BIOS_DEBUG, "TCO_STS: "); @@ -195,13 +160,7 @@ */ u16 reset_alt_gp_smi_status(void) { - u16 reg16; - - reg16 = read_pmbase16(ALT_GP_SMI_STS); - /* set status bits are cleared by writing 1 to them */ - write_pmbase16(ALT_GP_SMI_STS, reg16); - - return reg16; + return pm_rwc16(ALT_GP_SMI_STS); } void dump_all_status(void) @@ -210,5 +169,5 @@ dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); + dump_tco_status(tco_reset_status()); } diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 5cf76b6..deedb6a 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -104,20 +104,10 @@ #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) -#define BOOT_STS (1 << 18) -#define TCO2_STS 0x66 -#define TCO1_CNT 0x68 -#define TCO_LOCK (1 << 12) -#define TCO2_CNT 0x6a - -u16 get_pmbase(void); u16 reset_pm1_status(void); void dump_pm1_status(u16 pm1_sts); void dump_tco_status(u32 tco_sts); -u32 reset_tco_status(void); void dump_gpe0_status(u64 gpe0_sts); u64 reset_gpe0_status(void); void dump_smi_status(u32 smi_sts); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 8309d12..d268a9f 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -10,11 +10,6 @@ #include "pmutil.h" -u16 get_pmbase(void) -{ - return lpc_get_pmbase(); -} - static int smi_enabled(void) { u32 smi_en; @@ -23,15 +18,12 @@ if (CONFIG(ELOG)) pch_log_state(); - printk(BIOS_DEBUG, "Initializing southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase()); - - smi_en = read_pmbase32(SMI_EN); + smi_en = pm_read32(SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return 1; } - printk(BIOS_DEBUG, "\n"); + return 0; } @@ -41,11 +33,11 @@ u32 gpe0_en; /* Disable GPE0 PME_B0 */ - gpe0_en = read_pmbase32(GPE0_EN); + gpe0_en = pm_read32(GPE0_EN); gpe0_en &= ~PME_B0_EN; - write_pmbase32(GPE0_EN, gpe0_en); + pm_write32(GPE0_EN, gpe0_en); - write_pmbase16(PM1_EN, pm1_events); + pm_write16(PM1_EN, pm1_events); /* Enable SMI generation: * - on TCO events @@ -65,7 +57,7 @@ /* The following need to be on for SMIs to happen */ smi_en |= EOS | GBL_SMI_EN; - write_pmbase32(SMI_EN, smi_en); + pm_write32(SMI_EN, smi_en); } void global_smi_enable(void) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 798f2f1..ce97c05 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -13,15 +13,11 @@ #include <halt.h> #include <option.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> #include <smmstore.h> #include "pmutil.h" -u16 get_pmbase(void) -{ - return lpc_get_pmbase(); -} - void gpi_route_interrupt(u8 gpi, u8 mode) { u32 gpi_rout; @@ -47,7 +43,7 @@ */ void southbridge_smi_set_eos(void) { - write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) | EOS); + pm_setbits8(SMI_EN, EOS); } static void busmaster_disable_on_bus(int bus) @@ -114,10 +110,10 @@ u8 slp_typ; /* First, disable further SMIs */ - write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN); + pm_clrbits8(SMI_EN, SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = read_pmbase32(PM1_CNT); + reg32 = pm_read32(PM1_CNT); slp_typ = acpi_sleep_from_pm1(reg32); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x, TYPE = 0x%02x\n", reg32, slp_typ); @@ -156,7 +152,7 @@ case ACPI_S5: printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - write_pmbase32(GPE0_EN, 0); + pm_write32(GPE0_EN, 0); /* Always set the flag in case CMOS was changed on runtime. */ if (power_on_after_fail()) @@ -174,7 +170,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - write_pmbase32(PM1_CNT, reg32 | SLP_EN); + pm_write32(PM1_CNT, reg32 | SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ >= ACPI_S3) @@ -184,11 +180,11 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = read_pmbase32(PM1_CNT); + reg32 = pm_read32(PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ reg32 &= ~(SLP_EN | SLP_TYP); - write_pmbase32(PM1_CNT, reg32); + pm_write32(PM1_CNT, reg32); } } @@ -278,10 +274,10 @@ reg8 = apm_get_apmc(); switch (reg8) { case APM_CNT_ACPI_DISABLE: - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) & ~SCI_EN); + pm_clrbits32(PM1_CNT, SCI_EN); break; case APM_CNT_ACPI_ENABLE: - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); + pm_setbits32(PM1_CNT, SCI_EN); break; case APM_CNT_FINALIZE: if (mainboard_finalized) { @@ -320,7 +316,7 @@ u32 reg32; reg32 = (7 << 10) | (1 << 13); elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - write_pmbase32(PM1_CNT, reg32); + pm_write32(PM1_CNT, reg32); } } @@ -337,21 +333,21 @@ u16 reg16; reg16 = reset_alt_gp_smi_status(); - reg16 &= read_pmbase16(ALT_GP_SMI_EN); + reg16 &= pm_read16(ALT_GP_SMI_EN); mainboard_smi_gpi(reg16); if (reg16) printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); - write_pmbase16(ALT_GP_SMI_STS, reg16); + pm_write16(ALT_GP_SMI_STS, reg16); } static void southbridge_smi_mc(void) { u32 reg32; - reg32 = read_pmbase32(SMI_EN); + reg32 = pm_read32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -364,7 +360,7 @@ { u32 tco_sts; - tco_sts = reset_tco_status(); + tco_sts = tco_reset_status(); /* Any TCO event? */ if (!tco_sts) @@ -402,7 +398,7 @@ { u32 reg32; - reg32 = read_pmbase32(SMI_EN); + reg32 = pm_read32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) diff --git a/src/southbridge/intel/common/tco.c b/src/southbridge/intel/common/tco.c new file mode 100644 index 0000000..f714441 --- /dev/null +++ b/src/southbridge/intel/common/tco.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> +#include <types.h> + +#define PMBASE_TCO_OFFSET 0x60 +#define PMSIZE 0x80 + +static void tco_write16(const uint8_t tco_reg, uint16_t value) +{ + ASSERT((PMBASE_TCO_OFFSET + tco_reg) <= (PMSIZE - sizeof(u16))); + pm_write16(PMBASE_TCO_OFFSET + tco_reg, value); +} + +static uint16_t tco_read16(const uint8_t tco_reg) +{ + ASSERT((PMBASE_TCO_OFFSET + tco_reg) <= (PMSIZE - sizeof(u16))); + return pm_read16(PMBASE_TCO_OFFSET + tco_reg); +} + +void tco_write32(const uint8_t tco_reg, uint32_t value) +{ + ASSERT((PMBASE_TCO_OFFSET + tco_reg) <= (PMSIZE - sizeof(u32))); + pm_write32(PMBASE_TCO_OFFSET + tco_reg, value); +} + +uint32_t tco_read32(const uint8_t tco_reg) +{ + ASSERT((PMBASE_TCO_OFFSET + tco_reg) <= (PMSIZE - sizeof(u32))); + return pm_read32(PMBASE_TCO_OFFSET + tco_reg); +} + +void tco_timer_disable(void) +{ + tco_write16(TCO1_CNT, tco_read16(TCO1_CNT) | TCO_TMR_HLT); +} + +void tco_timer_disable_2(void) +{ + tco_write16(TCO1_CNT, TCO_TMR_HLT); +} + +void tco_clear_timeout(void) +{ + tco_write16(TCO1_STS, TCO1_TIMEOUT); /* clear timeout */ + tco_write16(TCO2_STS, SECOND_TO_STS); /* clear 2nd timeout */ +} + +void tco_lockdown(void) +{ + tco_write16(TCO1_CNT, tco_read16(TCO1_CNT) | TCO_LOCK); +} + +void tco_timer_init(void) +{ + /* Set higher timer value. */ + if (!CONFIG(HAVE_SMI_HANDLER)) + tco_write16(TCO_TMR, 0x8); + + /* Update timer. */ + tco_write16(TCO_RLD, 0); +} + +/* Clear TCO status and return events that are enabled and active */ +uint32_t tco_reset_status(void) +{ + uint32_t tco_sts = tco_read32(TCO1_STS); + uint32_t tco_en = tco_read32(TCO1_CNT); + + /* Don't clear BOOT_STS before SECOND_TO_STS */ + tco_write32(TCO1_STS, tco_sts & ~BOOT_STS); + + /* Clear BOOT_STS */ + if (tco_sts & BOOT_STS) + tco_write32(TCO1_STS, BOOT_STS); + + return tco_sts & tco_en; +} diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 03d3122..34858da 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -3,12 +3,24 @@ #ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H #define SOUTHBRIDGE_INTEL_COMMON_TCO_H -#define PMBASE_TCO_OFFSET 0x60 -#define TCO1_STS 0x04 -#define TCO1_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define SECOND_TO_STS (1 << 1) -#define TCO1_CNT 0x08 -#define TCO_TMR_HLT (1 << 11) +#include <types.h> + +#define TCO1_STS 0x04 +#define TCO1_TIMEOUT (1 << 3) +#define DMISCI_STS (1 << 9) +#define BOOT_STS (1 << 18) ?? 16 bit register (1 << 2) on TCO2_STS +#define TCO2_STS 0x06 +#define SECOND_TO_STS (1 << 1) +#define TCO1_CNT 0x08 +#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO2_CNT 0x0a + + +void tco_timer_disable(void); +void tco_timer_disable_2(void); +void tco_lockdown(void); +void tco_clear_timeout(void); +uint32_t tco_reset_status(void); #endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index b40c5fe..c0f4b3a 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -5,7 +5,6 @@ #include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/tco.h> #include <watchdog.h> @@ -27,13 +26,10 @@ pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ - value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); - value |= TCO_TMR_HLT; - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); + tco_timer_disable(); /* Clear TCO timeout status. */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); + tco_clear_timeout(); printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); } diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index e3e67ea..a8e71dc 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -127,7 +127,7 @@ Name (BUF1, ResourceTemplate () { /* PM register ports */ - IO (Decode16, PM_IO_BASE, PM_IO_BASE, 0x01, 0x40, ) + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x01, 0x40, ) /* SMBus register ports */ IO (Decode16, SMBUS_IO_BASE, SMBUS_IO_BASE, 0x01, 0x10, ) }) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 1d640f4..9ea7623 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -8,6 +8,7 @@ #include <device/device.h> #include <device/pci.h> #include <version.h> +#include <southbridge/intel/common/pmbase.h> #include "i82371eb.h" @@ -17,6 +18,8 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { + u16 pmbase = get_pmbase(); + fadt->sci_int = 9; if (permanent_smi_handler()) { @@ -24,11 +27,11 @@ fadt->smi_cmd = 0x00; } - fadt->pm1a_evt_blk = DEFAULT_PMBASE; - fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; + fadt->pm1a_evt_blk = pmbase; + fadt->pm1a_cnt_blk = pmbase + PMCNTRL; - fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR; - fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS; + fadt->pm_tmr_blk = pmbase + PMTMR; + fadt->gpe0_blk = pmbase + GPSTS; /* *_len define register width in bytes */ fadt->pm1_evt_len = 4; diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 2a3b167..0b3e1f38c 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -39,7 +39,7 @@ #define SMBUS_IO_BASE 0x0f00 #define SMBHSTCFG 0xd2 /* SMBus host configuration */ -/* Power management (ACPI) I/O ports, offset from PM_IO_BASE below */ +/* Power management (ACPI) I/O ports, offset from DEFAULT_PMBASE below */ #define PMSTS 0x00 /* Power Management Status */ #define PMEN 0x02 /* Power Management Resume Enable */ #define PWRBTN_EN (1<<8) @@ -88,7 +88,6 @@ /* Power management (ACPI) PCI registers */ #define PMBA 0x40 /* Power management base address */ #define DEFAULT_PMBASE 0xe400 -#define PM_IO_BASE DEFAULT_PMBASE #define DEVRESA 0x5c /* Device resource A */ #define DEVRESB 0x60 /* Device resource B */ #define DEVRESC 0x64 /* Device resource C */ diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 7c1ce1b..46925dc 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -8,6 +8,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/smbus.h> +#include <southbridge/intel/common/pmbase.h> + #include "chip.h" #include "i82371eb.h" @@ -35,40 +37,40 @@ (1<<24)| (0xff<<8)| (sb->thrm_polarity<<2); - outl(reg, DEFAULT_PMBASE + GLBCTL); + pm_write32(GLBCTL, reg); /* set processor control: * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3 * bit11 (sleep_en): 1=enable slp# assertion on lvl3 * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs */ - outl(0, DEFAULT_PMBASE + PCNTRL); + pm_write32(PCNTRL, 0); /* disable smi event enables */ - outw(0, DEFAULT_PMBASE + GLBEN); - outl(0, DEFAULT_PMBASE + DEVCTL); + pm_write16(GLBEN, 0); + pm_write32(DEVCTL, 0); /* set default gpo value. * power-on default is 0x7fffbfffh */ if (gpo) { /* only 8bit access allowed */ - outb(gpo & 0xff, DEFAULT_PMBASE + GPO0); - outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); - outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); - outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); + pm_write8(GPO0, gpo & 0xff); + pm_write8(GPO1, (gpo >> 8) & 0xff); + pm_write8(GPO2, (gpo >> 16) & 0xff); + pm_write8(GPO3, (gpo >> 24) & 0xff); } else { printk(BIOS_SPEW, "%s: gpo default missing in devicetree.cb!\n", __func__); } /* Clear status events. */ - outw(0xffff, DEFAULT_PMBASE + PMSTS); - outw(0xffff, DEFAULT_PMBASE + GPSTS); - outw(0xffff, DEFAULT_PMBASE + GLBSTS); - outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); + pm_write16(PMSTS, 0xffff); + pm_write16(GPSTS, 0xffff); + pm_write16(GLBSTS, 0xffff); + pm_write32(DEVSTS, 0xffffffff); /* set PMCNTRL default */ - outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); + pm_write16(PMCNTRL, SUS_TYP_S0|SCI_EN); } static void pwrmgt_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index 4cad322..1346cb0 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -31,7 +31,7 @@ { u16 reg, result; - reg = inw(DEFAULT_PMBASE + PMCNTRL); + reg = pm_read16(PMCNTRL); result = acpi_sus_to_slp_typ[(reg >> 10) & 7]; printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg); diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index fdb7fb3..33498cd 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -2,12 +2,12 @@ #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <device/pci_ops.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/pmutil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) { - u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - + u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 4c1366e..c0758bb 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -140,9 +140,6 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 -/* TCO1 Control Register */ -#define TCO1_CNT 0x68 - #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index d914335..2b4e40a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -132,14 +132,11 @@ reg16 |= (1 << 5); // CPUSLP_EN Desktop only pci_write_config16(dev, GEN_PMCON_1, reg16); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - + reg32 = pm_read32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + pm_write32(PM1_CNT, reg32); } diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index deb3deb..425584c 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -6,6 +6,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -57,8 +58,6 @@ pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); } -#define TCO_BASE 0x60 - #if ENV_RAMINIT void i82801gx_early_init(void) { @@ -72,9 +71,8 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ - write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ - write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + tco_timer_disable_2(); /* halt timer */ + tco_clear_timeout(); /* clear timeouts */ printk(BIOS_DEBUG, " done.\n"); /* program secondary mlt XXX byte? */ diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 6d63e72..62d6461 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -12,7 +12,7 @@ { struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_i82801gx_config *chip = dev->chip_info; - u16 pmbase = lpc_get_pmbase(); + u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 68a32df..cf76a40 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -320,7 +320,6 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 -#define TCO1_CNT 0x68 #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ec0df27..ab4f6d9 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -20,6 +20,7 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> +#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -217,16 +218,16 @@ // Set the board's GPI routing. i82801gx_gpi_routing(dev); - write_pmbase32(GPE0_EN, config->gpe0_en); - write_pmbase16(ALT_GP_SMI_EN, config->alt_gp_smi_en); + pm_write32(GPE0_EN, config->gpe0_en); + pm_write16(ALT_GP_SMI_EN, config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ - reg32 = read_pmbase32(PM1_CNT); + reg32 = pm_read32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP reg32 |= (1 << 1); // enable C3->C0 transition on bus master reg32 |= (1 << 0); // SCI_EN - write_pmbase32(PM1_CNT, reg32); + pm_write32(PM1_CNT, reg32); } static void i82801gx_configure_cstates(struct device *dev) @@ -422,8 +423,6 @@ static void lpc_final(struct device *dev) { - u16 tco1_cnt; - if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; @@ -440,9 +439,7 @@ pci_or_config16(dev, GEN_PMCON_1, 1 << 4); /* TCO_Lock */ - tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT); - tco1_cnt |= (1 << 12); /* TCO lock */ - outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT); + tco_lockdown(); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index b8bc9d8..469c143 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> #include "i82801ix.h" #include "chip.h" @@ -64,8 +65,7 @@ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); /* Reset watchdog. */ - outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ - outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ + tco_clear_timeout(); /* clear timeouts */ /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 54ebcbd..7c69ce5 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -1,15 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> #include <version.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) { - u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - + u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 846c9d8..b35f4c4 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci.h> #include <console/console.h> +#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801ix.h" @@ -196,10 +197,7 @@ i82801ix_hide_functions(); /* Reset watchdog timer. */ -#if !CONFIG(HAVE_SMI_HANDLER) - outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ -#endif - outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ + tco_timer_init(); } struct chip_operations southbridge_intel_i82801ix_ops = { diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index f0b60f6..0c4269a 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -17,7 +17,6 @@ #else # define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ #endif -#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_GPIOBASE 0x00000580 #define APM_CNT 0xb2 diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 24b8a27..d79d040 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -14,9 +14,12 @@ #include <acpi/acpi.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> + #include "chip.h" #include "i82801ix.h" + #include <southbridge/intel/common/pciehp.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba_pirq.h> @@ -140,7 +143,7 @@ static void i82801ix_power_options(struct device *dev) { u8 reg8; - u16 reg16, pmbase; + u16 reg16; u32 reg32; const char *state; /* Get the chip configuration */ @@ -236,24 +239,24 @@ // Set the board's GPI routing. i82801ix_gpi_routing(dev); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; +#define GPE0_EN 0x28 - outl(config->gpe0_en, pmbase + 0x28); - outw(config->alt_gp_smi_en, pmbase + 0x38); + pm_write32(GPE0_EN, config->gpe0_en); + pm_write16(ALT_GP_SMI_EN, config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ - reg16 = inw(pmbase + 0x00); /* PM1_STS */ - outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power + + pm_rwc16(PM1_STS); /* Clear status bits. At least bit11 (power button override) must be cleared or SCI will be constantly fired and OSPM must not know about it (ACPI spec says to ignore the bit). */ /* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */ - reg32 = inl(pmbase + 0x10); + reg32 = pm_read32(0x10); reg32 &= ~(7 << 5); reg32 |= (config->throttle_duty & 7) << 5; - outl(reg32, pmbase + 0x10); + pm_write32(0x10, reg32); } static void i82801ix_configure_cstates(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index f7e880c..32d61d2 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -6,6 +6,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> #include "i82801jx.h" #include "chip.h" @@ -63,8 +64,6 @@ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); } -#define TCO_BASE 0x60 - void i82801jx_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); @@ -80,9 +79,8 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ - write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ - write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + tco_timer_disable_2(); /* halt timer */ + tco_clear_timeout(); /* clear timeouts */ printk(BIOS_DEBUG, " done.\n"); /* Enable IOAPIC */ diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 9d60ca5a..eef22f4 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -1,15 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> #include <version.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) { - u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - + u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index 6f903014..ad46a27 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci.h> #include <console/console.h> +#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801jx.h" @@ -187,10 +188,7 @@ i82801jx_hide_functions(); /* Reset watchdog timer. */ -#if !CONFIG(HAVE_SMI_HANDLER) - outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ -#endif - outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ + tco_timer_init(); } struct chip_operations southbridge_intel_i82801jx_ops = { diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 33386f5..f2c5a92 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -8,7 +8,6 @@ #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #define DEFAULT_PMBASE 0x00000500 -#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_GPIOBASE 0x00000580 #define APM_CNT 0xb2 diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 7dfc33f..26ef42b 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -238,27 +238,27 @@ // Set the board's GPI routing. i82801jx_gpi_routing(dev); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; +#define GPE0_EN 0x28 - outl(config->gpe0_en, pmbase + 0x28); - outw(config->alt_gp_smi_en, pmbase + 0x38); + pm_write32(GPE0_EN, config->gpe0_en); + pm_write16(ALT_GPI_SMI_EN, config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ - reg16 = inw(pmbase + 0x00); /* PM1_STS */ - outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power + pm_rwc16(PM1_STS); /* Clear status bits. At least bit11 (power button override) must be cleared or SCI will be constantly fired and OSPM must not know about it (ACPI spec says to ignore the bit). */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + + reg32 = pm_read32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP - outl(reg32, pmbase + 0x04); + pm_write32(PM1_CNT, reg32); /* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */ - reg32 = inl(pmbase + 0x10); + reg32 = pm_read32(0x10); reg32 &= ~(7 << 5); reg32 |= (config->throttle_duty & 7) << 5; - outl(reg32, pmbase + 0x10); + pm_write32(0x10, reg32); } static void i82801jx_rtc_init(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 4df47f3..4fd4a0d 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -8,6 +8,7 @@ #include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/tco.h> static void early_gpio_init(void) { @@ -42,10 +43,8 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); /* No reset */ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); - /* halt timer */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); - /* halt timer */ - outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); + tco_timer_disable_2(); /* halt timer */ + tco_clear_timeout(); /* clear timeouts */ printk(BIOS_DEBUG, " done.\n"); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0, diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index bdf711b..e7fed0f 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -19,7 +19,7 @@ int i; /* Unlock registers. */ - write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); + pm_setbits16(UPWRC, UPRWC_WR_EN); for (i = 0; i < TOTAL_USB_PORTS; i++) RCBA32_AND_OR(USBIR0 + 4 * i, ~0xfff, currents[portmap[i].current]); @@ -55,5 +55,5 @@ RCBA32(USBOCM2) = reg32; /* Relock registers. */ - write_pmbase16(UPRWC, 0); + pm_write16(UPRWC, 0); } diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index 13243af..e128bc0 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> + #include "chip.h" void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f0d0ac9..e54396d 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -140,7 +140,7 @@ static void pch_power_options(struct device *dev) { u8 reg8; - u16 reg16, pmbase; + u16 reg16; u32 reg32; const char *state; /* Get the chip configuration */ @@ -214,17 +214,14 @@ // Set the board's GPI routing. pch_gpi_routing(dev); - - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - - outl(config->gpe0_en, pmbase + GPE0_EN); - outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + pm_write32(GPE0_EN, config->gpe0_en); + pm_write16(ALT_GP_SMI_EN, config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 = pm_read32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + pm_write32(PM1_CNT, reg32); /* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(PRSTS); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index c42fe0f..60bbe77 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -445,9 +445,9 @@ #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 -#define TCO1_STS 0x64 +#define TCO1_STS 0x04 #define DMISCI_STS (1 << 9) -#define TCO2_STS 0x66 +#define TCO2_STS 0x06 #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 03823ff..f2eb3eb 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -50,7 +50,7 @@ { printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(0x60 | 0x08, (1 << 11)); /* halt timer */ + pm_write16(0x60 | 0x08, (1 << 11)); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); } diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 839773a..8824b8b 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -6,13 +6,14 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> +#include <southbridge/intel/common/tco.h> #include <elog.h> #include "pch.h" static void pch_log_standard_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg) { - u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); - u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; + u32 gpe0_en = pm_read32(gpe0_en_reg); + u32 gpe0_sts = pm_read32(gpe0_sts_reg) & gpe0_en; /* PME (TODO: determine wake device) */ if (gpe0_sts & PME_STS) @@ -30,8 +31,8 @@ static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start) { /* GPE Bank 1 is GPIO 0-31 */ - u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); - u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; + u32 gpe0_en = pm_read32(gpe0_en_reg); + u32 gpe0_sts = pm_read32(gpe0_sts_reg) & gpe0_en; int i; for (i = 0; i <= 31; i++) { @@ -43,7 +44,6 @@ static void pch_log_gpe(void) { int i; - u16 pmbase = get_pmbase(); u32 gpe0_sts, gpe0_en; int gpe0_high_gpios[] = { [0] = 27, @@ -60,8 +60,8 @@ pch_log_standard_gpe(GPE0_EN, GPE0_STS); /* GPIO 0-15 */ - gpe0_en = inw(pmbase + GPE0_EN + 2); - gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; + gpe0_en = pm_read16(GPE0_EN + 2); + gpe0_sts = pm_read16(GPE0_STS + 2) & gpe0_en; for (i = 0; i <= 15; i++) { if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); @@ -71,8 +71,8 @@ * Now check and log upper status bits */ - gpe0_en = inl(pmbase + GPE0_EN_2); - gpe0_sts = inl(pmbase + GPE0_STS_2) & gpe0_en; + gpe0_en = pm_read32(GPE0_EN_2); + gpe0_sts = pm_read32(GPE0_STS_2) & gpe0_en; for (i = 0; i <= 31; i++) { if (!gpe0_high_gpios[i]) @@ -102,8 +102,9 @@ if (!lpc) return; - pm1_sts = inw(get_pmbase() + PM1_STS); - tco2_sts = inw(get_pmbase() + TCO2_STS); + pm1_sts = pm_read16(PM1_STS); + tco2_sts = tco_read16(TCO2_STS); + gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 448ee8b..e723dcf 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -47,9 +47,33 @@ }; } +static __always_inline void gpio_lp_write32(u16 reg, u32 value) +{ + io_write32(get_gpio_base() + reg, value); +} + +static __always_inline u32 gpio_lp_read32(u16 reg) +{ + return io_read32(gpio_base() + addr); +} + +static __always_inline u32 gpio_lp_clrsetbits32(u16 reg, u32 clr, u32 set) +{ + io_clrsetbits32(get_gpio_base() + reg, clr, set); +} + +static __always_inline void gpio_lp_setbits32(const u16 addr, const u32 mask) +{ + io_setbits32(get_gpiobase() + addr, mask); +} + +static __always_inline u16 gpio_lp_rwc16(const u16 addr) +{ + return io_rwc16(get_gpiobase() + addr); +} + void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]) { - u16 gpio_base = get_gpio_base(); const struct pch_lp_gpio_map *config; u32 owner[3] = {0}; u32 route[3] = {0}; @@ -64,8 +88,8 @@ break; /* Setup Configuration registers 1 and 2 */ - outl(config->conf0, gpio_base + GPIO_CONFIG0(gpio)); - outl(config->conf1, gpio_base + GPIO_CONFIG1(gpio)); + gpio_lp_write32(GPIO_CONFIG0(gpio), config->conf0); + gpio_lp_write32(GPIO_CONFIG1(gpio), config->conf1); /* Determine set and bit based on GPIO number */ set = gpio >> 5; @@ -89,24 +113,22 @@ } for (set = 0; set <= 2; set++) { - outl(owner[set], gpio_base + GPIO_OWNER(set)); - outl(route[set], gpio_base + GPIO_ROUTE(set)); - outl(irqen[set], gpio_base + GPIO_IRQ_IE(set)); - outl(reset[set], gpio_base + GPIO_RESET(set)); + gpio_lp_write32(GPIO_OWNER(set), owner[set]); + gpio_lp_write32(GPIO_ROUTE(set), route[set]); + gpio_lp_write32(GPIO_IRQ_IE(set), irqen[set]); + gpio_lp_write32(GPIO_RESET(set), reset[set]); } - outl(blink, gpio_base + GPIO_BLINK); - outl(pirq2apic, gpio_base + GPIO_PIRQ_APIC_EN); + gpio_lp_write32(GPIO_BLINK, blink); + gpio_lp_write32(GPIO_PIRQ_APIC_EN, pirq2apic); } int get_gpio(int gpio_num) { - u16 gpio_base = get_gpio_base(); - if (gpio_num > MAX_GPIO_NUMBER) return 0; - return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); + return !!(gpio_lp_read32(GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); } /* @@ -130,21 +152,13 @@ void set_gpio(int gpio_num, int value) { - u16 gpio_base = get_gpio_base(); - u32 conf0; - if (gpio_num > MAX_GPIO_NUMBER) return; - conf0 = inl(gpio_base + GPIO_CONFIG0(gpio_num)); - conf0 &= ~GPO_LEVEL_MASK; - conf0 |= value << GPO_LEVEL_SHIFT; - outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num)); -} + gpio_lp_clrsetbits32(GPIO_CONFIG0(gpio_num), GPO_LEVEL_MASK, value << GPO_LEVEL_SHIFT); + int gpio_is_native(int gpio_num) { - u16 gpio_base = get_gpio_base(); - - return !(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & 1); + return !(gpio_lp_read32(GPIO_CONFIG0(gpio_num)) & 1); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b8e9d5f..f139b6d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -259,10 +259,10 @@ } /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 = pm_read32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + pm_write32(PM1_CNT, reg32); /* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(0x3310); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 8f7cdb8..a307f5f 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -56,14 +56,9 @@ return PCH_TYPE_DESKTOP; } -u16 get_pmbase(void) +u16 lpc_get_pmbase(void) { - static u16 pmbase; - - if (!pmbase) - pmbase = pci_read_config16(pch_get_lpc_device(), - PMBASE) & 0xfffc; - return pmbase; + return pci_read_config16(pch_get_lpc_device(), PMBASE) & 0xfffc; } u16 get_gpiobase(void) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index dcd3ce5..44c55d0 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -120,7 +120,6 @@ enum pch_platform_type get_pch_platform_type(void); int pch_silicon_revision(void); int pch_silicon_id(void); -u16 get_pmbase(void); u16 get_gpiobase(void); /* Power Management register handling in pmutil.c */ @@ -619,10 +618,11 @@ #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 -#define TCO1_STS 0x64 +#define TCO1_STS 0x04 #define DMISCI_STS (1 << 9) -#define TCO2_STS 0x66 +#define TCO2_STS 0x06 #define SECOND_TO_STS (1 << 1) + #define ALT_GP_SMI_EN2 0x5c #define ALT_GP_SMI_STS2 0x5e diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index dd7f199..9b40d22 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -13,6 +13,7 @@ #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/common/tco.h> #include "pch.h" #if CONFIG(INTEL_LYNXPOINT_LP) @@ -62,19 +63,15 @@ */ /* Enable events in PM1 control register */ -void enable_pm1_control(u32 mask) +void enable_pm1_control(uint32_t mask) { - u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, get_pmbase() + PM1_CNT); + pm_setbits32(PM1_CNT, mask); } /* Disable events in PM1 control register */ -void disable_pm1_control(u32 mask) +void disable_pm1_control(uint32_t mask) { - u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, get_pmbase() + PM1_CNT); + pm_clrbits32(PM1_CNT, mask); } /* @@ -84,9 +81,7 @@ /* Clear and return PM1 status register */ static u16 reset_pm1_status(void) { - u16 pm1_sts = inw(get_pmbase() + PM1_STS); - outw(pm1_sts, get_pmbase() + PM1_STS); - return pm1_sts; + return pm_rwc16(PM1_STS); } /* Print PM1 status bits */ @@ -122,7 +117,7 @@ /* Set the PM1 register to events */ void enable_pm1(u16 events) { - outw(events, get_pmbase() + PM1_EN); + pm_write16(PM1_EN, events); } /* @@ -132,9 +127,7 @@ /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(get_pmbase() + SMI_STS); - outl(smi_sts, get_pmbase() + SMI_STS); - return smi_sts; + return pm_rwc32(SMI_STS); } /* Print SMI status bits */ @@ -180,19 +173,15 @@ } /* Enable SMI event */ -void enable_smi(u32 mask) +void enable_smi(uint32_t mask) { - u32 smi_en = inl(get_pmbase() + SMI_EN); - smi_en |= mask; - outl(smi_en, get_pmbase() + SMI_EN); + pm_setbits32(SMI_EN, mask); } /* Disable SMI event */ -void disable_smi(u32 mask) +void disable_smi(uint32_t mask) { - u32 smi_en = inl(get_pmbase() + SMI_EN); - smi_en &= ~mask; - outl(smi_en, get_pmbase() + SMI_EN); + pm_clrbits32(SMI_EN, mask); } /* @@ -206,24 +195,17 @@ if (pch_is_lp()) { /* LynxPoint-LP moves this to GPIO region as dword */ - alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS); - outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS); - - alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); + alt_sts = gpio_lp_rwc32(GPIO_ALT_GPI_SMI_STS); + alt_en = gpio_lp_read32(GPIO_ALT_GPI_SMI_EN); } else { - u16 pmbase = get_pmbase(); - /* LynxPoint-H adds a second enable/status word */ - alt_sts = inw(pmbase + ALT_GP_SMI_STS2); - outw(alt_sts & 0xffff, pmbase + ALT_GP_SMI_STS2); + u16 alt_sts_h = pm_rwc16(ALT_GP_SMI_STS2); + u16 alt_sts_l = pm_rwc16(ALT_GP_SMI_STS); + alt_sts = (alt_sts_h << 16) | alt_sts_l; - alt_sts <<= 16; - alt_sts |= inw(pmbase + ALT_GP_SMI_STS); - outw(alt_sts & 0xffff, pmbase + ALT_GP_SMI_STS); - - alt_en = inw(pmbase + ALT_GP_SMI_EN2); + alt_en = pm_read16(ALT_GP_SMI_EN2); alt_en <<= 16; - alt_en |= inw(pmbase + ALT_GP_SMI_EN); + alt_en |= pm_read16(ALT_GP_SMI_EN); } /* Only report enabled events */ @@ -273,24 +255,14 @@ void enable_alt_smi(u32 mask) { if (pch_is_lp()) { - u32 alt_en; + gpio_lp_setbits32(GPIO_ALT_GPI_SMI_EN, mask); - alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); - alt_en |= mask; - outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN); } else { - u16 pmbase = get_pmbase(); - u16 alt_en; - /* Lower enable register */ - alt_en = inw(pmbase + ALT_GP_SMI_EN); - alt_en |= mask & 0xffff; - outw(alt_en, pmbase + ALT_GP_SMI_EN); + pm_setbits16(ALT_GP_SMI_EN, mask & 0xffff); /* Upper enable register */ - alt_en = inw(pmbase + ALT_GP_SMI_EN2); - alt_en |= (mask >> 16) & 0xffff; - outw(alt_en, pmbase + ALT_GP_SMI_EN2); + pm_setbits16(ALT_GP_SMI_EN_2, mask >> 16); } } @@ -298,22 +270,6 @@ * TCO */ -/* Clear TCO status and return events that are active */ -static u32 reset_tco_status(void) -{ - u32 tcobase = get_pmbase() + 0x60; - u32 tco_sts = inl(tcobase + 0x04); - - /* Don't clear BOOT_STS before SECOND_TO_STS */ - outl(tco_sts & ~(1 << 18), tcobase + 0x04); - - /* Clear BOOT_STS */ - if (tco_sts & (1 << 18)) - outl(tco_sts & (1 << 18), tcobase + 0x04); - - return tco_sts; -} - /* Print TCO status bits */ static u32 print_tco_status(u32 tco_sts) { @@ -347,16 +303,17 @@ /* Print, clear, and return TCO status */ u32 clear_tco_status(void) { - return print_tco_status(reset_tco_status()); + return print_tco_status(tco_reset_status()); } /* Enable TCO SCI */ void enable_tco_sci(void) { - u16 gpe0_sts = pch_is_lp() ? LP_GPE0_STS_4 : GPE0_STS; - /* Clear pending events */ - outl(TCOSCI_STS, get_pmbase() + gpe0_sts); + if (pch_is_lp()) + pm_write32(LP_GPE0_STS_4, TCOSCI_STS); + else + pm_write32(GPE0_STS, TCOSCI_STS); /* Enable TCO SCI events */ enable_gpe(TCOSCI_EN); @@ -369,10 +326,8 @@ /* Clear a GPE0 status and return events that are enabled and active */ static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { - u32 gpe0_sts = inl(get_pmbase() + sts_reg); - u32 gpe0_en = inl(get_pmbase() + en_reg); - - outl(gpe0_sts, get_pmbase() + sts_reg); + u32 gpe0_sts = pm_rwc32(sts_reg); + u32 gpe0_en = pm_read32(en_reg); /* Only report enabled events */ return gpe0_sts & gpe0_en; @@ -499,16 +454,14 @@ /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) { - u16 pmbase = get_pmbase(); - if (pch_is_lp()) { - outl(set1, pmbase + LP_GPE0_EN_1); - outl(set2, pmbase + LP_GPE0_EN_2); - outl(set3, pmbase + LP_GPE0_EN_3); - outl(set4, pmbase + LP_GPE0_EN_4); + pm_write32(LP_GPE0_EN_1, set1); + pm_write32(LP_GPE0_EN_2, set2); + pm_write32(LP_GPE0_EN_3, set3); + pm_write32(LP_GPE0_EN_4, set4); } else { - outl(set1, pmbase + GPE0_EN); - outl(set2, pmbase + GPE0_EN_2); + pm_write32(GPE0_EN, set1); + pm_write32(GPE0_EN_2, set2); } } @@ -521,17 +474,17 @@ /* Enable a standard GPE */ void enable_gpe(u32 mask) { - u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; - u32 gpe0_en = inl(get_pmbase() + gpe0_reg); - gpe0_en |= mask; - outl(gpe0_en, get_pmbase() + gpe0_reg); + if (pch_is_lp()) + pm_setbits32(LP_GPE0_EN_4, mask); + else + pm_setbits32(GPE0_EN, mask); } /* Disable a standard GPE */ void disable_gpe(u32 mask) { - u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; - u32 gpe0_en = inl(get_pmbase() + gpe0_reg); - gpe0_en &= ~mask; - outl(gpe0_en, get_pmbase() + gpe0_reg); + if (pch_is_lp()) + pm_clrbits32(LP_GPE0_EN_4, mask); + else + pm_clrbits32(GPE0_EN, mask); } diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 6edf5c1..0ef7255 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -17,17 +17,12 @@ if (CONFIG(ELOG)) pch_log_state(); - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); - - smi_en = inl(get_pmbase() + SMI_EN); + smi_en = pm_read32(SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } - printk(BIOS_DEBUG, "\n"); - /* Dump and clear status registers */ clear_smi_status(); clear_pm1_status(); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 769cacb..a80100b 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -95,13 +95,12 @@ { u32 reg32; u8 slp_typ; - u16 pmbase = get_pmbase(); /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -174,7 +173,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = pm_read32(PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -328,7 +327,7 @@ static void southbridge_smi_mc(void) { - u32 reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = pm_read32(SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -371,7 +370,7 @@ static void southbridge_smi_periodic(void) { - u32 reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = pm_read32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/69760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Gerrit-Change-Number: 69760 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022