coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[M] Change in coreboot[master]: src/drivers: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69803 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/drivers: Remove unnecessary space after casts ...................................................................... src/drivers: Remove unnecessary space after casts Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69803 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/amd/agesa/heapmanager.c M src/drivers/aspeed/common/ast_post.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/tpm/tis.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_ops.c M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/ipmi/ocp/ipmi_ocp_romstage.c M src/drivers/ipmi/supermicro_oem.c M src/drivers/net/ne2k.c M src/drivers/pc80/vga/vga.c M src/drivers/pc80/vga/vga_io.c 14 files changed, 58 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index 26947f1..8a82efe 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -42,7 +42,7 @@ memset(base, 0, BIOS_HEAP_SIZE); printk(BIOS_DEBUG, "Wiped HEAP at [%08x - %08x]\n", - (unsigned int)(uintptr_t)base, (unsigned int)(uintptr_t) base + BIOS_HEAP_SIZE - 1); + (unsigned int)(uintptr_t)base, (unsigned int)(uintptr_t)base + BIOS_HEAP_SIZE - 1); } #if defined(HEAP_CALLOUT_RUNTIME) && ENV_RAMSTAGE @@ -345,7 +345,7 @@ } } - AllocParams->BufferPointer = (UINT8 *)((UINT8 *) AllocNodePtr + sizeof(BIOS_BUFFER_NODE)); + AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE)); AllocParams->BufferLength = AllocNodePtr->BufferSize; return AGESA_SUCCESS; diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index 08bc42c..856e4e5 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -740,9 +740,9 @@ passcnt[dqsip]++; tag[dqsip][dlli] = 'P'; if (dlli < pass[dqidly][dqsip][0]) - pass[dqidly][dqsip][0] = (u16) dlli; + pass[dqidly][dqsip][0] = (u16)dlli; if (dlli > pass[dqidly][dqsip][1]) - pass[dqidly][dqsip][1] = (u16) dlli; + pass[dqidly][dqsip][1] = (u16)dlli; } else if (passcnt[dqsip] >= 5) break; else { diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 25ed98a..46719dc 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -63,7 +63,7 @@ static void ptn3460_init(struct device *dev) { struct ptn_3460_config cfg; - uint8_t edid_data[PTN_EDID_LEN], edid_tab, *ptr = (uint8_t *) &cfg; + uint8_t edid_data[PTN_EDID_LEN], edid_tab, *ptr = (uint8_t *)&cfg; int i, val; /* Guard against re-initialization of the device */ @@ -108,7 +108,7 @@ /* Mainboard can modify the configuration data. Write back configuration data to PTN3460 if modified by mainboard */ if (mb_adjust_cfg(&cfg) == PTN_CFG_MODIFIED) { - ptr = (uint8_t *) &cfg; + ptr = (uint8_t *)&cfg; for (i = 0; i < sizeof(struct ptn_3460_config); i++) { val = i2c_dev_writeb_at(dev, PTN_CONFIG_OFF + i, *ptr++); if (val < 0) { diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 80de2df..ea8cf3d 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -78,7 +78,7 @@ } ASSERT(chip.vendor.send); - rc = chip.vendor.send(&chip, (uint8_t *) sbuf, count); + rc = chip.vendor.send(&chip, (uint8_t *)sbuf, count); if (rc < 0) { printk(BIOS_DEBUG, "%s: tpm_send error\n", __func__); goto out; @@ -111,7 +111,7 @@ out_recv: - rc = chip.vendor.recv(&chip, (uint8_t *) rbuf, rbufsiz); + rc = chip.vendor.recv(&chip, (uint8_t *)rbuf, rbufsiz); if (rc < 0) printk(BIOS_DEBUG, "%s: tpm_recv: error %d\n", __func__, rc); out: diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index f0f580b..aae1ff8 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -261,14 +261,14 @@ tcount = fvih->Count; #elif CONFIG(DISPLAY_FSP_VERSION_INFO_2) - uint8_t *hobstart = (uint8_t *) hob; + uint8_t *hobstart = (uint8_t *)hob; hobstart += sizeof(EFI_HOB_GUID_TYPE); const SMBIOS_TABLE_TYPE_OEM_INTEL_FVI *stfvi = (SMBIOS_TABLE_TYPE_OEM_INTEL_FVI *)hobstart; const INTEL_FIRMWARE_VERSION_INFO *fvi; - str_ptr = ((char *) &(stfvi->Fvi[0])) + + str_ptr = ((char *)&(stfvi->Fvi[0])) + (stfvi->Count * sizeof(INTEL_FIRMWARE_VERSION_INFO)); tcount = stfvi->Count; fvi = &stfvi->Fvi[0]; diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 87f77a2..678892a 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -96,7 +96,7 @@ struct fsp_multi_phase_params multi_phase_params; struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; - supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base); + supd = (FSPS_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE); @@ -127,7 +127,7 @@ soc_load_logo(upd); /* Call SiliconInit */ - silicon_init = (void *) (uintptr_t)(hdr->image_base + + silicon_init = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_silicon_init_entry_offset); fsp_debug_before_silicon_init(silicon_init, supd, upd); @@ -165,7 +165,7 @@ return; /* Call MultiPhaseSiInit */ - multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base + + multi_phase_si_init = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_multi_phase_si_init_entry_offset); /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index f165307..844eb8e 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -36,8 +36,8 @@ while (retry_count <= MAX_FRU_BUSY_RETRY) { ret = ipmi_message(port, IPMI_NETFN_STORAGE, 0x0, - IPMI_READ_FRU_DATA, (const unsigned char *) req, - sizeof(*req), (unsigned char *) &rsp, sizeof(rsp)); + IPMI_READ_FRU_DATA, (const unsigned char *)req, + sizeof(*req), (unsigned char *)&rsp, sizeof(rsp)); if (rsp.resp.completion_code == 0x81) { /* Device is busy */ if (retry_count == MAX_FRU_BUSY_RETRY) { diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index d9b3256..18547c5 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -21,8 +21,8 @@ req.initial_countdown_val = countdown; ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_SET_WDG_TIMER, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { printk(BIOS_ERR, "IPMI: %s set wdt command failed " @@ -35,7 +35,7 @@ /* Reset command to start timer */ ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_RESET_WDG_TIMER, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { printk(BIOS_ERR, "IPMI: %s reset wdt command failed " @@ -59,7 +59,7 @@ /* Get current timer first */ ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_GET_WDG_TIMER, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s get wdt command failed " @@ -79,8 +79,8 @@ req = rsp.data; ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_SET_WDG_TIMER, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &resp, sizeof(resp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&resp, sizeof(resp)); if (ret < sizeof(struct ipmi_rsp) || resp.completion_code) { printk(BIOS_ERR, "IPMI: %s set wdt command stop timer failed " @@ -107,7 +107,7 @@ ret = ipmi_message(port, IPMI_NETFN_APPLICATION, 0x0, IPMI_BMC_GET_SYSTEM_GUID, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", @@ -130,8 +130,8 @@ } ret = ipmi_message(port, IPMI_NETFN_STORAGE, 0x0, - IPMI_ADD_SEL_ENTRY, (const unsigned char *) sel, - 16, (unsigned char *) &rsp, sizeof(rsp)); + IPMI_ADD_SEL_ENTRY, (const unsigned char *)sel, + 16, (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.c b/src/drivers/ipmi/ocp/ipmi_ocp.c index 9f583be..e75edca 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.c +++ b/src/drivers/ipmi/ocp/ipmi_ocp.c @@ -29,8 +29,8 @@ req.cpu1_hi = xeon_sp_ppin[1].hi; } ret = ipmi_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", diff --git a/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c b/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c index 7b0b9ea..8ef379e 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c +++ b/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c @@ -11,7 +11,7 @@ struct ipmi_rsp rsp; ret = ipmi_message(port, IPMI_NETFN_OEM, 0x0, - IPMI_BMC_SET_POST_START, NULL, 0, (u8 *) &rsp, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { @@ -45,7 +45,7 @@ ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BIOS_BOOT_ORDER, NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (read ret=%d resp=0x%x)\n", @@ -58,8 +58,8 @@ SET_CMOS_AND_VALID_BIT(req.boot_mode); ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_BIOS_BOOT_ORDER, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&req, sizeof(req), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { printk(BIOS_ERR, "IPMI: %s command failed (sent ret=%d resp=0x%x)\n", diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c index 7af4e3b..c63da5f 100644 --- a/src/drivers/ipmi/supermicro_oem.c +++ b/src/drivers/ipmi/supermicro_oem.c @@ -36,8 +36,8 @@ bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_VER; ret = ipmi_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, - (const unsigned char *) &bios_ver, sizeof(bios_ver), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&bios_ver, sizeof(bios_ver), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(rsp) || rsp.completion_code) { printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", __func__, ret, rsp.completion_code); @@ -55,8 +55,8 @@ bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_DATE; ret = ipmi_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, - (const unsigned char *) &bios_ver, sizeof(bios_ver), - (unsigned char *) &rsp, sizeof(rsp)); + (const unsigned char *)&bios_ver, sizeof(bios_ver), + (unsigned char *)&rsp, sizeof(rsp)); if (ret < sizeof(rsp) || rsp.completion_code) { printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", __func__, ret, rsp.completion_code); diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 235c909..e0dc58b 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -281,7 +281,7 @@ c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET); outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET); - (void) inb(0x84); + (void)inb(0x84); outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND); outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index dde0355..d970fea 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -186,7 +186,7 @@ /* plane 2 */ vga_sr_write(0x02, 0x04); - p = (unsigned char *) VGA_FB; + p = (unsigned char *)VGA_FB; for (i = 0; i < count; i++) { for (j = 0; j < 32; j++) { if (j < height) @@ -262,7 +262,7 @@ void vga_line_write(unsigned int line, const char *string) { - unsigned short *p = (unsigned short *) VGA_FB + (80 * line); + unsigned short *p = (unsigned short *)VGA_FB + (80 * line); int i, len = strlen(string); for (i = 0; i < 80; i++) { diff --git a/src/drivers/pc80/vga/vga_io.c b/src/drivers/pc80/vga/vga_io.c index e4b1eb9..2bf2af4 100644 --- a/src/drivers/pc80/vga/vga_io.c +++ b/src/drivers/pc80/vga/vga_io.c @@ -147,10 +147,10 @@ { unsigned char ret; - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(index, VGA_AR_INDEX); ret = inb(VGA_AR_VALUE_READ); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); return ret; } @@ -158,10 +158,10 @@ void vga_ar_write(unsigned char index, unsigned char value) { - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(index, VGA_AR_INDEX); outb(value, VGA_AR_VALUE_WRITE); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); } void @@ -209,17 +209,17 @@ void vga_palette_enable(void) { - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(0x00, VGA_AR_INDEX); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); } void vga_palette_disable(void) { - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); outb(0x20, VGA_AR_INDEX); - (void) inb(VGA_STAT1); + (void)inb(VGA_STAT1); } unsigned char -- To view, visit https://review.coreboot.org/c/coreboot/+/69803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf Gerrit-Change-Number: 69803 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Marvin Drees (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Arthur Heymans, Martin Roth, Fred Reitberger, Felix Held. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 13:25:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: device/mdio: Provide helper functions for read and write
by Arthur Heymans (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Mario Scheithauer, Angel Pons, Werner Zeh. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69611 ) Change subject: device/mdio: Provide helper functions for read and write ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/device/mdio.c: https://review.coreboot.org/c/coreboot/+/69611/comment/53ffa39f_a5d6b70d PS4, Line 27: 0 > Yes, the error log was the one I had in mind for debug purposes. Is it OK to fully rely on that? Yes. C is sadly not like golang where you can easily return tuples of error and values :-). The writes should fail for the same reason so things are then just a noop with error messages -- To view, visit https://review.coreboot.org/c/coreboot/+/69611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I293d93435d27269a071b4b9b94a1b55307c575a7 Gerrit-Change-Number: 69611 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 13:25:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: device/mdio: Provide helper functions for read and write
by Werner Zeh (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Mario Scheithauer, Angel Pons, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69611 ) Change subject: device/mdio: Provide helper functions for read and write ...................................................................... Patch Set 5: (1 comment) File src/device/mdio.c: https://review.coreboot.org/c/coreboot/+/69611/comment/c6879ec6_47e6507c PS4, Line 27: 0 > There's the error print in `dev_get_mdio_ops()` which should suffice. Yes, the error log was the one I had in mind for debug purposes. Is it OK to fully rely on that? -- To view, visit https://review.coreboot.org/c/coreboot/+/69611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I293d93435d27269a071b4b9b94a1b55307c575a7 Gerrit-Change-Number: 69611 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 22 Nov 2022 13:22:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/ehl: Add MDIO operation to TSN GbE device
by Arthur Heymans (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Mario Scheithauer, Angel Pons, Lean Sheng Tan. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add MDIO operation to TSN GbE device ...................................................................... Patch Set 12: (1 comment) File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/0b8fa8cf_a7c7d4dd PS12, Line 161: & > Are you sure? If I do this without address operator '&', I get a compiler error 'incompatible types'. Eh it's a struct. My bad. -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 12 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 13:19:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/ehl: Add MDIO operation to TSN GbE device
by Mario Scheithauer (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add MDIO operation to TSN GbE device ...................................................................... Patch Set 12: (2 comments) File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/7ac3378d_075409b8 PS12, Line 104: (void *)(uintptr_t)gbe_tsn_res->base > Use res2mmio I will change this from 'gbe_tsn_res' to 'res2mmio'. https://review.coreboot.org/c/coreboot/+/69383/comment/d739bc34_ccb8c8e9 PS12, Line 161: & > & is not needed with function pointers. Are you sure? If I do this without address operator '&', I get a compiler error 'incompatible types'. -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 12 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 13:13:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: src/include: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69802 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/include: Remove unnecessary space after casts ...................................................................... src/include: Remove unnecessary space after casts Change-Id: Ie6def0dab9ac37c0938b73d27148a49531c6b17f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69802 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_rom.h 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index efda282..83015a1 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -8,7 +8,7 @@ #include <stdint.h> #define PCI_ROM_HDR 0xAA55 -#define PCI_DATA_HDR ((uint32_t) (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) +#define PCI_DATA_HDR ((uint32_t)(('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) #define PCI_RAM_IMAGE_START 0xD0000 #define PCI_VGA_RAM_IMAGE_START 0xC0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/69802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6def0dab9ac37c0938b73d27148a49531c6b17f Gerrit-Change-Number: 69802 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src/cpu: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69801 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/cpu: Remove unnecessary space after casts ...................................................................... src/cpu: Remove unnecessary space after casts Change-Id: I12463d4d26c03c85fa018b421bb9166fbfeb0b60 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69801 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/car/romstage.c 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 4c68ded..c7c218b 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -32,7 +32,7 @@ printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n", size); - stack_base = (u32 *) (_ecar_stack - size); + stack_base = (u32 *)(_ecar_stack - size); for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; -- To view, visit https://review.coreboot.org/c/coreboot/+/69801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12463d4d26c03c85fa018b421bb9166fbfeb0b60 Gerrit-Change-Number: 69801 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: security: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69800 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: security: Remove unnecessary space after casts ...................................................................... security: Remove unnecessary space after casts Change-Id: Ibd41382d0e0ef58498ac925dc9e10b54a76a798a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69800 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/intel/stm/StmPlatformSmm.c M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/vboot/vbnv.c 4 files changed, 26 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index bcf935c..e5b3cf1 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -85,7 +85,7 @@ TXT_PROCESSOR_SMM_DESCRIPTOR *psd; - smbase_processor = (void *) SMM_DEFAULT_BASE;//we are here + smbase_processor = (void *)SMM_DEFAULT_BASE;//we are here psd = smbase + SMM_PSD_OFFSET; printk(BIOS_DEBUG, @@ -121,8 +121,8 @@ read_gdtr(&gdtr); - gdtr.base -= (uintptr_t) smbase_processor; - gdtr.base += (uintptr_t) smbase; + gdtr.base -= (uintptr_t)smbase_processor; + gdtr.base += (uintptr_t)smbase; psd->smm_gdt_ptr = gdtr.base; psd->smm_gdt_size = gdtr.limit + 1; // the stm will subtract, so add @@ -159,7 +159,7 @@ // some processor to receive a bad value // calculate the location in SMRAM addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; - stm_resource_heap = (uint8_t *) addr_calc; + stm_resource_heap = (uint8_t *)addr_calc; if (cpu == 0) { diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 6b79aab..39c44ec 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -51,7 +51,7 @@ { uint32_t size; from_tpm_uint32(buffer + sizeof(uint16_t), &size); - return (int) size; + return (int)size; } /* Gets the code field of a TPM command. */ diff --git a/src/security/tpm/tss/tcg-1.2/tss_structures.h b/src/security/tpm/tss/tcg-1.2/tss_structures.h index 4a976c8..689bb4b 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_structures.h +++ b/src/security/tpm/tss/tcg-1.2/tss_structures.h @@ -21,13 +21,13 @@ #define TPM_NV_PER_READ_STCLEAR (((uint32_t)1)<<31) #define TPM_NV_PER_WRITE_STCLEAR (((uint32_t)1)<<14) -#define TPM_TAG_RQU_COMMAND ((uint16_t) 0xc1) -#define TPM_TAG_RQU_AUTH1_COMMAND ((uint16_t) 0xc2) -#define TPM_TAG_RQU_AUTH2_COMMAND ((uint16_t) 0xc3) +#define TPM_TAG_RQU_COMMAND ((uint16_t)0xc1) +#define TPM_TAG_RQU_AUTH1_COMMAND ((uint16_t)0xc2) +#define TPM_TAG_RQU_AUTH2_COMMAND ((uint16_t)0xc3) -#define TPM_TAG_RSP_COMMAND ((uint16_t) 0xc4) -#define TPM_TAG_RSP_AUTH1_COMMAND ((uint16_t) 0xc5) -#define TPM_TAG_RSP_AUTH2_COMMAND ((uint16_t) 0xc6) +#define TPM_TAG_RSP_COMMAND ((uint16_t)0xc4) +#define TPM_TAG_RSP_AUTH1_COMMAND ((uint16_t)0xc5) +#define TPM_TAG_RSP_AUTH2_COMMAND ((uint16_t)0xc6) typedef uint8_t TSS_BOOL; typedef uint16_t TPM_STRUCTURE_TAG; diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 26946fd..e9223c0 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -24,7 +24,7 @@ } } - return (uint8_t) (crc >> 8); + return (uint8_t)(crc >> 8); } void vbnv_reset(uint8_t *vbnv_copy) -- To view, visit https://review.coreboot.org/c/coreboot/+/69800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd41382d0e0ef58498ac925dc9e10b54a76a798a Gerrit-Change-Number: 69800 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/nivviks,yaviks: Remove ISH firmware-name
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69868 ) Change subject: mb/google/nissa/var/nivviks,yaviks: Remove ISH firmware-name ...................................................................... mb/google/nissa/var/nivviks,yaviks: Remove ISH firmware-name For nissa, the ISH main firmware will be included in the CSE region in flash instead of loading it from rootfs. So remove the ISH firmware-name. BUG=b:234776154 TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not loaded by kernel, and device still goes to S0i3. Cq-Depend: chrome-internal:5102230 Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/brya/variants/nivviks/overridetree.cb M src/mainboard/google/brya/variants/yaviks/overridetree.cb 2 files changed, 24 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 9567d4f..76fe43e 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -519,10 +519,6 @@ probe STORAGE STORAGE_EMMC end device ref ish on - chip drivers/intel/ish - register "firmware_name" = ""adl_ish_lite.bin"" - device generic 0 on end - end probe STORAGE STORAGE_UFS end device ref ufs on diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb index c3b98b5..6b57ada 100644 --- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb @@ -212,12 +212,7 @@ end end device ref emmc on end - device ref ish on - chip drivers/intel/ish - register "firmware_name" = ""adl_ish_lite.bin"" - device generic 0 on end - end - end + device ref ish on end device ref ufs on end device ref pch_espi on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/69868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b Gerrit-Change-Number: 69868 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022