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[S] Change in coreboot[master]: src/commonlib: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69817 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/commonlib: Remove unnecessary space after casts ...................................................................... src/commonlib: Remove unnecessary space after casts Change-Id: Ib20f02cc9e5be0efea8bc29fce6bd148adf28ead Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69817 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/fsp_relocate.c M src/commonlib/storage/bouncebuf.h M src/commonlib/storage/sdhci_adma.c M src/commonlib/storage/storage.h 4 files changed, 19 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 55295ca..ad24ca7 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -233,13 +233,13 @@ uint32_t i; EFI_IMAGE_DATA_DIRECTORY *relocd; - relocd = (void *) &pe_base[offset]; + relocd = (void *)&pe_base[offset]; offset += sizeof(*relocd); // Read relocation type, offset pairs rlen = read_le32(&relocd->Size) - sizeof(*relocd); rnum = rlen / sizeof(uint16_t); vaddr = read_le32(&relocd->VirtualAddress); - rdata = (uint16_t *) &pe_base[offset]; + rdata = (uint16_t *)&pe_base[offset]; printk(FSP_DBG_LVL, "\t%d Relocs for RVA %x\n", rnum, vaddr); for (i = 0; i < rnum; i++) { diff --git a/src/commonlib/storage/bouncebuf.h b/src/commonlib/storage/bouncebuf.h index 9e3ab74..fce3fbd 100644 --- a/src/commonlib/storage/bouncebuf.h +++ b/src/commonlib/storage/bouncebuf.h @@ -76,7 +76,7 @@ #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ char __##name[ROUND(size * sizeof(type), DMA_MINALIGN) + \ DMA_MINALIGN - 1]; \ - type *name = (type *) ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) + type *name = (type *)ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) #ifndef ARCH_DMA_MINALIGN #define ARCH_DMA_MINALIGN (DMA_MINALIGN) #endif diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 92f938f..9ad949e 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -120,10 +120,10 @@ } if (dma64) - sdhci_writel(sdhci_ctrlr, (uintptr_t) sdhci_ctrlr->adma64_descs, + sdhci_writel(sdhci_ctrlr, (uintptr_t)sdhci_ctrlr->adma64_descs, SDHCI_ADMA_ADDRESS); else - sdhci_writel(sdhci_ctrlr, (uintptr_t) sdhci_ctrlr->adma_descs, + sdhci_writel(sdhci_ctrlr, (uintptr_t)sdhci_ctrlr->adma_descs, SDHCI_ADMA_ADDRESS); return 0; diff --git a/src/commonlib/storage/storage.h b/src/commonlib/storage/storage.h index cdd5e6c..5f51ba9 100644 --- a/src/commonlib/storage/storage.h +++ b/src/commonlib/storage/storage.h @@ -11,7 +11,7 @@ #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ char __##name[ROUND(size * sizeof(type), DMA_MINALIGN) + \ DMA_MINALIGN - 1]; \ - type *name = (type *) ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) + type *name = (type *)ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN) /* NOOPs mirroring ARM's cache API, since x86 devices usually cache snoop */ #define dcache_invalidate_by_mva(addr, len) -- To view, visit https://review.coreboot.org/c/coreboot/+/69817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib20f02cc9e5be0efea8bc29fce6bd148adf28ead Gerrit-Change-Number: 69817 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src/arch: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69816 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/arch: Remove unnecessary space after casts ...................................................................... src/arch: Remove unnecessary space after casts Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69816 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/arm/eabi_compat.c M src/arch/arm/libgcc/umoddi3.c M src/arch/riscv/trap_handler.c M src/arch/x86/cpu.c M src/arch/x86/memset.c M src/arch/x86/pirq_routing.c 6 files changed, 22 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index cbc285c..2a110d5 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -26,11 +26,11 @@ void __aeabi_memcpy(void *dest, const void *src, size_t n); void __aeabi_memcpy(void *dest, const void *src, size_t n) { - (void) memcpy(dest, src, n); + (void)memcpy(dest, src, n); } void __aeabi_memset(void *dest, size_t n, int c); void __aeabi_memset(void *dest, size_t n, int c) { - (void) memset(dest, c, n); + (void)memset(dest, c, n); } diff --git a/src/arch/arm/libgcc/umoddi3.c b/src/arch/arm/libgcc/umoddi3.c index 5d2ede7..c84e9e4 100644 --- a/src/arch/arm/libgcc/umoddi3.c +++ b/src/arch/arm/libgcc/umoddi3.c @@ -4,6 +4,6 @@ uint64_t __umoddi3(uint64_t num, uint64_t den) { uint64_t v; - (void) __udivmoddi4(num, den, &v); + (void)__udivmoddi4(num, den, &v); return v; } diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index f940f63..f5953d3 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -64,8 +64,8 @@ previous_mode, mprv? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr); - printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); - printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + printk(BIOS_DEBUG, "Stored ra: %p\n", (void *)tf->gpr[1]); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void *)tf->gpr[2]); } static void interrupt_handler(trapframe *tf) diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 6a8ddef..9fc5233 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -59,7 +59,7 @@ : "cc"); /* AH is 0x02 on Cyrix after the divide.. */ - return (unsigned char) (test >> 8) == 0x02; + return (unsigned char)(test >> 8) == 0x02; } /* diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index fc09a9b..8a0165b 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -12,7 +12,7 @@ void *memset(void *dstpp, int c, size_t len) { int d0; - unsigned long int dstp = (unsigned long int) dstpp; + unsigned long int dstp = (unsigned long int)dstpp; #if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) @@ -22,7 +22,7 @@ /* This explicit register allocation improves code very much indeed. */ register op_t x asm("ax"); - x = (unsigned char) c; + x = (unsigned char)c; /* Clear the direction flag, so filling will move forward. */ asm volatile("cld"); diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 362650d..0da057f 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -17,7 +17,7 @@ if (sizeof(struct irq_routing_table) != rt->size) { printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", - (unsigned int) sizeof(struct irq_routing_table), + (unsigned int)sizeof(struct irq_routing_table), rt->size); rt->size = sizeof(struct irq_routing_table); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78 Gerrit-Change-Number: 69816 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: src/northbridge: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69813 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/northbridge: Remove unnecessary space after casts ...................................................................... src/northbridge: Remove unnecessary space after casts Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/quickpath.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_native.c 12 files changed, 60 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index cf88cfa..4febfaf 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -13,7 +13,7 @@ IO_APIC_ADDR, 0); /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1, 0xFEC20000, 24); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 30d3fed..246fe9a 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -63,7 +63,7 @@ current = start; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - dmar = (acpi_dmar_t *) current; + dmar = (acpi_dmar_t *)current; acpi_create_dmar(dmar, 0, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 0b5319b..6700e68 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -22,7 +22,7 @@ if (cpuidr.eax < 0x80000004) { strcpy(cpu_string, "Platform info not available"); } else { - u32 *p = (u32*) cpu_string; + u32 *p = (u32 *)cpu_string; for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 93cbeb9..b3f8780 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -358,7 +358,7 @@ /* Configure the RAM command. */ reg16 = pci_read_config16(NB, SDRAMC); reg16 &= 0xff1f; /* Clear bits 7-5. */ - reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ + reg16 |= (u16)(command << 5); /* Write command into bits 7-5. */ pci_write_config16(NB, SDRAMC, reg16); /* diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index fb21d35..515dc2f 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -179,8 +179,8 @@ res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); - res->base = (resource_t) 0xd0000000; - res->size = (resource_t) 0x10000000; + res->base = (resource_t)0xd0000000; + res->size = (resource_t)0x10000000; } static void gma_generate_ssdt(const struct device *device) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4935ea9..bbd4052 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -48,8 +48,8 @@ 0xff800000-0xffffffff ROM. */ resource = new_resource(dev, index++); - resource->base = (resource_t) HPET_BASE_ADDRESS; - resource->size = (resource_t) 0x00100000; + resource->base = (resource_t)HPET_BASE_ADDRESS; + resource->size = (resource_t)0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index 81621d2..56cd14b 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -98,9 +98,9 @@ (freq1_reduced - freq2_reduced)) / freq2_reduced; result->freq4_to_2_remainder = -(char)((freq1_reduced - freq2_reduced) + - ((u8) freq4 - + ((u8)freq4 - (freq1_reduced - - freq2_reduced)) % (u8) freq2_reduced); + freq2_reduced)) % (u8)freq2_reduced); } else { if (freq2_reduced > freq1_reduced) { result->freq4_to_max_remainder = @@ -275,11 +275,11 @@ + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1; u32 y = - (u8) ((vv.freq_max_reduced - vv.freq_min_reduced) + + (u8)((vv.freq_max_reduced - vv.freq_min_reduced) + vv.freq_max_reduced * multiplier) | (vv. - freqs_reversed << 8) | ((u8) (vv.freq_min_reduced * - multiplier) << 16) | ((u8) (vv. + freqs_reversed << 8) | ((u8)(vv.freq_min_reduced * + multiplier) << 16) | ((u8)(vv. freq_min_reduced * multiplier) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index e3b0b33..e1482be 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1651,7 +1651,7 @@ u32 curroffset = comp3 * 8 * 60 + 2 * comp1 + 8 * comp2; read128((total_rank << 28) | (curroffset << 3), - (u64 *) re); + (u64 *)re); failxor[0] |= get_etalon2(flip, curroffset) ^ re[0]; failxor[1] |= diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 7e29db9..151cc01 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -26,8 +26,8 @@ struct resource *resource; resource = new_resource(dev, index++); - resource->base = (resource_t) HPET_BASE_ADDRESS; - resource->size = (resource_t) 0x00100000; + resource->base = (resource_t)HPET_BASE_ADDRESS; + resource->size = (resource_t)0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 90053b4..eda3a65 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -526,7 +526,7 @@ s->pioffset = 1; } else { PRINTK_DEBUG("MCH set to unknown (%02x)\n", - (uint8_t) s->selected_timings.mem_clock & 0xff); + (uint8_t)s->selected_timings.mem_clock & 0xff); } } @@ -723,7 +723,7 @@ if (wl > 2) { flag = 1; } - reg16 = (u8) (wl - 1 - flag); + reg16 = (u8)(wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; mchbar_clrsetbits16(C0WRDATACTRL, 0x1ff, reg16); @@ -794,11 +794,11 @@ reg32 = (2 << 29) | (1 << 28) | (1 << 23); mchbar_clrsetbits32(WRWMCONFIG, 0xffb << 20, reg32); - reg8 = (u8) ((mchbar_read16(C0CYCTRKACT) & 0xe000) >> 13); - reg8 |= (u8) ((mchbar_read16(C0CYCTRKACT + 2) & 1) << 3); + reg8 = (u8)((mchbar_read16(C0CYCTRKACT) & 0xe000) >> 13); + reg8 |= (u8)((mchbar_read16(C0CYCTRKACT + 2) & 1) << 3); mchbar_clrsetbits8(BYPACTSF, 0xf << 4, reg8 << 4); - reg8 = (u8) ((mchbar_read32(C0CYCTRKRD) & 0x000f0000) >> 17); + reg8 = (u8)((mchbar_read32(C0CYCTRKRD) & 0x000f0000) >> 17); mchbar_clrsetbits8(BYPACTSF, 0xf, reg8); /* FIXME: Why not clear everything at once? */ @@ -875,12 +875,12 @@ u32 reg32; /* CTRL0 and CTRL1 */ - reg32 = ((u32) pll->dbsel[f][i]) << 20; - reg32 |= ((u32) pll->dben[f][i]) << 21; - reg32 |= ((u32) pll->dbsel[f][i]) << 22; - reg32 |= ((u32) pll->dben[f][i]) << 23; - reg32 |= ((u32) pll->clkdelay[f][i]) << 24; - reg32 |= ((u32) pll->clkdelay[f][i]) << 27; + reg32 = ((u32)pll->dbsel[f][i]) << 20; + reg32 |= ((u32)pll->dben[f][i]) << 21; + reg32 |= ((u32)pll->dbsel[f][i]) << 22; + reg32 |= ((u32)pll->dben[f][i]) << 23; + reg32 |= ((u32)pll->clkdelay[f][i]) << 24; + reg32 |= ((u32)pll->clkdelay[f][i]) << 27; mchbar_clrsetbits32(C0CTLTX2, 0x01bf0000, reg32); reg8 = pll->pi[f][i]; @@ -888,12 +888,12 @@ mchbar_clrsetbits8(C0TXCTL1DLL, 0x3f, reg8); /* CTRL2 and CTRL3 */ - reg32 = ((u32) pll->dbsel[f][i]) << 12; - reg32 |= ((u32) pll->dben[f][i]) << 13; - reg32 |= ((u32) pll->dbsel[f][i]) << 8; - reg32 |= ((u32) pll->dben[f][i]) << 9; - reg32 |= ((u32) pll->clkdelay[f][i]) << 14; - reg32 |= ((u32) pll->clkdelay[f][i]) << 10; + reg32 = ((u32)pll->dbsel[f][i]) << 12; + reg32 |= ((u32)pll->dben[f][i]) << 13; + reg32 |= ((u32)pll->dbsel[f][i]) << 8; + reg32 |= ((u32)pll->dben[f][i]) << 9; + reg32 |= ((u32)pll->clkdelay[f][i]) << 14; + reg32 |= ((u32)pll->clkdelay[f][i]) << 10; mchbar_clrsetbits32(C0CMDTX2, 0xff << 8, reg32); reg8 = pll->pi[f][i]; @@ -912,12 +912,12 @@ rank = j % 4; dqs = j / 4; - reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); - reg32 |= ((u32) pll->dbsel[f][clk]) << dqs; + reg32 |= ((u32)pll->dben[f][clk]) << (dqs + 9); + reg32 |= ((u32)pll->dbsel[f][clk]) << dqs; mchbar_clrsetbits32(C0DQSRyTX1(rank), 1 << (dqs + 9) | 1 << dqs, reg32); - reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); + reg32 = ((u32)pll->clkdelay[f][clk]) << ((dqs * 2) + 16); mchbar_clrsetbits32(C0DQSDQRyTX3(rank), 1 << (dqs * 2 + 17) | 1 << (dqs * 2 + 16), reg32); @@ -936,12 +936,12 @@ rank = j % 4; dq = j / 4; - reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); - reg32 |= ((u32) pll->dbsel[f][clk]) << dq; + reg32 |= ((u32)pll->dben[f][clk]) << (dq + 9); + reg32 |= ((u32)pll->dbsel[f][clk]) << dq; mchbar_clrsetbits32(C0DQRyTX1(rank), 1 << (dq + 9) | 1 << dq, reg32); - reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); + reg32 = ((u32)pll->clkdelay[f][clk]) << (dq*2); mchbar_clrsetbits32(C0DQSDQRyTX3(rank), 1 << (dq * 2 + 1) | 1 << (dq * 2), reg32); reg8 = pll->pi[f][clk]; @@ -1414,8 +1414,8 @@ ; reg32 = mchbar_read32(XCOMP); - rcompp = (u8) ((reg32 & ~(1 << 31)) >> 24); - rcompn = (u8) ((reg32 & ~(0xff800000)) >> 16); + rcompp = (u8)((reg32 & ~(1 << 31)) >> 24); + rcompn = (u8)((reg32 & ~(0xff800000)) >> 16); FOR_EACH_RCOMP_GROUP(i) { srup = (mchbar_read8(C0RCOMPCTRLx(i) + 1) & 0xc0) >> 6; @@ -2134,7 +2134,7 @@ FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { nranks++; - dra = (u8) ((mchbar_read32(C0DRA01) >> (8 * r)) & 0x7f); + dra = (u8)((mchbar_read32(C0DRA01) >> (8 * r)) & 0x7f); curranksize = drbtab[dra]; if (maxranksize == 0) { maxranksize = curranksize; diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9ef491b..4e95815 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -693,9 +693,9 @@ /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { - mch_cas = (u16) ((ctrl->CAS - 4) << 1); + mch_cas = (u16)((ctrl->CAS - 4) << 1); } else { - mch_cas = (u16) (ctrl->CAS - 12); + mch_cas = (u16)(ctrl->CAS - 12); mch_cas = ((mch_cas << 1) | 0x1); } @@ -1732,7 +1732,7 @@ FOR_ALL_LANES { u64 res = mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); - res |= ((u64) mchbar_read32(lane_base[lane] + + res |= ((u64)mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 7141116..a46390c 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -555,7 +555,7 @@ * Exit early to prevent a system hang. */ reg1 = mchbar_read32(MC_BIOS_DATA); - val2 = (u8) reg1; + val2 = (u8)reg1; if (val2) return; @@ -577,7 +577,7 @@ /* Step 3 - Verify lock frequency */ reg1 = mchbar_read32(MC_BIOS_DATA); - val2 = (u8) reg1; + val2 = (u8)reg1; if (val2 >= ctrl->FRQ) { printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", (1000 << 8) / ctrl->tCK); -- To view, visit https://review.coreboot.org/c/coreboot/+/69813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Gerrit-Change-Number: 69813 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/soc/samsung: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69812 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/soc/samsung: Remove unnecessary space after casts ...................................................................... src/soc/samsung: Remove unnecessary space after casts Change-Id: I32b41eded11e4e575627fec3947a75c08fdfd0a6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69812 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/samsung/exynos5420/fimd.c 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 53c9fe4..bf236d3 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -182,7 +182,7 @@ cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED); - src_clock = (unsigned long long) get_lcd_clk(); + src_clock = (unsigned long long)get_lcd_clk(); /* get quotient and remainder. */ remainder = src_clock % pixel_clock; -- To view, visit https://review.coreboot.org/c/coreboot/+/69812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b41eded11e4e575627fec3947a75c08fdfd0a6 Gerrit-Change-Number: 69812 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src/soc/cavium: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69811 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/soc/cavium: Remove unnecessary space after casts ...................................................................... src/soc/cavium: Remove unnecessary space after casts Change-Id: Ieb094096e9e204e59a1f3fcf716d906e7736fb43 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69811 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/cavium/cn81xx/twsi.c 1 file changed, 15 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c index b1c1e66..f06989b 100644 --- a/src/soc/cavium/cn81xx/twsi.c +++ b/src/soc/cavium/cn81xx/twsi.c @@ -497,7 +497,7 @@ twsi_sw.u = 0; twsi_sw.s.op = TWSI_SW_EOP_IA; twsi_sw.s.eop_ia = TWSI_DATA; - twsi_sw.s.data = (u32) (slave_addr << 1) | TWSI_OP_WRITE; + twsi_sw.s.data = (u32)(slave_addr << 1) | TWSI_OP_WRITE; twsi_write_sw(baseaddr, twsi_sw); twsi_write_ctl(baseaddr, TWSI_CTL_ENAB); @@ -574,7 +574,7 @@ twsi_sw.s.op = TWSI_SW_EOP_IA; twsi_sw.s.eop_ia = TWSI_DATA; - twsi_sw.s.data = (u32) (slave_addr << 1) | TWSI_OP_READ; + twsi_sw.s.data = (u32)(slave_addr << 1) | TWSI_OP_READ; twsi_write_sw(baseaddr, twsi_sw); twsi_write_ctl(baseaddr, TWSI_CTL_ENAB); -- To view, visit https://review.coreboot.org/c/coreboot/+/69811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb094096e9e204e59a1f3fcf716d906e7736fb43 Gerrit-Change-Number: 69811 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src/soc/nvidia: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69810 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/soc/nvidia: Remove unnecessary space after casts ...................................................................... src/soc/nvidia: Remove unnecessary space after casts Change-Id: I096e88158027ac22cf93a9450c869807dbc14670 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69810 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/sor.c M src/soc/nvidia/tegra210/spi.c 5 files changed, 22 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 5da2c06..de98d65 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -28,7 +28,7 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -36,7 +36,7 @@ static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, u32 reg, u32 val) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 3d2750f..8246a09 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -42,7 +42,7 @@ static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -50,7 +50,7 @@ static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, u32 val) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index f3bc208..f6f955c 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -36,7 +36,7 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -44,7 +44,7 @@ static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, u32 reg, u32 val) { - void *addr = dp->aux_base + (u32) (reg << 2); + void *addr = dp->aux_base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 91ea5f4..c24e0d6 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -44,7 +44,7 @@ static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); u32 reg_val = READL(addr); return reg_val; } @@ -52,7 +52,7 @@ static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, u32 val) { - void *addr = sor->base + (u32) (reg << 2); + void *addr = sor->base + (u32)(reg << 2); WRITEL(val, addr); } diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index f8db110..0f38df2 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -478,7 +478,7 @@ dcache_clean_by_mva(spi->out_buf, bytes); write32(&spi->dma_out->regs->apb_ptr, - (uintptr_t) & spi->regs->tx_fifo); + (uintptr_t)&spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); -- To view, visit https://review.coreboot.org/c/coreboot/+/69810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I096e88158027ac22cf93a9450c869807dbc14670 Gerrit-Change-Number: 69810 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src/soc/mediatek: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69809 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/soc/mediatek: Remove unnecessary space after casts ...................................................................... src/soc/mediatek: Remove unnecessary space after casts Change-Id: I871579cc434820294f285298fe43da4cd1da27a3 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69809 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/spm.c 2 files changed, 20 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index ec39049..c772885 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -985,14 +985,14 @@ u16 debug_cnt_perbyte, current_pass = 0, pass_byte_cnt = 0; for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { - u8 dqs_result_r = (u8) ((result_r >> (8 * dqs)) & 0xff); - u8 dqs_result_f = (u8) ((result_f >> (8 * dqs)) & 0xff); + u8 dqs_result_r = (u8)((result_r >> (8 * dqs)) & 0xff); + u8 dqs_result_f = (u8)((result_f >> (8 * dqs)) & 0xff); if (pass_byte_cnt & (1 << dqs)) continue; current_pass = 0; - debug_cnt_perbyte = (u16) debug_cnt[dqs]; + debug_cnt_perbyte = (u16)debug_cnt[dqs]; if (dqs_result_r == 0 && dqs_result_f == 0 && debug_cnt_perbyte == GATING_GOLDEND_DQSCNT) current_pass = 1; @@ -2135,7 +2135,7 @@ dramc_dbg("%d ", dly); for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; + bool bit_fail = (err_value & ((u32)1 << bit)) != 0; /* pass window bigger than 7, * consider as real pass window. @@ -2401,7 +2401,7 @@ SET32_BITFIELDS(&ch[chn].ao.padctrl, PADCTRL_DQIENQKEND, 1, PADCTRL_DQIENLATEBEGIN, 1); - return (u8) best_step; + return (u8)best_step; } static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 freq_group, u8 datlat0, u8 datlat1) diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 5fba84d..83e814f 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -156,7 +156,7 @@ write32(&mtk_spm->pcm_im_host_rw_ptr, PCM_IM_HOST_EN_LSB | PCM_IM_HOST_W_EN_LSB | i); write32(&mtk_spm->pcm_im_host_rw_dat, - (u32) *(pcm->buf + i)); + (u32)*(pcm->buf + i)); } write32(&mtk_spm->pcm_im_host_rw_ptr, 0); } @@ -168,7 +168,7 @@ for (i = 0; i < pcm->desc.size; i++) { write32(&mtk_spm->pcm_im_host_rw_ptr, PCM_IM_HOST_EN_LSB | i); if ((read32(&mtk_spm->pcm_im_host_rw_dat)) != - (u32) *(pcm->buf + i)) + (u32)*(pcm->buf + i)) spm_load_pcm_code(pcm); } write32(&mtk_spm->pcm_im_host_rw_ptr, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/69809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I871579cc434820294f285298fe43da4cd1da27a3 Gerrit-Change-Number: 69809 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/soc/ti: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69808 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/soc/ti: Remove unnecessary space after casts ...................................................................... src/soc/ti: Remove unnecessary space after casts Change-Id: If4564abf060410726b0b245ba002a35ca9d30769 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69808 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/ti/am335x/uart.c 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index b19ba96..0543475 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -149,7 +149,7 @@ void uart_init(unsigned int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); - uint16_t div = (uint16_t) uart_baudrate_divisor( + uint16_t div = (uint16_t)uart_baudrate_divisor( get_uart_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4564abf060410726b0b245ba002a35ca9d30769 Gerrit-Change-Number: 69808 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: src/southbridge: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69805 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/southbridge: Remove unnecessary space after casts ...................................................................... src/southbridge: Remove unnecessary space after casts Change-Id: Ib82968724696110a8d1655928db5b2a665525d20 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69805 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/ibexpeak/setup_heci_uma.c 6 files changed, 33 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 49c137a..9daf497 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -76,7 +76,7 @@ /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void)RCBA16(OIC); } void southbridge_rcba_config(void) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index e243c97..9dc58fd 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -142,8 +142,8 @@ write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); reg32 &= ~0x00000002; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 44d283c..1d274e8 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -158,7 +158,7 @@ u8 v = read8(addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); + v, ((unsigned int)addr & 0xffff) - 0xf020); return v; } @@ -167,7 +167,7 @@ u16 v = read16(addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); + v, ((unsigned int)addr & 0xffff) - 0xf020); return v; } @@ -176,7 +176,7 @@ u32 v = read32(addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); + v, ((unsigned int)addr & 0xffff) - 0xf020); return v; } @@ -184,21 +184,21 @@ { write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); + b, ((unsigned int)addr & 0xffff) - 0xf020); } static void writew_(u16 b, void *addr) { write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); + b, ((unsigned int)addr & 0xffff) - 0xf020); } static void writel_(u32 b, void *addr) { write32(addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); + b, ((unsigned int)addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ @@ -787,8 +787,8 @@ if (addr + len > flash->size) { printk(BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", - (unsigned int) addr, - (unsigned int) addr+(unsigned int) len); + (unsigned int)addr, + (unsigned int)addr+(unsigned int) len); return -1; } @@ -835,7 +835,7 @@ if ((i % 4) == 0) temp32 = 0; - temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + temp32 |= ((uint32_t)data[i]) << ((i % 4) * 8); if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ writel_(temp32, cntlr.data + (i - (i % 4))); @@ -856,7 +856,7 @@ if (addr + len > flash->size) { printk(BIOS_ERR, "Attempt to write 0x%x-0x%x which is out of chip\n", - (unsigned int)addr, (unsigned int) (addr+len)); + (unsigned int)addr, (unsigned int)(addr+len)); return -1; } @@ -890,7 +890,7 @@ len -= block_len; } printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", - (unsigned int) (addr - start), start); + (unsigned int)(addr - start), start); return 0; } diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 260d76a..7621a4d 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -46,8 +46,8 @@ /* PI (Ports implemented) */ write32(abar + 0x0c, port_map); /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ /* VSP (Vendor Specific Register) */ reg32 = read32(abar + 0xa0); diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 4e01481..1694d3c 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -45,8 +45,8 @@ /* PI (Ports implemented) */ write32(abar + 0x0c, port_map); /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x0c); /* Read back 1 */ + (void)read32(abar + 0x0c); /* Read back 2 */ /* VSP (Vendor Specific Register) */ reg32 = read32(abar + 0xa0); diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c index e490573..572e5e7 100644 --- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c +++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c @@ -97,7 +97,7 @@ csr.raw = read32(DEFAULT_HECIBAR + 0xc); } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); - *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); + *(u32 *)head = read32(DEFAULT_HECIBAR + 0x8); if (!head->length) { write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); *packet_size = 0; @@ -188,7 +188,7 @@ }; u32 reply_size; - send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); + send_heci_message((u8 *)&msg, sizeof(msg), 0, 7); reply_size = sizeof(reply); if (recv_heci_message(&reply, &reply_size) == -1) -- To view, visit https://review.coreboot.org/c/coreboot/+/69805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82968724696110a8d1655928db5b2a665525d20 Gerrit-Change-Number: 69805 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/device/pci_: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69804 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/device/pci_: Remove unnecessary space after casts ...................................................................... src/device/pci_: Remove unnecessary space after casts Change-Id: I11593245fedc26489e3506d773aaff1ad34188b1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69804 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/pci_device.c M src/device/pci_rom.c 2 files changed, 28 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 8651586..9de2946 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -108,7 +108,7 @@ PCI_BASE_ADDRESS_MEM_LIMIT_64)) { /* Find the high bits that move. */ moving |= - ((resource_t) pci_moving_config32(dev, index + 4)) << 32; + ((resource_t)pci_moving_config32(dev, index + 4)) << 32; } /* Find the resource constraints. @@ -496,13 +496,13 @@ resource_t moving_base, moving_limit, moving; /* See if the bridge I/O resources are implemented. */ - moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8; + moving_base = ((u32)pci_moving_config8(dev, PCI_IO_BASE)) << 8; moving_base |= - ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; + ((u32)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; - moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; + moving_limit = ((u32)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; moving_limit |= - ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; + ((u32)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; moving = moving_base & moving_limit; @@ -511,14 +511,14 @@ /* See if the bridge prefmem resources are implemented. */ moving_base = - ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; + ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; moving_base |= - ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32; + ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32; moving_limit = - ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; + ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; moving_limit |= - ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; + ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; moving = moving_base & moving_limit; /* Initialize the prefetchable memory constraints on the current bus. */ @@ -526,8 +526,8 @@ IORESOURCE_MEM | IORESOURCE_PREFETCH); /* See if the bridge mem resources are implemented. */ - moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; - moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; + moving_base = ((u32)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; + moving_limit = ((u32)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; moving = moving_base & moving_limit; diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index b8dafd1..8480626 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -159,10 +159,10 @@ do { /* Get next image. */ - rom_header = (struct rom_header *)((void *) rom_header + rom_header = (struct rom_header *)((void *)rom_header + image_size); - rom_data = (struct pci_data *)((void *) rom_header + rom_data = (struct pci_data *)((void *)rom_header + le32_to_cpu(rom_header->data)); image_size = le32_to_cpu(rom_data->ilen) * 512; @@ -190,7 +190,7 @@ memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); } - return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); + return (struct rom_header *)(PCI_VGA_RAM_IMAGE_START); } printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x bytes\n", @@ -198,7 +198,7 @@ memcpy(pci_ram_image_start, rom_header, rom_size); pci_ram_image_start += rom_size; - return (struct rom_header *) (pci_ram_image_start-rom_size); + return (struct rom_header *)(pci_ram_image_start-rom_size); } /* ACPI */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11593245fedc26489e3506d773aaff1ad34188b1 Gerrit-Change-Number: 69804 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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