coreboot-gerrit November 2022

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[L] Change in coreboot[master]: security/tpm: resolve conflicts in TSS implementations
by Sergii Dmytruk (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Michał Żygowski, Frans Hendriks, Matt DeVillier, Christian Walter, Julius Werner, Krystian Hebel, Fred Reitberger, Sergii Dmytruk, Felix Held. Hello build bot (Jenkins), Raul Rangel, Frans Hendriks, Matt DeVillier, Julius Werner, Krystian Hebel, Erik van den Bogaert, Jason Glenesk, Michał Żygowski, Christian Walter, Fred Reitberger, Yu-Ping Wu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69160 to look at the new patch set (#9). Change subject: security/tpm: resolve conflicts in TSS implementations ...................................................................... security/tpm: resolve conflicts in TSS implementations No functional changes. Just code updates to don't have any compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled in. One might want to support both TPM families for example if TPM is pluggable, in which case currently one has to update both TPM device and firmware. Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/security/tpm/Makefile.inc M src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c A src/security/tpm/tss/tss.c M src/security/tpm/tss/vendor/cr50/cr50.c A src/security/tpm/tss1.h A src/security/tpm/tss2.h M src/security/vboot/secdata_tpm.c M src/soc/amd/common/psp_verstage/psp_verstage.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/google/chromeos/tpm2.c 15 files changed, 413 insertions(+), 279 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69160/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/69160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Gerrit-Change-Number: 69160 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: security/tpm: make tis_probe() return tpm_family
by Sergii Dmytruk (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Christian Walter, Julius Werner, Krystian Hebel, Sergii Dmytruk. Hello build bot (Jenkins), Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69159 to look at the new patch set (#6). Change subject: security/tpm: make tis_probe() return tpm_family ...................................................................... security/tpm: make tis_probe() return tpm_family Via an out parameter. This is needed to be able to dynamically pick TSS implementation based on the information discovered on probing. Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/tpm/tpm.h M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/tis.c M src/security/tpm/tis.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c 11 files changed, 79 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/69159/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Gerrit-Change-Number: 69159 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: drivers/pc80/tpm: probe for TPM family of a device
by Sergii Dmytruk (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Christian Walter, Julius Werner, Krystian Hebel, Sergii Dmytruk. Hello build bot (Jenkins), Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69023 to look at the new patch set (#6). Change subject: drivers/pc80/tpm: probe for TPM family of a device ...................................................................... drivers/pc80/tpm: probe for TPM family of a device At the moment this is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Later this TPM family will be returned to the caller. Change-Id: I5464771836c66bcc441efb7189ded416b8f53827 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 93 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/69023/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5464771836c66bcc441efb7189ded416b8f53827 Gerrit-Change-Number: 69023 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: /: Remove unnecessary space in log messages
by Elyes Haouas (Code Review) 22 Nov '22

22 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69903 ) Change subject: /: Remove unnecessary space in log messages ...................................................................... /: Remove unnecessary space in log messages Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/pirq_routing.c M src/drivers/intel/gma/intel_ddi.c M src/lib/selfboot.c M src/security/vboot/secdata_tpm.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pcie.c 10 files changed, 21 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/69903/1 diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 0da057f..0a1e75d 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -164,7 +164,7 @@ } for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) - printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); + printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 24bc162..6c6d13e 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -48,7 +48,7 @@ hsw_ddi_translations_fdi : hsw_ddi_translations_dp); - printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n", + printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n", port, use_fdi_mode ? "FDI" : "DP"); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 637ad13..e21c493 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -93,7 +93,7 @@ break; } default: - printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression); + printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression); return 0; } /* Calculate middle after any changes to len. */ diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 7885069..844b28d 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -15,7 +15,7 @@ #include <console/console.h> #define VBDEBUG(format, args...) \ - printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) + printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) #define RETURN_ON_FAILURE(tpm_cmd) do { \ uint32_t result_; \ diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index b37f256..61d6962 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -295,7 +295,7 @@ if (dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* 8.2 Configuration of PCI Express Root Ports */ pci_or_config32(dev, 0x338, 1 << 26); diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 0cd6483..2d33873 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -229,7 +229,7 @@ CH2_PD | CH3_PD); break; default: - printk(BIOS_ERR, "DP undefined block number : %d\n", block); + printk(BIOS_ERR, "DP undefined block number : %d\n", block); return -1; } diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index d24604c..16ffaf5 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -327,7 +327,7 @@ } if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* * PCIE Power Savings for PantherPoint and CougarPoint/B1+ @@ -408,7 +408,7 @@ return pch_pcie_enable(dev); if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(dev, PCI_COMMAND, diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 6d4e7115..4783099 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -56,7 +56,7 @@ u16 reg16; if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 8f7cdb8..f83f3f6 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -185,7 +185,7 @@ return; if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(dev, PCI_COMMAND, diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 24fab3b..2f01560 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -322,7 +322,7 @@ if (dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(dev, PCI_COMMAND, -- To view, visit https://review.coreboot.org/c/coreboot/+/69903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Gerrit-Change-Number: 69903 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: commonlib/bsd: Add zstd support
by build bot (Jenkins) (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Martin L Roth, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69893 ) Change subject: commonlib/bsd: Add zstd support ...................................................................... Patch Set 1: (1 comment) File src/commonlib/bsd/zstd_wrapper.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164274): https://review.coreboot.org/c/coreboot/+/69893/comment/b64040a4_bce8730f PS1, Line 27: printk(BIOS_ERR, "Bogus free called\n"); Prefer using '"%s...", __func__' to using 'free', this function's name, in a string -- To view, visit https://review.coreboot.org/c/coreboot/+/69893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1b1f53327c598d07bd83d4391e8012d41696a16 Gerrit-Change-Number: 69893 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Nov 2022 15:52:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Add option to compress FSP with ZSTD
by Arthur Heymans (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Andrey Petrov. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69894 ) Change subject: drivers/intel/fsp2_0: Add option to compress FSP with ZSTD ...................................................................... drivers/intel/fsp2_0: Add option to compress FSP with ZSTD Currently no platform uses this. Change-Id: Ia13f027205b2f4eea5574dfea455eefa854cfe66 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc 2 files changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/69894/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8c36063..59f7348 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -217,6 +217,9 @@ config FSP_COMPRESS_FSP_S_LZMA bool +config FSP_COMPRESS_FSP_S_ZSTD + bool + config FSP_COMPRESS_FSP_S_LZ4 bool @@ -224,6 +227,10 @@ bool depends on !FSP_M_XIP +config FSP_COMPRESS_FSP_M_ZSTD + bool + depends on !FSP_M_XIP + config FSP_COMPRESS_FSP_M_LZ4 bool depends on !FSP_M_XIP diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index f5641ac..64f3db4 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -64,8 +64,9 @@ endif ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZMA),y) $(FSP_M_CBFS)-compression := LZMA -endif -ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y) +else ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_ZSTD),y) +$(FSP_M_CBFS)-compression := ZSTD +else ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y) $(FSP_M_CBFS)-compression := LZ4 endif ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),) @@ -77,8 +78,9 @@ $(FSP_S_CBFS)-type := fsp ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZMA),y) $(FSP_S_CBFS)-compression := LZMA -endif -ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) +else ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_ZSTD),y) +$(FSP_S_CBFS)-compression := ZSTD +else ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) $(FSP_S_CBFS)-compression := LZ4 endif ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),) -- To view, visit https://review.coreboot.org/c/coreboot/+/69894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia13f027205b2f4eea5574dfea455eefa854cfe66 Gerrit-Change-Number: 69894 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: commonlib/bsd: Add zstd support
by Arthur Heymans (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Martin L Roth, Julius Werner. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69893 ) Change subject: commonlib/bsd: Add zstd support ...................................................................... commonlib/bsd: Add zstd support This adds the option to compress ramstage and payloads with ZSTD. Change-Id: Ic1b1f53327c598d07bd83d4391e8012d41696a16 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/Kconfig M src/Kconfig M src/commonlib/Makefile.inc A src/commonlib/bsd/zstd/Makefile.inc A src/commonlib/bsd/zstd_wrapper.c M src/commonlib/include/commonlib/timestamp_serialized.h M src/lib/Makefile.inc M src/lib/cbfs.c M src/lib/selfboot.c 10 files changed, 150 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69893/1 diff --git a/Makefile.inc b/Makefile.inc index 563a2bc..5bc1cec 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -386,16 +386,19 @@ ####################################################################### # a variety of flags for our build CBFS_COMPRESS_FLAG:=none -ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y) +ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA),y) CBFS_COMPRESS_FLAG:=LZMA +else ifeq ($(CONFIG_COMPRESS_RAMSTAGE_ZSTD),y) +CBFS_COMPRESS_FLAG:=ZSTD endif CBFS_PAYLOAD_COMPRESS_FLAG:=none ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) CBFS_PAYLOAD_COMPRESS_FLAG:=LZMA -endif -ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZ4),y) +else ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZ4),y) CBFS_PAYLOAD_COMPRESS_FLAG:=LZ4 +else ifeq ($(CONFIG_COMPRESSED_PAYLOAD_ZSTD),y) +CBFS_PAYLOAD_COMPRESS_FLAG:=ZSTD endif CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG:=none diff --git a/payloads/Kconfig b/payloads/Kconfig index 2a2773a..a8381ab 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -72,6 +72,12 @@ In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. +config COMPRESSED_PAYLOAD_ZSTD + bool "Use ZSTD compression for payloads" + help + In order to reduce the size payloads take up in the ROM chip + coreboot can compress them using the ZSTD algorithm. + config COMPRESSED_PAYLOAD_LZ4 bool "Use LZ4 compression for payloads" help diff --git a/src/Kconfig b/src/Kconfig index f30a1bb..671df2a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -170,13 +170,32 @@ every boot. Use this if you want the NVRAM configuration to never be modified from its default values. -config COMPRESS_RAMSTAGE - bool "Compress ramstage with LZMA" +choice COMPRESS_RAMSTAGE + bool "Ramstage compression" depends on HAVE_RAMSTAGE + default COMPRESS_RAMSTAGE_LZMA # Default value set at the end of the file help Compress ramstage to save memory in the flash image. +config COMPRESS_RAMSTAGE_NONE + bool "none" + help + Don't compress ramstage + +config COMPRESS_RAMSTAGE_LZMA + bool "LZMA" + help + Compress ramstage with LZMA. + +config COMPRESS_RAMSTAGE_ZSTD + bool "ZSTD" + help + Compress ramstage with ZSTD. + This is faster than LZMA but uses more stack. + +endchoice + config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES @@ -660,7 +679,7 @@ config STACK_SIZE hex - default 0x2000 if ARCH_X86 + default 0x20000 if ARCH_X86 default 0x0 config MAX_CPUS diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index e90ed4f..cb19fd0 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -51,8 +51,12 @@ ramstage-y += bsd/lz4_wrapper.c postcar-y += bsd/lz4_wrapper.c +all-y += bsd/zstd_wrapper.c + ramstage-y += sort.c romstage-y += bsd/elog.c ramstage-y += bsd/elog.c smm-y += bsd/elog.c + +subdirs-y += bsd/zstd diff --git a/src/commonlib/bsd/zstd/Makefile.inc b/src/commonlib/bsd/zstd/Makefile.inc new file mode 100644 index 0000000..ceb330a --- /dev/null +++ b/src/commonlib/bsd/zstd/Makefile.inc @@ -0,0 +1,18 @@ +all-y += decompress/huf_decompress.c +all-y += decompress/zstd_ddict.c +all-y += decompress/zstd_decompress_block.c +all-y += decompress/zstd_decompress.c + +all-y += common/debug.c +all-y += common/entropy_common.c +all-y += common/error_private.c +all-y += common/fse_decompress.c +all-y += common/pool.c +all-y += common/threading.c +all-y += common/xxhash_zstd.c # this is renamed to avoid namespace conflicts with lz4 code +all-y += common/zstd_common.c + +subdirs-y += bsd/zstd +CPPFLAGS_common += -I$(src)/commonlib/bsd/zstd -I$(src)/commonlib/bsd/zstd/common +CPPFLAGS_common += -I$(src)/commonlib/bsd/zstd/decompress +CPPFLAGS_common += -DXXH_NAMESPACE=ZSTD_ -DZSTD_DISABLE_ASM=1 -DZSTD_HEAPMODE=0 diff --git a/src/commonlib/bsd/zstd_wrapper.c b/src/commonlib/bsd/zstd_wrapper.c new file mode 100644 index 0000000..4f3d68c1 --- /dev/null +++ b/src/commonlib/bsd/zstd_wrapper.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ + +#include <assert.h> +#include <commonlib/bsd/compression.h> +#include <stdint.h> +#include <stddef.h> +#define ZSTD_STATIC_LINKING_ONLY 1 +#include <zstd.h> + +size_t uzstdfn(const void *src, size_t srcn, void *dst, size_t dstn) +{ + static char buffer[95792] __aligned(8); + ASSERT(sizeof(buffer) <= ZSTD_estimateDCtxSize()); + ZSTD_DCtx *dctx = ZSTD_initStaticDCtx(buffer, sizeof(buffer)); + if (!dctx) + return 0; + return ZSTD_decompressDCtx(dctx, dst, dstn, src, srcn); +} + +#if !ENV_HAS_HEAP_SECTION +#include <stdlib.h> +#include <console/console.h> + +/* Fix some linking issues. This should never be called. */ +void free(void *) +{ + printk(BIOS_ERR, "Bogus free called\n"); +} +#endif diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 4b1001e..074b793 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -37,6 +37,8 @@ TS_ULZMA_END = 16, TS_ULZ4F_START = 17, TS_ULZ4F_END = 18, + TS_UZSTDF_START = 19, + TS_UZSTDF_END = 20, TS_DEVICE_ENUMERATE = 30, TS_DEVICE_CONFIGURE = 40, TS_DEVICE_ENABLE = 50, @@ -211,6 +213,8 @@ TS_NAME_DEF(TS_ULZMA_END, 0, "finished LZMA decompress (ignore for x86)"), TS_NAME_DEF(TS_ULZ4F_START, TS_ULZ4F_END, "starting LZ4 decompress (ignore for x86)"), TS_NAME_DEF(TS_ULZ4F_END, 0, "finished LZ4 decompress (ignore for x86)"), + TS_NAME_DEF(TS_UZSTDF_START, TS_ULZ4F_END, "starting ZSTD decompress (ignore for x86)"), + TS_NAME_DEF(TS_UZSTDF_END, 0, "finished ZSTD decompress (ignore for x86)"), TS_NAME_DEF(TS_DEVICE_ENUMERATE, TS_DEVICE_CONFIGURE, "device enumeration"), TS_NAME_DEF(TS_DEVICE_CONFIGURE, TS_DEVICE_ENABLE, "device configuration"), TS_NAME_DEF(TS_DEVICE_ENABLE, TS_DEVICE_INITIALIZE, "device enable"), diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1c7bc22..c266797 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -95,7 +95,7 @@ romstage-y += fmap.c romstage-y += delay.c romstage-y += cbfs.c -romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +romstage-$(CONFIG_COMPRESS_RAMSTAGE_LZMA) += lzma.c lzmadecode.c romstage-y += libgcc.c romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c @@ -294,7 +294,7 @@ postcar-y += gcc.c postcar-y += halt.c postcar-y += libgcc.c -postcar-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +postcar-$(CONFIG_COMPRESS_RAMSTAGE_LZMA) += lzma.c lzmadecode.c postcar-y += memchr.c postcar-y += memcmp.c postcar-y += prog_loaders.c diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index d2829d1..0f44468 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -142,7 +142,25 @@ return false; if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) return false; - if ((ENV_ROMSTAGE || ENV_POSTCAR) && !CONFIG(COMPRESS_RAMSTAGE)) + if ((ENV_ROMSTAGE || ENV_POSTCAR) && !CONFIG(COMPRESS_RAMSTAGE_LZMA)) + return false; + if (ENV_SMM) + return false; + return true; +} + +static inline bool cbfs_zstd_enabled(void) +{ + if (fsps_env() && CONFIG(FSP_COMPRESS_FSP_S_ZSTD)) + return true; + if (fspm_env() && CONFIG(FSP_COMPRESS_FSP_M_ZSTD)) + return true; + /* We assume here romstage and postcar are never compressed. */ + if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) + return false; + if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) + return false; + if ((ENV_ROMSTAGE || ENV_POSTCAR) && !CONFIG(COMPRESS_RAMSTAGE_ZSTD)) return false; if (ENV_SMM) return false; @@ -255,6 +273,24 @@ rdev_munmap(rdev, map); return out_size; + case CBFS_COMPRESS_ZSTD: + if (!cbfs_zstd_enabled()) + return 0; + + map = rdev_mmap_full(rdev); + if (map == NULL) + return 0; + + if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) { + /* Note: timestamp not useful for memory-mapped media (x86) */ + timestamp_add_now(TS_UZSTDF_START); + out_size = uzstdfn(map, in_size, buffer, buffer_size); + timestamp_add_now(TS_UZSTDF_END); + } + + rdev_munmap(rdev, map); + + return out_size; default: return 0; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 637ad13..a921c02 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -87,6 +87,16 @@ return 0; break; } + case CBFS_COMPRESS_ZSTD: { + printk(BIOS_DEBUG, "using ZSTD\n"); + timestamp_add_now(TS_UZSTDF_START); + len = uzstdfn(src, len, dest, memsz); + timestamp_add_now(TS_UZSTDF_END); + if (!len) /* Decompression Error. */ + return 0; + break; + } + case CBFS_COMPRESS_NONE: { printk(BIOS_DEBUG, "it's not compressed!\n"); memcpy(dest, src, len); -- To view, visit https://review.coreboot.org/c/coreboot/+/69893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1b1f53327c598d07bd83d4391e8012d41696a16 Gerrit-Change-Number: 69893 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[master]: util/cbfstool: Add zstd support
by Arthur Heymans (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Shelley Chen, Martin L Roth, Arthur Heymans. Hello Shelley Chen, build bot (Jenkins), Martin L Roth, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69753 to look at the new patch set (#2). Change subject: util/cbfstool: Add zstd support ...................................................................... util/cbfstool: Add zstd support This adds zstd support to cbfstool. The code is taken from zstd-1.5.2 and one minor modifications: renaming xxhash.c to xxhash_zstd.c to avoid namespace conflicts with lz4. ZSTD offers similar compression ratios to LZMA, but a vastly fast decompress speed. Typically ZSTD results in slightly larger binaries than LZMA. Whether ZSTD should then be preferred over LZMA depends on a few things: - Caching: When loading from memory mapped boot devices, ZSTD will read the boot medium multiple times, while LZMA will not. If the memory mapped boot medium is not cached ZSTD results in much slower decompression. - Boot medium speed: Often, but not always LZMA results in smaller binaries. If the boot medium is the bottleneck, than loading smaller binaries might actually be faster. On a fast boot medium (high spi freq, using quad/dual io), the performance benefits from ZSTD might be more substantial - ZSTD decompression code has a much larger footprint than LZMA. If the stage (postcar) is loaded in uncached memory the size increase might slow things down. - ZSTD uses a lot of .bss (CTX is 95792 bytes large). This might not be available in some environments. Change-Id: I34508268f8767008ef25cb9e466d201345881232 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h M src/commonlib/bsd/include/commonlib/bsd/compression.h A src/commonlib/bsd/zstd/common/bitstream.h A src/commonlib/bsd/zstd/common/compiler.h A src/commonlib/bsd/zstd/common/cpu.h A src/commonlib/bsd/zstd/common/debug.c A src/commonlib/bsd/zstd/common/debug.h A src/commonlib/bsd/zstd/common/entropy_common.c A src/commonlib/bsd/zstd/common/error_private.c A src/commonlib/bsd/zstd/common/error_private.h A src/commonlib/bsd/zstd/common/fse.h A src/commonlib/bsd/zstd/common/fse_decompress.c A src/commonlib/bsd/zstd/common/huf.h A src/commonlib/bsd/zstd/common/mem.h A src/commonlib/bsd/zstd/common/pool.c A src/commonlib/bsd/zstd/common/pool.h A src/commonlib/bsd/zstd/common/portability_macros.h A src/commonlib/bsd/zstd/common/threading.c A src/commonlib/bsd/zstd/common/threading.h A src/commonlib/bsd/zstd/common/xxhash.h A src/commonlib/bsd/zstd/common/xxhash_zstd.c A src/commonlib/bsd/zstd/common/zstd_common.c A src/commonlib/bsd/zstd/common/zstd_deps.h A src/commonlib/bsd/zstd/common/zstd_internal.h A src/commonlib/bsd/zstd/common/zstd_trace.h A src/commonlib/bsd/zstd/decompress/huf_decompress.c A src/commonlib/bsd/zstd/decompress/huf_decompress_amd64.S A src/commonlib/bsd/zstd/decompress/zstd_ddict.c A src/commonlib/bsd/zstd/decompress/zstd_ddict.h A src/commonlib/bsd/zstd/decompress/zstd_decompress.c A src/commonlib/bsd/zstd/decompress/zstd_decompress_block.c A src/commonlib/bsd/zstd/decompress/zstd_decompress_block.h A src/commonlib/bsd/zstd/decompress/zstd_decompress_internal.h A src/commonlib/bsd/zstd/zdict.h A src/commonlib/bsd/zstd/zstd.h A src/commonlib/bsd/zstd/zstd_errors.h M util/cbfstool/Makefile.inc M util/cbfstool/cbfs.h M util/cbfstool/compress.c A util/cbfstool/zstd/common/bitstream.h A util/cbfstool/zstd/common/compiler.h A util/cbfstool/zstd/common/cpu.h A util/cbfstool/zstd/common/debug.h A util/cbfstool/zstd/common/error_private.h A util/cbfstool/zstd/common/fse.h A util/cbfstool/zstd/common/huf.h A util/cbfstool/zstd/common/mem.h A util/cbfstool/zstd/common/pool.h A util/cbfstool/zstd/common/portability_macros.h A util/cbfstool/zstd/common/threading.h A util/cbfstool/zstd/common/xxhash.h A util/cbfstool/zstd/common/zstd_deps.h A util/cbfstool/zstd/common/zstd_internal.h A util/cbfstool/zstd/common/zstd_trace.h A util/cbfstool/zstd/compress/clevels.h A util/cbfstool/zstd/compress/fse_compress.c A util/cbfstool/zstd/compress/hist.c A util/cbfstool/zstd/compress/hist.h A util/cbfstool/zstd/compress/huf_compress.c A util/cbfstool/zstd/compress/zstd_compress.c A util/cbfstool/zstd/compress/zstd_compress_internal.h A util/cbfstool/zstd/compress/zstd_compress_literals.c A util/cbfstool/zstd/compress/zstd_compress_literals.h A util/cbfstool/zstd/compress/zstd_compress_sequences.c A util/cbfstool/zstd/compress/zstd_compress_sequences.h A util/cbfstool/zstd/compress/zstd_compress_superblock.c A util/cbfstool/zstd/compress/zstd_compress_superblock.h A util/cbfstool/zstd/compress/zstd_cwksp.h A util/cbfstool/zstd/compress/zstd_double_fast.c A util/cbfstool/zstd/compress/zstd_double_fast.h A util/cbfstool/zstd/compress/zstd_fast.c A util/cbfstool/zstd/compress/zstd_fast.h A util/cbfstool/zstd/compress/zstd_lazy.c A util/cbfstool/zstd/compress/zstd_lazy.h A util/cbfstool/zstd/compress/zstd_ldm.c A util/cbfstool/zstd/compress/zstd_ldm.h A util/cbfstool/zstd/compress/zstd_ldm_geartab.h A util/cbfstool/zstd/compress/zstd_opt.c A util/cbfstool/zstd/compress/zstd_opt.h A util/cbfstool/zstd/compress/zstdmt_compress.c A util/cbfstool/zstd/compress/zstdmt_compress.h A util/cbfstool/zstd/zdict.h A util/cbfstool/zstd/zstd.h A util/cbfstool/zstd/zstd_errors.h 84 files changed, 54,802 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/69753/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34508268f8767008ef25cb9e466d201345881232 Gerrit-Change-Number: 69753 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/crossgcc: Limit LLVM targets to the needed ones
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69841 ) Change subject: util/crossgcc: Limit LLVM targets to the needed ones ...................................................................... util/crossgcc: Limit LLVM targets to the needed ones coreboot only supports a small subset of the targets that LLVM supports. It's not needed to enable all possible targets. Thus limit the targets to the following ones: * X86 * RISC-V * AArch32 * AArch64 * PowerPC Change-Id: I9938bf176b5fe2b0a631c3b1ae858f988898a196 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69841 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M util/crossgcc/buildgcc 1 file changed, 26 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9b7fc1c..6e8d3f0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -813,7 +813,8 @@ $CMAKE -G "Unix Makefiles" -DCMAKE_INSTALL_PREFIX="$DESTDIR$TARGETDIR" \ -DCLANG_VENDOR="coreboot toolchain v$CROSSGCC_VERSION - " \ -DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;compiler-rt" \ - -DLLVM_INCLUDE_BENCHMARKS="OFF" -DCMAKE_BUILD_TYPE=Release ../llvm || touch .failed + -DLLVM_INCLUDE_BENCHMARKS="OFF" -DCMAKE_BUILD_TYPE=Release ../llvm \ + -DLLVM_TARGETS_TO_BUILD="AArch64;ARM;PowerPC;RISCV;X86" || touch .failed # shellcheck disable=SC2086 $MAKE $JOBS || touch .failed $MAKE install || touch .failed -- To view, visit https://review.coreboot.org/c/coreboot/+/69841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9938bf176b5fe2b0a631c3b1ae858f988898a196 Gerrit-Change-Number: 69841 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: sb/intel/i82801gx/lpc.c: Use post_code()
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Arthur Heymans, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69901 ) Change subject: sb/intel/i82801gx/lpc.c: Use post_code() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Gerrit-Change-Number: 69901 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 22 Nov 2022 15:09:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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