coreboot-gerrit November 2022

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[M] Change in coreboot[master]: soc/amd/*/Makefile: fix readelf parameters to get bootblock size
by build bot (Jenkins) (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69895 ) Change subject: soc/amd/*/Makefile: fix readelf parameters to get bootblock size ...................................................................... Patch Set 1: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164286): https://review.coreboot.org/c/coreboot/+/69895/comment/31b5407c_eff2cf50 PS1, Line 25: LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000 Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164286): https://review.coreboot.org/c/coreboot/+/69895/comment/70a1ffdc_0d30d427 PS1, Line 31: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164286): https://review.coreboot.org/c/coreboot/+/69895/comment/0c7cc0f9_9c9d5937 PS1, Line 37: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164286): https://review.coreboot.org/c/coreboot/+/69895/comment/94661eba_e5554e38 PS1, Line 38: LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Gerrit-Change-Number: 69895 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 19:25:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] soc/amd/cezanne: Add support for 64bit builds
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

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[S] Change in coreboot[master]: [WIP] vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy conf...
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69897 ) Change subject: [WIP] vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configuration ...................................................................... [WIP] vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configuration The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c --- M src/soc/amd/cezanne/fsp_m_params.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 2 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/69897/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index f370331..f86be94 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -4,6 +4,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <assert.h> +#include <console/console.h> #include <console/uart.h> #include <device/device.h> #include <fsp/api.h> @@ -156,9 +157,15 @@ lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); - mcfg->usb_phy = &lcl_usb_phy; + if ((uintptr_t)&lcl_usb_phy <= UINT32_MAX) { + mcfg->usb_phy_ptr = (uint32_t)(uintptr_t)&lcl_usb_phy; + } else { + printk(BIOS_ERR, "USB PHY config struct above 4GB; can't pass USB PHY " + "configuration to 32 bit FSP.\n"); + mcfg->usb_phy_ptr = 0; + } } else { - mcfg->usb_phy = NULL; + mcfg->usb_phy_ptr = 0; } if (config->edp_phy_override) { diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 38aa36c..92dbb23 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -94,7 +94,8 @@ /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; - /** Offset 0x04D8**/ struct usb_phy_config *usb_phy; + /* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */ + /** Offset 0x04D8**/ uint32_t usb_phy_ptr; /** Offset 0x04DC**/ uint8_t edp_phy_override; /** Offset 0x04DD**/ uint8_t edp_physel; /** Offset 0x04DE**/ uint8_t dp_vs_pemph_level; -- To view, visit https://review.coreboot.org/c/coreboot/+/69897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Gerrit-Change-Number: 69897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/fsp_m_params: rework local USB PHY table update
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69896 ) Change subject: soc/amd/*/fsp_m_params: rework local USB PHY table update ...................................................................... soc/amd/*/fsp_m_params: rework local USB PHY table update Update the fields that need to be updated directly in the local static usb_phy_config struct instead of dereferencing the pointer written to the corresponding UPD field. This will allow updating the type of UPD field in a follow-up commit to enable 64 bit coreboot builds. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d --- M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/glinda/fsp_m_params.c M src/soc/amd/mendocino/fsp_m_params.c M src/soc/amd/morgana/fsp_m_params.c 4 files changed, 27 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/69896/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index ba2663a..f370331 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -153,10 +153,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c index 7e78287..d8de742 100644 --- a/src/soc/amd/glinda/fsp_m_params.c +++ b/src/soc/amd/glinda/fsp_m_params.c @@ -155,10 +155,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index ed8be66..8cbea5d 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -154,10 +154,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } diff --git a/src/soc/amd/morgana/fsp_m_params.c b/src/soc/amd/morgana/fsp_m_params.c index e1e8c26..0c51c1a 100644 --- a/src/soc/amd/morgana/fsp_m_params.c +++ b/src/soc/amd/morgana/fsp_m_params.c @@ -155,10 +155,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d Gerrit-Change-Number: 69896 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/*/Makefile: fix readelf parameters to get bootblock size
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69895 ) Change subject: soc/amd/*/Makefile: fix readelf parameters to get bootblock size ...................................................................... soc/amd/*/Makefile: fix readelf parameters to get bootblock size This ports forward part of commit df0968062622 ("soc/amd/picasso: Add support for 64bit builds") to the newer AMD SoCs. Use -Wl instead of -l to get the output format that the commands in the Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this change, readelf will split the output into two lines in case of a 64 bit coreboot build. This results in invalid amdcompress and amdfwtool command lines which will cause the amdfwtool call to fail with Error: BIOS binary destination and uncompressed size are required With the old readelf -l command we get this output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000 0x0000000000010000 0x0000000000010000 RWE 0x10 while we get the correct output in a 32 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20 With readelf -Wl we also get the expected output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10 TEST=This fixes the 64 bit build on Cezanne with some follow-up patches applied. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/morgana/Makefile.inc 4 files changed, 52 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/69895/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 1f2bb6d..091e63f 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -141,8 +141,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index e00421d..4d1ba55 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -141,8 +141,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 92c75f8..ab709e6 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -142,8 +142,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index a88e1a5..44a92eb 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -141,8 +141,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -- To view, visit https://review.coreboot.org/c/coreboot/+/69895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Gerrit-Change-Number: 69895 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Karthik Ramasubramanian (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Arthur Heymans, Martin Roth, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/b9f9aaab_8330d7d1 PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) > > This will lead to integer overflow if CONFIG_AMD_FWM_POSITION is greater than ROM_SIZE. […] Earlier the position was in memory map 0xffc20000 and the SPI ROM was in the memory map range [0xff800000..0xffffffff]. So it was right. Now that we have redefined the meaning of AMD_FWM_POSITION to be flash offset, we have to define more offsets(not just 6) such that this arithmetic fit within the memory map. -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 18:52:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: DO NOT MERGE: Disable clang chromeos builds
by Martin L Roth (Code Review) 22 Nov '22

22 Nov '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69626 to look at the new patch set (#3). Change subject: DO NOT MERGE: Disable clang chromeos builds ...................................................................... DO NOT MERGE: Disable clang chromeos builds Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie92c0144481562b7579bced6ac23813b914b10c5 --- M util/abuild/abuild 1 file changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/69626/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie92c0144481562b7579bced6ac23813b914b10c5 Gerrit-Change-Number: 69626 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Arthur Heymans (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/3faa1d99_cab8e6d3 PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) > This will lead to integer overflow if CONFIG_AMD_FWM_POSITION is greater than ROM_SIZE. > > eg. Mandolin has 8 MB ROM size but AMD_FWM_POSITION is 0xc20000 I guess the position for mandolin is just wrong then. -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 18:16:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Karthik Ramasubramanian (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Arthur Heymans, Martin Roth, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/8891b122_2e9486b7 PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) This will lead to integer overflow if CONFIG_AMD_FWM_POSITION is greater than ROM_SIZE. eg. Mandolin has 8 MB ROM size but AMD_FWM_POSITION is 0xc20000 -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 18:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Karthik Ramasubramanian (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Arthur Heymans, Martin Roth, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/cezanne/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/b2e1b2b3_9cb26ee8 PS4, Line 232: CEZANNE_FWM_POSITION Undefined value. Please check other SoC variants. Some SoCs have it updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 18:02:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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