coreboot-gerrit November 2022

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[S] Change in coreboot[master]: device/xhci: Add struct for capability registers
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69915 ) Change subject: device/xhci: Add struct for capability registers ...................................................................... device/xhci: Add struct for capability registers The XHCI code does not currently contain a structure that corresponds to the XHCI capability registers. These registers contain various useful information about the controller. This commit creates a `xhci_capability_regs` struct to address this. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/include/device/xhci.h 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/69915/1 diff --git a/src/include/device/xhci.h b/src/include/device/xhci.h index 3fcb4eb..cff0437 100644 --- a/src/include/device/xhci.h +++ b/src/include/device/xhci.h @@ -95,6 +95,19 @@ uint32_t num_usb3_ports; }; +struct xhci_capability_regs { + uint8_t caplength; + uint8_t reserved0; + uint16_t hciversion; + uint32_t hcsparams1; + uint32_t hcsparams2; + uint32_t hcsparams3; + uint32_t hccparams1; + uint32_t dboff; + uint32_t rtsoff; + uint32_t hccparams2; +}; + /** * Iterates over the xHCI Extended Capabilities List. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Gerrit-Change-Number: 69915 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: device/xhci: Refactor functions to work with a non-const device tree
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Refactor functions to work with a non-const device tree ...................................................................... device/xhci: Refactor functions to work with a non-const device tree The XHCI device functions currently use functions that require a non-const device tree. This commit creates variants of these functions that can operate with a resource* as an argument and refactors the existing device*-based functions to operate by calling the resource*-based variants. This allows for this functionality to be used in stages with a const device tree, like SMM. BRANCH=guybrush BUG=b:186792595 TEST=Ran on skyrim device, verified that XHCI ACPI tables are still generated correctly. Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/device/Makefile.inc M src/device/xhci.c A src/device/xhci_const.c M src/include/device/xhci.h 4 files changed, 163 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/69914/1 diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 28acd73..a87f844 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -61,6 +61,7 @@ ramstage-y += resource_allocator_common.c ramstage-y += resource_allocator_v4.c -ramstage-$(CONFIG_XHCI_UTILS) += xhci.c +ramstage-$(CONFIG_XHCI_UTILS) += xhci.c xhci_const.c +smm-$(CONFIG_XHCI_UTILS) += xhci_const.c ramstage-y += gpio.c diff --git a/src/device/xhci.c b/src/device/xhci.c index 4523b56..e515402 100644 --- a/src/device/xhci.c +++ b/src/device/xhci.c @@ -2,31 +2,18 @@ #include <arch/mmio.h> #include <console/console.h> +#include <device/device.h> #include <device/pci_def.h> #include <device/xhci.h> -#include <string.h> - -union xhci_ext_caps_header { - uint32_t val; - struct { - uint32_t cap_id : 8; - uint32_t next_ptr : 8; - uint32_t reserved : 16; - }; -}; enum cb_err xhci_for_each_ext_cap(const struct device *device, void *context, void (*callback)(void *context, const struct xhci_ext_cap *cap)) { - struct resource *res; - uint32_t *ext_cap_ptr; - uint32_t ext_caps_word_offset; - union xhci_ext_caps_header header; - struct xhci_ext_cap cap; + const struct resource *res; - if (!device || !callback) - return CB_ERR_ARG; + if (!device) + return CB_ERR; res = probe_resource(device, PCI_BASE_ADDRESS_0); if (!res) { @@ -35,89 +22,24 @@ return CB_ERR; } - if (!(res->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "%s: BAR is not assigned\n", __func__); - return CB_ERR; - } - - if (res->limit > 0xFFFFFFFF) { - printk(BIOS_ERR, "%s: 64-bit BAR is not supported\n", __func__); - return CB_ERR; - } - - ext_caps_word_offset = read16(res2mmio(res, XHCI_HCCPARAMS1_XECP, 0)); - - if (!ext_caps_word_offset) { - printk(BIOS_ERR, "%s: No extended capabilities defined\n", __func__); - return CB_ERR; - } - - ext_cap_ptr = res2mmio(res, ext_caps_word_offset << 2, 0); - - while ((uintptr_t)ext_cap_ptr < (uintptr_t)res->limit) { - header.val = read32(ext_cap_ptr); - - cap.cap_id = header.cap_id; - - if (header.cap_id == XHCI_ECP_CAP_ID_SUPP) { - cap.supported_protocol.reg0 = header.val; - cap.supported_protocol.reg1 = read32(ext_cap_ptr + 1); - cap.supported_protocol.reg2 = read32(ext_cap_ptr + 2); - } - - callback(context, &cap); - - if (!header.next_ptr) - break; - - ext_cap_ptr += header.next_ptr; - } - - return CB_SUCCESS; -} - -struct supported_usb_cap_context { - void *context; - void (*callback)(void *context, const struct xhci_supported_protocol *data); -}; - -static void xhci_supported_usb_cap_handler(void *context, const struct xhci_ext_cap *cap) -{ - const struct xhci_supported_protocol *data; - struct supported_usb_cap_context *internal_context = context; - - if (cap->cap_id != XHCI_ECP_CAP_ID_SUPP) - return; - - data = &cap->supported_protocol; - - if (memcmp(data->name, "USB ", 4)) { - printk(BIOS_DEBUG, "%s: Unknown Protocol: %.*s\n", __func__, - (int)sizeof(data->name), data->name); - return; - } - - internal_context->callback(internal_context->context, data); + return xhci_resource_for_each_ext_cap(res, context, callback); } enum cb_err xhci_for_each_supported_usb_cap( const struct device *device, void *context, void (*callback)(void *context, const struct xhci_supported_protocol *data)) { - struct supported_usb_cap_context internal_context = { - .context = context, - .callback = callback, - }; + const struct resource *res; - return xhci_for_each_ext_cap(device, &internal_context, xhci_supported_usb_cap_handler); -} + if (!device) + return CB_ERR; -void xhci_print_supported_protocol(const struct xhci_supported_protocol *supported_protocol) -{ - printk(BIOS_DEBUG, "xHCI Supported Protocol:\n"); - printk(BIOS_DEBUG, " Major: %#x, Minor: %#x, Protocol: '%.*s'\n", - supported_protocol->major_rev, supported_protocol->minor_rev, - (int)sizeof(supported_protocol->name), supported_protocol->name); - printk(BIOS_DEBUG, " Port Offset: %d, Port Count: %d\n", - supported_protocol->port_offset, supported_protocol->port_count); -} + res = probe_resource(device, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "%s: Unable to find BAR resource for %s\n", __func__, + dev_path(device)); + return CB_ERR; + } + + return xhci_resource_for_each_supported_usb_cap(res, context, callback); +} \ No newline at end of file diff --git a/src/device/xhci_const.c b/src/device/xhci_const.c new file mode 100644 index 0000000..55e312c --- /dev/null +++ b/src/device/xhci_const.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/mmio.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/xhci.h> +#include <string.h> + +union xhci_ext_caps_header { + uint32_t val; + struct { + uint32_t cap_id : 8; + uint32_t next_ptr : 8; + uint32_t reserved : 16; + }; +}; + +enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, + void (*callback)(void *context, + const struct xhci_ext_cap *cap)) +{ + uint32_t *ext_cap_ptr; + uint32_t ext_caps_word_offset; + union xhci_ext_caps_header header; + struct xhci_ext_cap cap; + + if (!res || !callback) + return CB_ERR_ARG; + + if (!(res->flags & IORESOURCE_ASSIGNED)) { + printk(BIOS_ERR, "%s: BAR is not assigned\n", __func__); + return CB_ERR; + } + + if (res->limit > 0xFFFFFFFF) { + printk(BIOS_ERR, "%s: 64-bit BAR is not supported\n", __func__); + return CB_ERR; + } + + ext_caps_word_offset = read16(res2mmio(res, XHCI_HCCPARAMS1_XECP, 0)); + + if (!ext_caps_word_offset) { + printk(BIOS_ERR, "%s: No extended capabilities defined\n", __func__); + return CB_ERR; + } + + ext_cap_ptr = res2mmio(res, ext_caps_word_offset << 2, 0); + + while ((uintptr_t)ext_cap_ptr < (uintptr_t)res->limit) { + header.val = read32(ext_cap_ptr); + + cap.cap_id = header.cap_id; + + if (header.cap_id == XHCI_ECP_CAP_ID_SUPP) { + cap.supported_protocol.reg0 = header.val; + cap.supported_protocol.reg1 = read32(ext_cap_ptr + 1); + cap.supported_protocol.reg2 = read32(ext_cap_ptr + 2); + } + + callback(context, &cap); + + if (!header.next_ptr) + break; + + ext_cap_ptr += header.next_ptr; + } + + return CB_SUCCESS; +} + +struct supported_usb_cap_context { + void *context; + void (*callback)(void *context, const struct xhci_supported_protocol *data); +}; + +static void xhci_supported_usb_cap_handler(void *context, const struct xhci_ext_cap *cap) +{ + const struct xhci_supported_protocol *data; + struct supported_usb_cap_context *internal_context = context; + + if (cap->cap_id != XHCI_ECP_CAP_ID_SUPP) + return; + + data = &cap->supported_protocol; + + if (memcmp(data->name, "USB ", 4)) { + printk(BIOS_DEBUG, "%s: Unknown Protocol: %.*s\n", __func__, + (int)sizeof(data->name), data->name); + return; + } + + internal_context->callback(internal_context->context, data); +} + +enum cb_err xhci_resource_for_each_supported_usb_cap( + const struct resource *res, void *context, + void (*callback)(void *context, const struct xhci_supported_protocol *data)) +{ + struct supported_usb_cap_context internal_context = { + .context = context, + .callback = callback, + }; + + return xhci_resource_for_each_ext_cap(res, &internal_context, + xhci_supported_usb_cap_handler); +} + +void xhci_print_supported_protocol(const struct xhci_supported_protocol *supported_protocol) +{ + printk(BIOS_DEBUG, "xHCI Supported Protocol:\n"); + printk(BIOS_DEBUG, " Major: %#x, Minor: %#x, Protocol: '%.*s'\n", + supported_protocol->major_rev, supported_protocol->minor_rev, + (int)sizeof(supported_protocol->name), supported_protocol->name); + printk(BIOS_DEBUG, " Port Offset: %d, Port Count: %d\n", + supported_protocol->port_offset, supported_protocol->port_count); +} \ No newline at end of file diff --git a/src/include/device/xhci.h b/src/include/device/xhci.h index a4a3bc1..3fcb4eb 100644 --- a/src/include/device/xhci.h +++ b/src/include/device/xhci.h @@ -98,6 +98,9 @@ /** * Iterates over the xHCI Extended Capabilities List. */ +enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, + void (*callback)(void *context, + const struct xhci_ext_cap *cap)); enum cb_err xhci_for_each_ext_cap(const struct device *device, void *context, void (*callback)(void *context, const struct xhci_ext_cap *cap)); @@ -109,6 +112,9 @@ enum cb_err xhci_for_each_supported_usb_cap( const struct device *device, void *context, void (*callback)(void *context, const struct xhci_supported_protocol *data)); +enum cb_err xhci_resource_for_each_supported_usb_cap( + const struct resource *res, void *context, + void (*callback)(void *context, const struct xhci_supported_protocol *data)); void xhci_print_supported_protocol(const struct xhci_supported_protocol *supported_protocol); -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/guybrush: Store XHCI BARs
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Nien, Martin Roth, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Nien, Martin Roth, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68326 to look at the new patch set (#7). Change subject: mb/google/guybrush: Store XHCI BARs ...................................................................... mb/google/guybrush: Store XHCI BARs This commit implements `smm_mainboard_pci_bar_store_init` to store the BARs for XHCI devices. These stored BARs are later used by the elog code to log XHCI wake events. Example elog contents: ``` 250 | 2022-10-11 16:04:49 | S0ix Enter 251 | 2022-10-11 16:04:53 | S0ix Exit 252 | 2022-10-11 16:04:53 | Wake Source | GPE # | 31 253 | 2022-10-11 16:04:53 | Wake Source | PME - XHCI (USB 2.0 port) | 1 254 | 2022-10-11 16:05:24 | S0ix Enter 255 | 2022-10-11 16:05:27 | S0ix Exit 256 | 2022-10-11 16:05:27 | Wake Source | GPE # | 31 257 | 2022-10-11 16:05:27 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin, verified that XHCI wake events show up in elog Change-Id: I1d0911df9e3102791bf7b5723ac38e2ba82a9db6 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/mainboard/google/guybrush/mainboard.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/68326/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/68326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0911df9e3102791bf7b5723ac38e2ba82a9db6 Gerrit-Change-Number: 68326 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/cezanne: Set up SoC-specific XHCI definitions
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67939 to look at the new patch set (#8). Change subject: soc/amd/cezanne: Set up SoC-specific XHCI definitions ...................................................................... soc/amd/cezanne: Set up SoC-specific XHCI definitions This commit sets up SoC-specific XHCI definitions. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/xhci.h 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/67939/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/67939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 Gerrit-Change-Number: 67939 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim: Store XHCI PCI BARs
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Robert Zieba, Raul Rangel, Jason Nien, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Martin Roth, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68325 to look at the new patch set (#7). Change subject: mb/google/skyrim: Store XHCI PCI BARs ...................................................................... mb/google/skyrim: Store XHCI PCI BARs This commit implements `smm_mainboard_pci_bar_store_init` to store the BARs for XHCI devices. These stored BARs are later used by the elog code to log XHCI wake events. Example elog contents: ``` 244 | 2022-10-11 15:49:24 | S0ix Enter 245 | 2022-10-11 15:49:29 | S0ix Exit 246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31 247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256 248 | 2022-10-11 15:50:08 | S0ix Enter 249 | 2022-10-11 15:50:16 | S0ix Exit 250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31 251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BUG=b:186792595 TEST=Ran on skyrim proto, verified that wake events show in elog Change-Id: I529f541a8932267a8825773ddc582beafb27da63 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/mainboard/google/skyrim/mainboard.c 1 file changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/68325/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/68325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529f541a8932267a8825773ddc582beafb27da63 Gerrit-Change-Number: 68325 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Set up SoC-specific XHCI defines
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Matt DeVillier, Angel Pons, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67938 to look at the new patch set (#8). Change subject: soc/amd/mendocino: Set up SoC-specific XHCI defines ...................................................................... soc/amd/mendocino: Set up SoC-specific XHCI defines This commit sets up SoC-specific XHCI defines. BUG=b:186792595 TEST=builds Change-Id: I16c789ff673c26ded84e4d46ab6dc743f33c5bb7 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/soc/amd/mendocino/Kconfig A src/soc/amd/mendocino/include/soc/xhci.h 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/67938/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/67938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16c789ff673c26ded84e4d46ab6dc743f33c5bb7 Gerrit-Change-Number: 67938 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/xhci: Add support for logging XHCI wake events
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Angel Pons, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67936 to look at the new patch set (#8). Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events ...................................................................... soc/amd/common/xhci: Add support for logging XHCI wake events This commit adds code to log XHCI wake events to the elog. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/soc/amd/common/block/acpi/elog.c A src/soc/amd/common/block/include/amdblocks/xhci.h A src/soc/amd/common/block/xhci/Kconfig A src/soc/amd/common/block/xhci/Makefile.inc A src/soc/amd/common/block/xhci/elog.c A src/soc/amd/common/block/xhci/xhci.c 6 files changed, 198 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/67936/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/67936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Gerrit-Change-Number: 67936 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/x86/smm: Add PCI BAR store functionality
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Arthur Heymans, Robert Zieba, Nico Huber, Angel Pons, Karthik Ramasubramanian, Felix Held. Hello Arthur Heymans, build bot (Jenkins), Martin Roth, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67931 to look at the new patch set (#8). Change subject: cpu/x86/smm: Add PCI BAR store functionality ...................................................................... cpu/x86/smm: Add PCI BAR store functionality In certain cases data within protected memmory areas like SMRAM could be leaked or modified if an attacker remaps PCI BARs to point within that area. This commit adds support to the existing SMM to allow storing PCI BARs in SMRAM and then later retrieved. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/pci_bar_store.c M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 6 files changed, 139 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/67931/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd: Define post codes
by Martin L Roth (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69867 ) Change subject: soc/amd: Define post codes ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/include/amdblocks/post_codes.h: https://review.coreboot.org/c/coreboot/+/69867/comment/e847caf4_161f1d68 PS2, Line 15: POST_PSP_NOTIFY_DRAM > this should probably be POST_PSP_NOTIFY_DRAM_DONE. […] Yah. Thanks - missed that. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Gerrit-Change-Number: 69867 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 20:42:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Define post codes
by Martin L Roth (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69867 to look at the new patch set (#3). Change subject: soc/amd: Define post codes ...................................................................... soc/amd: Define post codes For the most part, this doesn't change any post codes, simply making the existing post-codes into macros. picasso/romstage.c did get a couple of post codes removed to match the other files. The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global at some point, while the POST_AGESA and POST_PSP codes would stay AMD specific. Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/noncar/pre_c.S A src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/morgana/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 11 files changed, 86 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/69867/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Gerrit-Change-Number: 69867 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022