coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: mb/google/brya/var/marasov: update pch_espi setting
by Nick Vaccaro (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kyle Lin, Frank Chu. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69785 ) Change subject: mb/google/brya/var/marasov: update pch_espi setting ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f Gerrit-Change-Number: 69785 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 21:40:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/marasov: Update SPD ID assignment
by Nick Vaccaro (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Tarun Tuli, Kyle Lin, Frank Chu. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69784 ) Change subject: mb/google/brya/var/marasov: Update SPD ID assignment ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt: https://review.coreboot.org/c/coreboot/+/69784/comment/63ec3c2b_0682f518 PS2, Line 7: 0 (0000) : H9JCNNNBK3MLYR-N6E 1 (0001) : MT62F1G32D4DR-031 WT:B 2 (0010) : H9JCNNNCP3MLYR-N6E 3 > I will give this CL a +2 as-is, but JFYI, it would be more efficient to define the dram id strap val […] Just to confirm. it's OK to use seperate and unique DRAM_ID strap values for your 4 memory parts, just wanted to make sure that you realize you could use 2 DRAM_ID values instead of 4, which also saves space in your CBFS image by bundling 2 SPDs instead of 4. -- To view, visit https://review.coreboot.org/c/coreboot/+/69784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0 Gerrit-Change-Number: 69784 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 21:38:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/marasov: Update SPD ID assignment
by Nick Vaccaro (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Tarun Tuli, Kyle Lin, Frank Chu. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69784 ) Change subject: mb/google/brya/var/marasov: Update SPD ID assignment ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt: https://review.coreboot.org/c/coreboot/+/69784/comment/6a0b5694_35d67c9d PS2, Line 7: 0 (0000) : H9JCNNNBK3MLYR-N6E 1 (0001) : MT62F1G32D4DR-031 WT:B 2 (0010) : H9JCNNNCP3MLYR-N6E 3 I will give this CL a +2 as-is, but JFYI, it would be more efficient to define the dram id strap values as follows: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0001) MT62F1G32D4DR-031 WT:B 1 (0010) H9JCNNNCP3MLYR-N6E 1 (0011) I thought the tool assigned it this way automatically to save more open slots of DRAM_ID values for future memory upgrades and to include fewer SPD files in the image. -- To view, visit https://review.coreboot.org/c/coreboot/+/69784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0 Gerrit-Change-Number: 69784 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 21:34:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: /: Update and rewrite README.md
by build bot (Jenkins) (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Felix Singer, Martin L Roth, Matt DeVillier, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67119 ) Change subject: /: Update and rewrite README.md ...................................................................... Patch Set 5: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164303): https://review.coreboot.org/c/coreboot/+/67119/comment/720a77b6_ad1695a6 PS5, Line 8: 'readme' may be misspelled - perhaps 'readme'? -- To view, visit https://review.coreboot.org/c/coreboot/+/67119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cd59d75da47b287029a9fc5eeddefaf99198965 Gerrit-Change-Number: 67119 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 20:57:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: /: Update and rewrite README.md
by Martin L Roth (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Felix Singer, Martin L Roth, Matt DeVillier, Martin Roth. Hello Felix Singer, build bot (Jenkins), Matt DeVillier, Angel Pons, Elyes Haouas, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67119 to look at the new patch set (#5). Change subject: /: Update and rewrite README.md ...................................................................... /: Update and rewrite README.md Update the top level readme file to reflect the updated documentation and project status. This is mostly a rewrite, but some text was just reformatted. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I2cd59d75da47b287029a9fc5eeddefaf99198965 --- M README.md 1 file changed, 166 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/67119/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/67119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cd59d75da47b287029a9fc5eeddefaf99198965 Gerrit-Change-Number: 67119 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: device/xhci: Refactor functions to work with a non-const device tree
by build bot (Jenkins) (Code Review) 22 Nov '22

22 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Refactor functions to work with a non-const device tree ...................................................................... Patch Set 1: (4 comments) File src/device/xhci.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164299): https://review.coreboot.org/c/coreboot/+/69914/comment/49ac63ad_e3467560 PS1, Line 45: } adding a line without newline at end of file File src/device/xhci_const.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164299): https://review.coreboot.org/c/coreboot/+/69914/comment/85daf733_8419f0ba PS1, Line 18: enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164299): https://review.coreboot.org/c/coreboot/+/69914/comment/a17e6739_21b882f0 PS1, Line 95: enum cb_err xhci_resource_for_each_supported_usb_cap( that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164299): https://review.coreboot.org/c/coreboot/+/69914/comment/41f8a3e7_2dc148c9 PS1, Line 116: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Nov 2022 20:52:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Set up SoC-specific XHCI defines
by build bot (Jenkins) (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Matt DeVillier, Angel Pons, Fred Reitberger, Karthik Ramasubramanian, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67938 ) Change subject: soc/amd/mendocino: Set up SoC-specific XHCI defines ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/mendocino/include/soc/xhci.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164295): https://review.coreboot.org/c/coreboot/+/67938/comment/fa13209b_f1af3101 PS8, Line 15: #endif /* AMD_MENDOCINO_XHCI_H */ adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/67938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16c789ff673c26ded84e4d46ab6dc743f33c5bb7 Gerrit-Change-Number: 67938 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 20:51:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/amd/common/xhci: Add support for logging XHCI wake events
by build bot (Jenkins) (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Angel Pons, Fred Reitberger, Karthik Ramasubramanian, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67936 ) Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events ...................................................................... Patch Set 8: (16 comments) File src/soc/amd/common/block/include/amdblocks/xhci.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/f183ba1e_a8fdaf3d PS8, Line 16: SOC_XHCI_0,\ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/0bd6cb8f_d6c260de PS8, Line 17: SOC_XHCI_1,\ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/30439643_44826aff PS8, Line 18: SOC_XHCI_2,\ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/1c9df2b5_ef29f9ca PS8, Line 19: SOC_XHCI_3,\ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/6d7a7c68_6e9dd779 PS8, Line 20: SOC_XHCI_4,\ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/e08fa12e_f2f10f4f PS8, Line 21: SOC_XHCI_5,\ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/6d477a5a_e19a5d7a PS8, Line 22: SOC_XHCI_6,\ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/977f0a7f_4dcd457d PS8, Line 23: SOC_XHCI_7,\ please, no spaces at the start of a line File src/soc/amd/common/block/xhci/elog.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/f08aa86f_b7887e4a PS8, Line 13: #define PORTSC_OFFSET 0x400; macros should not use a trailing semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/5533307e_46b58ff1 PS8, Line 47: const struct xhci_context *context = (const struct xhci_context*)data; "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/0cd3c0d3_dbcfda50 PS8, Line 50: (const struct xhci_capability_regs*)context->bar; "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/b12d389f_2bbc1616 PS8, Line 84: } Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/37efb547_63062a3c PS8, Line 98: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/d1402080_6b3dff1e PS8, Line 104: const struct resource *res = (const struct resource*) &bar_store[i_bar].bars[0]; "(foo*)" should be "(foo *)" File src/soc/amd/common/block/xhci/xhci.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/fd79ec82_f783b10b PS8, Line 12: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164294): https://review.coreboot.org/c/coreboot/+/67936/comment/12a94ec9_b011ee06 PS8, Line 19: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/67936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Gerrit-Change-Number: 67936 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 20:50:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/cezanne: Update XHCI GPE to use constant
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69917 ) Change subject: soc/amd/cezanne: Update XHCI GPE to use constant ...................................................................... soc/amd/cezanne: Update XHCI GPE to use constant The GPE number used for XHCI has now been defined in AMD's common code This commit changes over existing code to use this new definition. BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin device and verified that XHCI events string use GPE 31. Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 --- M src/soc/amd/cezanne/xhci.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/69917/1 diff --git a/src/soc/amd/cezanne/xhci.c b/src/soc/amd/cezanne/xhci.c index f599007..b0205c6 100644 --- a/src/soc/amd/cezanne/xhci.c +++ b/src/soc/amd/cezanne/xhci.c @@ -2,6 +2,7 @@ #include <amdblocks/gpio.h> #include <amdblocks/smi.h> +#include <amdblocks/xhci.h> #include <bootstate.h> #include <device/device.h> #include <drivers/usb/pci_xhci/pci_xhci.h> @@ -11,13 +12,13 @@ static const struct sci_source xhci_sci_sources[] = { { .scimap = SMITYPE_XHC0_PME, - .gpe = GEVENT_31, + .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG }, { .scimap = SMITYPE_XHC1_PME, - .gpe = GEVENT_31, + .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG } -- To view, visit https://review.coreboot.org/c/coreboot/+/69917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 Gerrit-Change-Number: 69917 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Update XHCI GPE to use constant
by Robert Zieba (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69916 ) Change subject: soc/amd/mendocino: Update XHCI GPE to use constant ...................................................................... soc/amd/mendocino: Update XHCI GPE to use constant The GPE number used for XHCI has now been defined in AMD's common code. This commit changes over existing code to use this new definition. BUG=b:186792595 TEST=Ran on skyrim device and verified XHCI GPE setting. Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I3bfc2256ea2ca851afe88f2cdb419f39eee76fdd --- M src/soc/amd/common/block/xhci/elog.c M src/soc/amd/mendocino/xhci.c 2 files changed, 23 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/69916/1 diff --git a/src/soc/amd/common/block/xhci/elog.c b/src/soc/amd/common/block/xhci/elog.c index 8e53cdb9..7378ac3 100644 --- a/src/soc/amd/common/block/xhci/elog.c +++ b/src/soc/amd/common/block/xhci/elog.c @@ -10,7 +10,7 @@ #include <device/xhci.h> #include <elog.h> -#define PORTSC_OFFSET 0x400; +#define PORTSC_OFFSET 0x400 #define PORTSC_STRIDE 0x10 #define XHCI_PROG_ID 0x30 @@ -53,7 +53,7 @@ uintptr_t op_base = context->bar + cap_regs->caplength; uintptr_t addr = op_base + PORTSC_OFFSET + PORTSC_STRIDE * (protocol->port_offset - 1); - switch (protocol->major_rev == 2) { + switch (protocol->major_rev) { case 2: xhci_port_wake_check(addr, controller, count, ELOG_WAKE_SOURCE_PME_XHCI_USB_2); break; diff --git a/src/soc/amd/mendocino/xhci.c b/src/soc/amd/mendocino/xhci.c index fdd0118..720cc76 100644 --- a/src/soc/amd/mendocino/xhci.c +++ b/src/soc/amd/mendocino/xhci.c @@ -4,6 +4,7 @@ #include <amdblocks/gpio.h> #include <amdblocks/smi.h> +#include <amdblocks/xhci.h> #include <bootstate.h> #include <device/device.h> #include <device/pci_ids.h> @@ -14,19 +15,19 @@ static const struct sci_source xhci_sci_sources[] = { { .scimap = SMITYPE_XHC0_PME, - .gpe = GEVENT_31, + .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG }, { .scimap = SMITYPE_XHC1_PME, - .gpe = GEVENT_31, + .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG }, { .scimap = SMITYPE_XHC2_PME, - .gpe = GEVENT_31, + .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG } -- To view, visit https://review.coreboot.org/c/coreboot/+/69916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bfc2256ea2ca851afe88f2cdb419f39eee76fdd Gerrit-Change-Number: 69916 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022