coreboot-gerrit November 2022

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[S] Change in coreboot[master]: contributing/project_ideas.md: Fix outb() parameter order
by Elyes Haouas (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Martin L Roth, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69902 ) Change subject: contributing/project_ideas.md: Fix outb() parameter order ...................................................................... Patch Set 1: (2 comments) File Documentation/contributing/project_ideas.md: https://review.coreboot.org/c/coreboot/+/69902/comment/7b212d2c_e39a67b3 PS1, Line 39: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/art… the link is broken, isn't it? https://review.coreboot.org/c/coreboot/+/69902/comment/0f3eca4e_d7dd050a PS1, Line 199: Replace `outb(..., 0x80)` with calls to `post_code(...)` maybe we can remove as the last one is pushed here: https://review.coreboot.org/c/coreboot/+/69901 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/69902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f9e892f14d4e38c8f90490c8d2b66013cc139a2 Gerrit-Change-Number: 69902 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 14:42:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: sb/intel/i82801gx/lpc.c: Use post_code()
by Elyes Haouas (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69901 ) Change subject: sb/intel/i82801gx/lpc.c: Use post_code() ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/69901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Gerrit-Change-Number: 69901 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 22 Nov 2022 14:32:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: contributing/project_ideas.md: Fix outb() parameter order
by Elyes Haouas (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69902 ) Change subject: contributing/project_ideas.md: Fix outb() parameter order ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/69902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f9e892f14d4e38c8f90490c8d2b66013cc139a2 Gerrit-Change-Number: 69902 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 14:28:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: contributing/project_ideas.md: Fix outb() parameter order
by Elyes Haouas (Code Review) 22 Nov '22

22 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69902 ) Change subject: contributing/project_ideas.md: Fix outb() parameter order ...................................................................... contributing/project_ideas.md: Fix outb() parameter order Change-Id: I7f9e892f14d4e38c8f90490c8d2b66013cc139a2 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Documentation/contributing/project_ideas.md 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/69902/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 94fdefe..c76bb21 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -196,7 +196,7 @@ Tasks: * Guard Kconfigs with a *depends on* to only show on supported platforms * Remove duplicated Kconfigs -* Replace `outb(0x80, ...)` with calls to `post_code(...)` +* Replace `outb(..., 0x80)` with calls to `post_code(...)` * Update Documentation/POSTCODES * Use defines from console/post_codes.h where possible * Drop duplicated POST codes -- To view, visit https://review.coreboot.org/c/coreboot/+/69902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f9e892f14d4e38c8f90490c8d2b66013cc139a2 Gerrit-Change-Number: 69902 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vboot: Fix hash digest size, padding and comparison
by Jakub Czapiga (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Caveh Jalali, Julius Werner, Yu-Ping Wu, Boris Mittelberg. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69762 ) Change subject: vboot: Fix hash digest size, padding and comparison ...................................................................... Patch Set 5: (2 comments) File src/ec/google/chromeec/vboot_storage.c: https://review.coreboot.org/c/coreboot/+/69762/comment/f4e0bdfb_55e62f4a PS2, Line 21: memset(data, 0, sizeof(data)); > With […] Oh, ok. I totally missed this. Thanks! File src/ec/google/chromeec/vboot_storage.c: https://review.coreboot.org/c/coreboot/+/69762/comment/83c602af_ac5dbb80 PS4, Line 21: data, sizeof(data) > `digest, digest_size`. `data` is not needed now. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Gerrit-Change-Number: 69762 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 14:23:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/ehl: Add MDIO operation to TSN GbE device
by Mario Scheithauer (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add MDIO operation to TSN GbE device ...................................................................... Patch Set 13: (2 comments) Patchset: PS13: Thanks all for reviewing this patch chain. File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/cdd9247c_99a0fca7 PS12, Line 104: (void *)(uintptr_t)gbe_tsn_res->base > I will change this from 'gbe_tsn_res' to 'res2mmio'. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 13 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 14:21:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/net/phy/m88e1512: Provide functionality to customize LED status
by build bot (Jenkins) (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/net/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 18: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164265): https://review.coreboot.org/c/coreboot/+/69386/comment/2178908b_86910b28 PS18, Line 14: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/… Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 18 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 14:19:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/ehl: Add MDIO operation to TSN GbE device
by Mario Scheithauer (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Mario Scheithauer, Angel Pons, Lean Sheng Tan. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69383 to look at the new patch set (#13). Change subject: soc/intel/ehl: Add MDIO operation to TSN GbE device ...................................................................... soc/intel/ehl: Add MDIO operation to TSN GbE device This patch refactors the MDIO access for the TSN GbE device by placing the MDIO read and write functions into mdio_bus_operations struct which is assigned to the .ops_mdio member of the PCI device struct. In this way the MDIO interface of the TSN GbE device is exposed and can be used by other drivers if needed. Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h M src/soc/intel/elkhartlake/tsn_gbe.c 2 files changed, 114 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/69383/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 13 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: sb/intel/i82801gx/lpc.c: Use post_code()
by Elyes Haouas (Code Review) 22 Nov '22

22 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69901 ) Change subject: sb/intel/i82801gx/lpc.c: Use post_code() ...................................................................... sb/intel/i82801gx/lpc.c: Use post_code() Use post_code() instead of 'outb(value, CONFIG_POST_IO_PORT)'. Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/lpc.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69901/1 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 05156f7..37095e84 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -446,7 +446,7 @@ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt); /* Indicate finalize step with post code */ - outb(POST_OS_BOOT, 0x80); + post_code(POST_OS_BOOT); } static const char *lpc_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/69901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Gerrit-Change-Number: 69901 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: src/acpi: Remove unnecessary space after casts
by Felix Held (Code Review) 22 Nov '22

22 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69818 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/acpi: Remove unnecessary space after casts ...................................................................... src/acpi: Remove unnecessary space after casts Change-Id: I3c077dee1c14e4aa45f837361daf799f02d32a29 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69818 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi.c M src/acpi/acpigen.c 2 files changed, 41 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 8d81284..877c47e 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -361,7 +361,7 @@ tcpa->platform_class = 0; tcpa->laml = tcpa_log_len; - tcpa->lasa = (uintptr_t) lasa; + tcpa->lasa = (uintptr_t)lasa; /* Calculate checksum. */ header->checksum = acpi_checksum((void *)tcpa, header->length); @@ -436,7 +436,7 @@ /* Fill the log area size and start address fields. */ tpm2->laml = tpm2_log_len; - tpm2->lasa = (uintptr_t) lasa; + tpm2->lasa = (uintptr_t)lasa; /* Calculate checksum. */ header->checksum = acpi_checksum((void *)tpm2, header->length); @@ -480,7 +480,7 @@ ssdt->asl_compiler_revision = asl_revision; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); /* Write object to declare coreboot tables */ acpi_ssdt_write_cbtable(); @@ -490,7 +490,7 @@ for (dev = all_devices; dev; dev = dev->next) if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt) dev->ops->acpi_fill_ssdt(dev); - current = (unsigned long) acpigen_get_current(); + current = (unsigned long)acpigen_get_current(); } /* (Re)calculate length and checksum. */ @@ -1070,7 +1070,7 @@ }; einj_smi->err_inj_cap = ACPI_EINJ_DEFAULT_CAP; - einj_smi->trigger_action_table = (u64) (uintptr_t)tat; + einj_smi->trigger_action_table = (u64)(uintptr_t)tat; for (i = 0; i < ACTION_COUNT; i++) printk(BIOS_DEBUG, "default_actions[%d].reg.addr is %llx\n", i, @@ -1248,7 +1248,7 @@ */ printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; + hpet = (acpi_hpet_t *)current; current += sizeof(acpi_hpet_t); current = ALIGN_UP(current, 16); acpi_create_hpet(hpet); @@ -1494,7 +1494,7 @@ case 0: /* MCE */ break; case 1: /* CMC */ - hen = (acpi_hest_hen_t *) (pos); + hen = (acpi_hest_hen_t *)(pos); memset(pos, 0, sizeof(acpi_hest_hen_t)); hen->type = 3; /* SCI? */ hen->length = sizeof(acpi_hest_hen_t); @@ -1587,7 +1587,7 @@ { acpi_header_t *header = &(fadt->header); - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); if (!header) return; @@ -1601,11 +1601,11 @@ header->asl_compiler_revision = asl_revision; fadt->FADT_MinorVersion = get_acpi_fadt_minor_version(); - fadt->firmware_ctrl = (unsigned long) facs; + fadt->firmware_ctrl = (unsigned long)facs; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; - fadt->dsdt = (unsigned long) dsdt; + fadt->dsdt = (unsigned long)dsdt; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; @@ -1625,7 +1625,7 @@ mainboard_fill_fadt(fadt); header->checksum = - acpi_checksum((void *) fadt, header->length); + acpi_checksum((void *)fadt, header->length); } void acpi_create_lpit(acpi_lpit_t *lpit) @@ -1746,7 +1746,7 @@ ssdt->asl_compiler_revision = asl_revision; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); /* Write object to declare coreboot tables */ acpi_ssdt_write_cbtable(); @@ -1795,19 +1795,19 @@ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; + rsdp = (acpi_rsdp_t *)current; coreboot_rsdp = (uintptr_t)rsdp; current += sizeof(acpi_rsdp_t); current = acpi_align_current(current); - rsdt = (acpi_rsdt_t *) current; + rsdt = (acpi_rsdt_t *)current; current += sizeof(acpi_rsdt_t); current = acpi_align_current(current); - xsdt = (acpi_xsdt_t *) current; + xsdt = (acpi_xsdt_t *)current; current += sizeof(acpi_xsdt_t); current = acpi_align_current(current); /* clear all table memory */ - memset((void *) start, 0, current - start); + memset((void *)start, 0, current - start); acpi_write_rsdp(rsdp, rsdt, xsdt, oem_id); acpi_write_rsdt(rsdt, oem_id, oem_table_id); @@ -1815,18 +1815,18 @@ printk(BIOS_DEBUG, "ACPI: * FACS\n"); current = ALIGN_UP(current, 64); - facs = (acpi_facs_t *) current; + facs = (acpi_facs_t *)current; current += sizeof(acpi_facs_t); current = acpi_align_current(current); acpi_create_facs(facs); printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; + dsdt = (acpi_header_t *)current; memcpy(dsdt, dsdt_file, sizeof(acpi_header_t)); if (dsdt->length >= sizeof(acpi_header_t)) { current += sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); if (CONFIG(ACPI_SOC_NVS)) acpi_fill_gnvs(); @@ -1836,7 +1836,7 @@ for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_inject_dsdt) dev->ops->acpi_inject_dsdt(dev); - current = (unsigned long) acpigen_get_current(); + current = (unsigned long)acpigen_get_current(); memcpy((char *)current, (char *)dsdt_file + sizeof(acpi_header_t), dsdt->length - sizeof(acpi_header_t)); @@ -1851,7 +1851,7 @@ current = acpi_align_current(current); printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; + fadt = (acpi_fadt_t *)current; current += sizeof(acpi_fadt_t); current = acpi_align_current(current); @@ -1877,7 +1877,7 @@ } printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; + mcfg = (acpi_mcfg_t *)current; acpi_create_mcfg(mcfg); if (mcfg->header.length > sizeof(acpi_mcfg_t)) { current += mcfg->header.length; @@ -1887,7 +1887,7 @@ if (CONFIG(TPM1)) { printk(BIOS_DEBUG, "ACPI: * TCPA\n"); - tcpa = (acpi_tcpa_t *) current; + tcpa = (acpi_tcpa_t *)current; acpi_create_tcpa(tcpa); if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { current += tcpa->header.length; @@ -1898,7 +1898,7 @@ if (CONFIG(TPM2)) { printk(BIOS_DEBUG, "ACPI: * TPM2\n"); - tpm2 = (acpi_tpm2_t *) current; + tpm2 = (acpi_tpm2_t *)current; acpi_create_tpm2(tpm2); if (tpm2->header.length >= sizeof(acpi_tpm2_t)) { current += tpm2->header.length; @@ -1921,7 +1921,7 @@ printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; + madt = (acpi_madt_t *)current; acpi_create_madt(madt); if (madt->header.length > sizeof(acpi_madt_t)) { current += madt->header.length; @@ -1933,7 +1933,7 @@ if (CONFIG(ACPI_BERT)) { void *region; size_t size; - bert = (acpi_bert_t *) current; + bert = (acpi_bert_t *)current; if (acpi_soc_get_bert_region(&region, &size) == CB_SUCCESS) { printk(BIOS_DEBUG, "ACPI: * BERT\n"); acpi_write_bert(bert, (uintptr_t)region, size); diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 85b49b2..7afb839 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -256,7 +256,7 @@ unsigned char *pathlen; acpigen_emit_byte(MULTI_NAME_PREFIX); acpigen_emit_byte(ZERO_OP); - pathlen = ((unsigned char *) acpigen_get_current()) - 1; + pathlen = ((unsigned char *)acpigen_get_current()) - 1; while (name[0] != '\0') { acpigen_emit_simple_namestring(name); @@ -399,7 +399,7 @@ acpigen_write_len_f(); snprintf(pscope, sizeof(pscope), - CONFIG_ACPI_CPU_STRING, (unsigned int) cpuindex); + CONFIG_ACPI_CPU_STRING, (unsigned int)cpuindex); acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_dword(pblock_addr); -- To view, visit https://review.coreboot.org/c/coreboot/+/69818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c077dee1c14e4aa45f837361daf799f02d32a29 Gerrit-Change-Number: 69818 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2022