coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/amd/*/fsp_m_params: rework local USB PHY table update
by Felix Held (Code Review) 23 Nov '22

23 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69896 ) Change subject: soc/amd/*/fsp_m_params: rework local USB PHY table update ...................................................................... soc/amd/*/fsp_m_params: rework local USB PHY table update Update the fields that need to be updated directly in the local static usb_phy_config struct instead of dereferencing the pointer written to the corresponding UPD field. This will allow updating the type of UPD field in a follow-up commit to enable 64 bit coreboot builds. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/glinda/fsp_m_params.c M src/soc/amd/mendocino/fsp_m_params.c M src/soc/amd/morgana/fsp_m_params.c 4 files changed, 31 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index ba2663a..f370331 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -153,10 +153,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } diff --git a/src/soc/amd/glinda/fsp_m_params.c b/src/soc/amd/glinda/fsp_m_params.c index 7e78287..d8de742 100644 --- a/src/soc/amd/glinda/fsp_m_params.c +++ b/src/soc/amd/glinda/fsp_m_params.c @@ -155,10 +155,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index ed8be66..8cbea5d 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -154,10 +154,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } diff --git a/src/soc/amd/morgana/fsp_m_params.c b/src/soc/amd/morgana/fsp_m_params.c index e1e8c26..0c51c1a 100644 --- a/src/soc/amd/morgana/fsp_m_params.c +++ b/src/soc/amd/morgana/fsp_m_params.c @@ -155,10 +155,10 @@ /* devicetree config is const, use local copy */ static struct usb_phy_config lcl_usb_phy; lcl_usb_phy = config->usb_phy; + lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; + lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); mcfg->usb_phy = &lcl_usb_phy; - mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; - mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; - mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d Gerrit-Change-Number: 69896 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/*/Makefile: fix readelf parameters to get bootblock size
by Felix Held (Code Review) 23 Nov '22

23 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69895 ) Change subject: soc/amd/*/Makefile: fix readelf parameters to get bootblock size ...................................................................... soc/amd/*/Makefile: fix readelf parameters to get bootblock size This ports forward part of commit df0968062622 ("soc/amd/picasso: Add support for 64bit builds") to the newer AMD SoCs. Use -Wl instead of -l to get the output format that the commands in the Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this change, readelf will split the output into two lines in case of a 64 bit coreboot build. This results in invalid amdcompress and amdfwtool command lines which will cause the amdfwtool call to fail with Error: BIOS binary destination and uncompressed size are required With the old readelf -l command we get this output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000 0x0000000000010000 0x0000000000010000 RWE 0x10 while we get the correct output in a 32 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20 With readelf -Wl we also get the expected output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10 TEST=This fixes the 64 bit build on Cezanne with some follow-up patches applied. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/morgana/Makefile.inc 4 files changed, 56 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 1f2bb6d..091e63f 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -141,8 +141,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index e00421d..4d1ba55 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -141,8 +141,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 92c75f8..ab709e6 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -142,8 +142,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index a88e1a5..44a92eb 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -141,8 +141,8 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -- To view, visit https://review.coreboot.org/c/coreboot/+/69895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Gerrit-Change-Number: 69895 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: Revert "mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE"
by Nick Vaccaro (Code Review) 23 Nov '22

23 Nov '22

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69919 ) Change subject: Revert "mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE" ...................................................................... Revert "mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE" This reverts commit 7203aa5c2dcb90e50356305cabbe062bd4f4dc76. BUG=b:260138434 TEST=None Cq-Depend: chrome-internal:5126951, chromium:4049177 Change-Id: Ieaa44a33a7c65d384581b5145821b449783ca3fa Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69919 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index bdd278e..71ea005 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -78,7 +78,6 @@ select SOC_INTEL_COMMON_BLOCK_IPU select CHROMEOS_WIFI_SAR if CHROMEOS select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG - select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" -- To view, visit https://review.coreboot.org/c/coreboot/+/69919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa44a33a7c65d384581b5145821b449783ca3fa Gerrit-Change-Number: 69919 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: Revert "mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE"
by Subrata Banik (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: David Wu, Tarun Tuli, Nick Vaccaro, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69919 ) Change subject: Revert "mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE" ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa44a33a7c65d384581b5145821b449783ca3fa Gerrit-Change-Number: 69919 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 19:33:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/testing: Fully clean all but the standard GCC build
by Martin L Roth (Code Review) 23 Nov '22

23 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69954 ) Change subject: util/testing: Fully clean all but the standard GCC build ...................................................................... util/testing: Fully clean all but the standard GCC build We don't currently use the artifacts from the Clang or CrOS GCC builds, so don't bother saving them. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I69fe803e4b4213a199d0b76089da443aa769aa92 --- M util/testing/Makefile.inc 1 file changed, 18 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/69954/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 7cf2c8d..3614542 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -76,7 +76,7 @@ lint lint-stable lint-extended: util/lint/lint $@ -ABUILD_OPTIONS=--blobs --junit --cpus $(CPUS) --clean-somewhat --payloads $(JENKINS_PAYLOAD) +ABUILD_OPTIONS=--blobs --junit --cpus $(CPUS) --payloads $(JENKINS_PAYLOAD) ABUILD_OPTIONS+=$(if $(V),--verbose,) ABUILD_OPTIONS+=$(if $(JENKINS_NOCCACHE),,--ccache) ABUILD_OPTIONS+=$(JENKINS_ABUILD_OPT) @@ -117,12 +117,12 @@ test-abuild: NAME=scanbuild; SCANBUILD_ARGS='-k -plist-html -maxloop 10' util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -scan-build --target EMULATION_QEMU_X86_Q35 --exitcode --name $${NAME} ifneq ($(JENKINS_SKIP_GCC_TESTS),y) - NAME=gcc-chromeos; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -x --name $${NAME} - NAME=gcc; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) --name $${NAME} + NAME=gcc-chromeos; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -x --name $${NAME} --clean + NAME=gcc; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) --name $${NAME} --clean-somewhat endif ifneq ($(JENKINS_SKIP_CLANG_TESTS),y) - NAME=clang-chromeos; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -L -x --name $${NAME} - NAME=clang; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -L --name $${NAME} + NAME=clang-chromeos; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -L -x --name $${NAME} --clean + NAME=clang; util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/$${NAME} $(ABUILD_OPTIONS) -L --name $${NAME} --clean endif test-payloads: -- To view, visit https://review.coreboot.org/c/coreboot/+/69954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69fe803e4b4213a199d0b76089da443aa769aa92 Gerrit-Change-Number: 69954 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board conf...
by Michał Kopeć (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69953 to look at the new patch set (#2). Change subject: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable ...................................................................... soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using a HECI message that needs to be sent before EOP. Make the option configurable to allow soft ME disable on alderlake. Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/cse/Kconfig 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/69953/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Gerrit-Change-Number: 69953 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board conf...
by build bot (Jenkins) (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69953 ) Change subject: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164394): https://review.coreboot.org/c/coreboot/+/69953/comment/5f7bd16c_9ab100ff PS1, Line 12: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164394): https://review.coreboot.org/c/coreboot/+/69953/comment/4e342b68_b78f8a48 PS1, Line 13: Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Gerrit-Change-Number: 69953 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 18:26:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board conf...
by Michał Kopeć (Code Review) 23 Nov '22

23 Nov '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69953 ) Change subject: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable ...................................................................... soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using a HECI message that needs to be sent before EOP. Make the option configurable to allow soft ME disable on alderlake. Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/cse/Kconfig 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/69953/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132..5b624d8 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -117,7 +117,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE @@ -459,6 +458,9 @@ endchoice +config SOC_INTEL_CSE_SEND_EOP_EARLY + default y + if STITCH_ME_BIN config CSE_BPDT_VERSION diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55a2b49..f728c3f 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -46,7 +46,7 @@ to make `HECI1` device disable using private configuration register (PCR) write. config SOC_INTEL_CSE_SEND_EOP_EARLY - bool + bool "CSE send EOP early" depends on SOC_INTEL_COMMON_BLOCK_CSE help Use this config to send End Of Post (EOP) earlier through SoC code in order to -- To view, visit https://review.coreboot.org/c/coreboot/+/69953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Gerrit-Change-Number: 69953 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/kconfig: Fix patch to be compatible with quilt
by Nicholas Chin (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Martin L Roth, Fred Reitberger. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69863 ) Change subject: util/kconfig: Fix patch to be compatible with quilt ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > yes, that code comment nicely explains why the code differs from upstream Kconfig Acknowledged. I created a new patch (CB:69952) to add that comment, as it's logically different change from the this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/69863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595 Gerrit-Change-Number: 69863 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 17:29:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/kconfig: Add comment explaining difference from upstream
by Nicholas Chin (Code Review) 23 Nov '22

23 Nov '22

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69952 ) Change subject: util/kconfig: Add comment explaining difference from upstream ...................................................................... util/kconfig: Add comment explaining difference from upstream coreboot adds a patch on top of upstream Kconfig which allows the generated Kconfig dependency files to be placed in a separate directory than the autoconfig files based on the KCONFIG_SPLITCONFIG variable. Add a comment to explain this difference. Change-Id: Ief38ab84f852ff24f896ec8bbf094aa737a172d9 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/kconfig/confdata.c M util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/69952/1 diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 3da9e8b..1300ab6 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -1035,6 +1035,11 @@ struct symbol *sym; int res, i; + /* + * Upstream Kconfig sets depfile_path based on the directory + * prefix of the autoconfig path, but coreboot overrides this + * using the KCONFIG_SPLITCONFIG environment variable + */ strcpy(depfile_path, conf_get_autobase_name()); depfile_prefix_len = strlen(depfile_path); diff --git a/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch b/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch index b4db86e..869adef 100644 --- a/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch +++ b/util/kconfig/patches/0014-util-kconfig-Move-Kconfig-deps-back-into-build-confi.patch @@ -35,7 +35,7 @@ static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p) { char *p2; -@@ -1024,19 +1031,14 @@ static int conf_write_autoconf_cmd(const +@@ -1024,19 +1031,19 @@ static int conf_write_autoconf_cmd(const static int conf_touch_deps(void) { @@ -52,6 +52,11 @@ - - strncpy(depfile_path, name, depfile_prefix_len); - depfile_path[depfile_prefix_len] = 0; ++ /* ++ * Upstream Kconfig sets depfile_path based on the directory ++ * prefix of the autoconfig path, but coreboot overrides this ++ * using the KCONFIG_SPLITCONFIG environment variable ++ */ + strcpy(depfile_path, conf_get_autobase_name()); + depfile_prefix_len = strlen(depfile_path); -- To view, visit https://review.coreboot.org/c/coreboot/+/69952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief38ab84f852ff24f896ec8bbf094aa737a172d9 Gerrit-Change-Number: 69952 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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