coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: util/lint: Ignore fmd files when evaluating Kconfig symbols
by Elyes Haouas (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Martin L Roth, Martin Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69918 ) Change subject: util/lint: Ignore fmd files when evaluating Kconfig symbols ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310 Gerrit-Change-Number: 69918 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 16:54:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: util/lint: Ignore fmd files when evaluating Kconfig symbols
by Arthur Heymans (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Martin L Roth, Martin Roth. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69918 ) Change subject: util/lint: Ignore fmd files when evaluating Kconfig symbols ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310 Gerrit-Change-Number: 69918 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 16:48:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/mediatek: Add error handling for dptx_get_edid()
by Felix Held (Code Review) 23 Nov '22

23 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69858 ) Change subject: soc/mediatek: Add error handling for dptx_get_edid() ...................................................................... soc/mediatek: Add error handling for dptx_get_edid() Skip eDP initialization when we failed to get EDID. This prevents the PLL assertion in dp_intf_config() if the display could not be initialized properly. BUG=b:233720142 TEST=boot to depthcharge on MT8188 EVB. Change-Id: I0fd672b175feb9b813c1d9ec4140e4273079ff07 Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69858 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/dp/dptx.c 1 file changed, 26 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/dp/dptx.c b/src/soc/mediatek/common/dp/dptx.c index f2c0905..08d288a 100644 --- a/src/soc/mediatek/common/dp/dptx.c +++ b/src/soc/mediatek/common/dp/dptx.c @@ -1111,7 +1111,10 @@ dptx_check_sinkcap(&mtk_edp); - dptx_get_edid(&mtk_edp, edid); + if (dptx_get_edid(&mtk_edp, edid) != 0) { + printk(BIOS_ERR, "Failed to get EDID\n"); + return -1; + } dptx_set_trainingstart(&mtk_edp); dp_intf_config(edid); -- To view, visit https://review.coreboot.org/c/coreboot/+/69858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd672b175feb9b813c1d9ec4140e4273079ff07 Gerrit-Change-Number: 69858 Gerrit-PatchSet: 5 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: src/soc/qualcomm: Remove unnecessary space after casts
by Felix Held (Code Review) 23 Nov '22

23 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69807 ) Change subject: src/soc/qualcomm: Remove unnecessary space after casts ...................................................................... src/soc/qualcomm: Remove unnecessary space after casts Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69807 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/common/include/soc/qspi_common.h M src/soc/qualcomm/common/qspi.c M src/soc/qualcomm/common/qupv3_config.c M src/soc/qualcomm/common/usb/qusb_phy.c M src/soc/qualcomm/common/usb/snps_usb_phy.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/sc7280/pcie.c 10 files changed, 50 insertions(+), 37 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/qualcomm/common/include/soc/qspi_common.h b/src/soc/qualcomm/common/include/soc/qspi_common.h index 6a1496a..a0c8e46 100644 --- a/src/soc/qualcomm/common/include/soc/qspi_common.h +++ b/src/soc/qualcomm/common/include/soc/qspi_common.h @@ -30,7 +30,7 @@ }; check_member(qcom_qspi_regs, rd_fifo, 0x50); -static struct qcom_qspi_regs * const qcom_qspi = (void *) QSPI_BASE; +static struct qcom_qspi_regs * const qcom_qspi = (void *)QSPI_BASE; // MSTR_CONFIG register diff --git a/src/soc/qualcomm/common/qspi.c b/src/soc/qualcomm/common/qspi.c index 1c345cc..eb0c062 100644 --- a/src/soc/qualcomm/common/qspi.c +++ b/src/soc/qualcomm/common/qspi.c @@ -66,7 +66,7 @@ uint32_t mstr_int_status; write32(&qcom_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&qcom_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + write32(&qcom_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t)chain); while (1) { mstr_int_status = read32(&qcom_qspi->mstr_int_sts); @@ -87,15 +87,15 @@ if (desc->direction == MASTER_READ) { if (desc->bounce_length == 0) dcache_invalidate_by_mva( - (void *)(uintptr_t) desc->data_address, + (void *)(uintptr_t)desc->data_address, desc->length); else { - src = (void *)(uintptr_t) desc->bounce_src; - dst = (void *)(uintptr_t) desc->bounce_dst; + src = (void *)(uintptr_t)desc->bounce_src; + dst = (void *)(uintptr_t)desc->bounce_dst; memcpy(dst, src, desc->bounce_length); } } - desc = (void *)(uintptr_t) desc->next_descriptor; + desc = (void *)(uintptr_t)desc->next_descriptor; } curr_desc_idx = -1; } @@ -112,7 +112,7 @@ index = ++curr_desc_idx; next = &dma->descriptors[index]; - next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; + next->data_address = (uint32_t)(uintptr_t)dma->buffers[index]; next->next_descriptor = 0; next->direction = MASTER_READ; @@ -131,7 +131,7 @@ next->bounce_length = 0; if (current) - current->next_descriptor = (uint32_t)(uintptr_t) next; + current->next_descriptor = (uint32_t)(uintptr_t)next; return next; } @@ -164,13 +164,13 @@ desc = allocate_descriptor(); desc->direction = write; desc->multi_io_mode = data_mode; - ptr = (void *)(uintptr_t) desc->data_address; + ptr = (void *)(uintptr_t)desc->data_address; if (write) { memcpy(ptr, data, data_bytes); } else { - desc->bounce_src = (uint32_t)(uintptr_t) ptr; - desc->bounce_dst = (uint32_t)(uintptr_t) data; + desc->bounce_src = (uint32_t)(uintptr_t)ptr; + desc->bounce_dst = (uint32_t)(uintptr_t)data; desc->bounce_length = data_bytes; } @@ -185,7 +185,7 @@ desc = allocate_descriptor(); desc->direction = write; desc->multi_io_mode = data_mode; - desc->data_address = (uint32_t)(uintptr_t) data; + desc->data_address = (uint32_t)(uintptr_t)data; desc->length = data_bytes; if (write) @@ -291,7 +291,7 @@ return -1; } - queue_data((uint8_t *) (out_bytes ? dout : din), + queue_data((uint8_t *)(out_bytes ? dout : din), in_bytes | out_bytes, mode, !!out_bytes); flush_chain(); diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c index b243fdd..919c11b 100644 --- a/src/soc/qualcomm/common/qupv3_config.c +++ b/src/soc/qualcomm/common/qupv3_config.c @@ -188,7 +188,7 @@ struct gsi_fw_hdr *gsi_hdr; struct gsi_fw_iep *fwIep; struct gsi_fw_iram *fwIRam; - struct gsi_regs *regs = (struct gsi_regs *)(uintptr_t) addr; + struct gsi_regs *regs = (struct gsi_regs *)(uintptr_t)addr; static const char * const filename = "fallback/gsi_fw"; /* Assign firmware header base */ @@ -241,7 +241,7 @@ { struct qupv3_common_reg *qupv3_common; /* HPG section 3.1.2 */ - qupv3_common = (struct qupv3_common_reg *)(uintptr_t) addr; + qupv3_common = (struct qupv3_common_reg *)(uintptr_t)addr; setbits32(&qupv3_common->qupv3_common_cfg_reg, QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK); diff --git a/src/soc/qualcomm/common/usb/qusb_phy.c b/src/soc/qualcomm/common/usb/qusb_phy.c index 494f7cd..ddb087f 100644 --- a/src/soc/qualcomm/common/usb/qusb_phy.c +++ b/src/soc/qualcomm/common/usb/qusb_phy.c @@ -96,7 +96,7 @@ hs_phy_reg = &qusb_phy; - hs_phy_reg->board_data = (struct usb_board_data *) board_data; + hs_phy_reg->board_data = (struct usb_board_data *)board_data; /* PWR_CTRL: set the power down bit to disable the PHY */ diff --git a/src/soc/qualcomm/common/usb/snps_usb_phy.c b/src/soc/qualcomm/common/usb/snps_usb_phy.c index 1b2d869..d04694b 100644 --- a/src/soc/qualcomm/common/usb/snps_usb_phy.c +++ b/src/soc/qualcomm/common/usb/snps_usb_phy.c @@ -36,7 +36,7 @@ void hs_usb_phy_init(void *board_data) { struct usb_board_data *override_data = - (struct usb_board_data *) board_data; + (struct usb_board_data *)board_data; clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN); diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 60e4f0d..ef19053 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -31,7 +31,7 @@ (blob_mbn->mbn_total_size > blob_size)) return NULL; - blob_dest = (void *) blob_mbn->mbn_destination; + blob_dest = (void *)blob_mbn->mbn_destination; if (blob_mbn->mbn_destination) { /* Copy the blob to the appropriate memory location. */ diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 0893dfc..ab8f530 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -591,7 +591,7 @@ write_force_cs(slave, 1); if (dout != NULL) { - ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + ret = blsp_spi_write(ds, txp, (unsigned int)out_bytes); if (ret != SUCCESS) goto out; } diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 15068a5..851ee81 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -27,7 +27,7 @@ (blob_mbn->mbn_total_size > blob_size)) return NULL; - blob_dest = (void *) blob_mbn->mbn_destination; + blob_dest = (void *)blob_mbn->mbn_destination; if (blob_mbn->mbn_destination) { /* Copy the blob to the appropriate memory location. */ memcpy(blob_dest, blob_mbn + 1, blob_mbn->mbn_total_size); @@ -99,7 +99,7 @@ return; } - load_addr = (u32) load_ipq_blob("rpm.mbn"); + load_addr = (u32)load_ipq_blob("rpm.mbn"); if (!load_addr) die("could not find or map RPM code\n"); diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index e212b84..4863188 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -660,7 +660,7 @@ return ret; if (dout != NULL) { - ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + ret = blsp_spi_write(ds, txp, (unsigned int)out_bytes); if (ret != SUCCESS) goto out; } diff --git a/src/soc/qualcomm/sc7280/pcie.c b/src/soc/qualcomm/sc7280/pcie.c index 28d520c..edc73b0 100644 --- a/src/soc/qualcomm/sc7280/pcie.c +++ b/src/soc/qualcomm/sc7280/pcie.c @@ -140,13 +140,13 @@ }; static pcie_cntlr_cfg_t pcie_host = { - .parf = (void *) PCIE1_PCIE_PARF, - .dbi_base = (void *) PCIE1_GEN3X2_PCIE_DBI, - .elbi = (void *) PCIE1_GEN3X2_PCIE_ELBI, - .atu_base = (void *) PCIE1_GEN3X2_DWC_PCIE_DM_IATU, - .cfg_base = (void *) PCIE1_GEN3X2_PCIE_DBI + PCIE_EP_CONF_OFFSET, - .pcie_bcr = (void *) PCIE1_BCR, - .qmp_phy_bcr = (void *) GCC_PCIE_1_PHY_BCR, + .parf = (void *)PCIE1_PCIE_PARF, + .dbi_base = (void *)PCIE1_GEN3X2_PCIE_DBI, + .elbi = (void *)PCIE1_GEN3X2_PCIE_ELBI, + .atu_base = (void *)PCIE1_GEN3X2_DWC_PCIE_DM_IATU, + .cfg_base = (void *)PCIE1_GEN3X2_PCIE_DBI + PCIE_EP_CONF_OFFSET, + .pcie_bcr = (void *)PCIE1_BCR, + .qmp_phy_bcr = (void *)GCC_PCIE_1_PHY_BCR, .lanes = PCIE_3x2_NUM_LANES, .cfg_size = PCIE_EP_CONF_SIZE, .perst = GPIO(2), @@ -160,14 +160,14 @@ }; static pcie_qmp_phy_cfg_t pcie1_qmp_phy_3x2 = { - .qmp_phy_base = (void *) PCIE_1_QMP_PHY, - .serdes = (void *) PCE1_QPHY_SERDES, - .tx0 = (void *) PCE1_QPHY_TX0, - .rx0 = (void *) PCE1_QPHY_RX0, - .pcs = (void *) PCIE1_QMP_PHY_PCS_COM, - .tx1 = (void *) PCE1_QPHY_TX1, - .rx1 = (void *) PCE1_QPHY_RX1, - .pcs_misc = (void *) PCE1_QPHY_PCS_MISC, + .qmp_phy_base = (void *)PCIE_1_QMP_PHY, + .serdes = (void *)PCE1_QPHY_SERDES, + .tx0 = (void *)PCE1_QPHY_TX0, + .rx0 = (void *)PCE1_QPHY_RX0, + .pcs = (void *)PCIE1_QMP_PHY_PCS_COM, + .tx1 = (void *)PCE1_QPHY_TX1, + .rx1 = (void *)PCE1_QPHY_RX1, + .pcs_misc = (void *)PCE1_QPHY_PCS_MISC, .serdes_tbl = sc7280_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_serdes_tbl), .tx_tbl = sc7280_qmp_pcie_tx_tbl, -- To view, visit https://review.coreboot.org/c/coreboot/+/69807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6 Gerrit-Change-Number: 69807 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/system76: Reset Realtek codec before configuring
by Jeremy Soller (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tim Crawford, Paul Menzel. Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66918 ) Change subject: mb/system76: Reset Realtek codec before configuring ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61 Gerrit-Change-Number: 66918 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 23 Nov 2022 16:21:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: util/kconfig: Fix patch to be compatible with quilt
by Fred Reitberger (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Martin L Roth, Nicholas Chin. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69863 ) Change subject: util/kconfig: Fix patch to be compatible with quilt ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I'm assuming you're referring to this comment? https://review.coreboot. […] yes, that code comment nicely explains why the code differs from upstream Kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/69863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595 Gerrit-Change-Number: 69863 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 16:21:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/octopus/variants/phaser: Implement variant_memory_sku()
by Eric Lai (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Jamie Chen, Derek Huang, Stanley Wu, Marco Chen. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69925 ) Change subject: mb/google/octopus/variants/phaser: Implement variant_memory_sku() ...................................................................... Patch Set 3: (3 comments) File src/mainboard/google/octopus/variants/phaser/memory.c: https://review.coreboot.org/c/coreboot/+/69925/comment/d3c254a1_cd91287b PS3, Line 17: extra tab. https://review.coreboot.org/c/coreboot/+/69925/comment/a0c22d6c_3ef7e841 PS3, Line 18: return (rt == 3) ? 1 : rt; // If RAM ID = 3, return 1 > Thanks for the suggestion. But there don`t have specific board_id define for ram_id=3 case. […] Since I can't access the issue, leave this to the SIE. I am fine here. https://review.coreboot.org/c/coreboot/+/69925/comment/54ea374c_0108a4c8 PS3, Line 18: extra tab -- To view, visit https://review.coreboot.org/c/coreboot/+/69925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 Gerrit-Change-Number: 69925 Gerrit-PatchSet: 3 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 15:52:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Comment-In-Reply-To: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: [RFC] Pull libgfxinit in early romstage
by Tarun Tuli (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Nico Huber, Martin L Roth, Jérémy Compostella, Angel Pons, Arthur Heymans, Kyösti Mälkki, Andrey Petrov. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69757 ) Change subject: [RFC] Pull libgfxinit in early romstage ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb: https://review.coreboot.org/c/coreboot/+/69757/comment/2ba27232_020baf0b PS5, Line 130: device ref igpu on I think we should deal with enablement (in the cb and Kconfigs/etc) on a individual variant level instead of the entire baseboards. e.g. not all variants will necessarily want to include this in their builds from day 1. -- To view, visit https://review.coreboot.org/c/coreboot/+/69757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Gerrit-Change-Number: 69757 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 15:48:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/adl/acpi: add FSPI to DSDT
by Tarun Tuli (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Eran Mitrani, Subrata Banik. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69920 ) Change subject: soc/intel/adl/acpi: add FSPI to DSDT ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Gerrit-Change-Number: 69920 Gerrit-PatchSet: 2 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 15:41:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: sb/intel/i82801gx/lpc.c: Use post_code()
by Felix Held (Code Review) 23 Nov '22

23 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69901 ) Change subject: sb/intel/i82801gx/lpc.c: Use post_code() ...................................................................... sb/intel/i82801gx/lpc.c: Use post_code() Use post_code() instead of 'outb(value, CONFIG_POST_IO_PORT)'. Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69901 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/southbridge/intel/i82801gx/lpc.c 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ec0df27..d8c9776 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -445,7 +445,7 @@ outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT); /* Indicate finalize step with post code */ - outb(POST_OS_BOOT, 0x80); + post_code(POST_OS_BOOT); } static const char *lpc_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/69901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Gerrit-Change-Number: 69901 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022