coreboot-gerrit November 2022

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by Tim Van Patten (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Eric Peers, Jason Glenesk, Dtrain Hsu, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 63: Code-Review+1 (7 comments) File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/ac79e120_aa783e54 PS53, Line 42: #if CONFIG(FEATURE_DYNAMIC_DPTC) : #include <soc/amd/common/acpi/DTTS.asl> : #endif > Hi Tim […] Done File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/dafa53c3_3eb551cb PS59, Line 22: /* If _SB.DTTS is not present, DTTS is not enabled. */ : If (CondRefOf (\_SB.DTTS)) : { : \_SB.DTTS() : Return (Zero) : } > Thanks your suggestion. […] Done https://review.coreboot.org/c/coreboot/+/68471/comment/d918f8ef_b4f76060 PS59, Line 52: > Thanks your suggestion. […] Done File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/2534e5a6_81fe01d1 PS63, Line 21: nit: remove extra newline File src/soc/amd/common/acpi/dtts.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/10c6f769_3217c8e4 PS63, Line 9: PRTN,7 nit: add whitespace after `,` https://review.coreboot.org/c/coreboot/+/68471/comment/b166ac70_57756ebc PS63, Line 13: //Set nit: whitespace after `//` This applies to the rest of the comments in this file too. https://review.coreboot.org/c/coreboot/+/68471/comment/46c62891_ee2c1607 PS63, Line 13: SUT nit: device -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 63 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 24 Nov 2022 00:31:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by Tim Van Patten (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Chris Wang, Martin Roth, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... Patch Set 31: (1 comment) File src/soc/amd/mendocino/root_complex.c: https://review.coreboot.org/c/coreboot/+/68649/comment/2098ae39_e2548f75 PS16, Line 393: #else > since the below settings will apply to dptc parameters, it's better to follow AMD IRM, or you have your own setting that needs to apply to. I don't fully understand what this means. What is "AMD IRM"? However, regarding: > There's no other STT setting that will be changed via DPTC, so those values will keep the value you set to default in devtree. My point is that the values added to `DPTC_INPUTS()` are **not** defined in the device tree for all other Mendocino boards. Only `winterhold/overridetree.cb` has the values defined, so they need to be added to `baseboard/devicetree.cb` (once https://review.coreboot.org/c/coreboot/+/69904 lands), so every Mendocino board has valid values. -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 31 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 24 Nov 2022 00:22:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Set Package Power Parameters
by Tim Van Patten (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Frank Wu, John Su, Jason Nien, Matt DeVillier, Chris Wang, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69565 ) Change subject: mb/google/skyrim/var/frostflow: Set Package Power Parameters ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/skyrim/variants/frostflow/overridetree.cb: https://review.coreboot.org/c/coreboot/+/69565/comment/bf2aa1e8_817cbac8 PS4, Line 10: register "stapm_time_constant_s" = "200" > Hi Tim, […] Ah, right, that's what I was missing. I wonder if it would make more sense to move the values from `skyrim/overridetree.cb` into `baseboard/devicetree.cb`, since they all need them defined anyway. That would avoid the duplication. CL is available here: https://review.coreboot.org/c/coreboot/+/69904 -- To view, visit https://review.coreboot.org/c/coreboot/+/69565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a Gerrit-Change-Number: 69565 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 00:15:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/adl/acpi: add FSPI to DSDT
by Eric Lai (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Eran Mitrani, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69920 ) Change subject: soc/intel/adl/acpi: add FSPI to DSDT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Gerrit-Change-Number: 69920 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 00:06:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/gladios: Update gpio table
by Felix Held (Code Review) 24 Nov '22

24 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69463 ) Change subject: mb/google/brya/var/gladios: Update gpio table ...................................................................... mb/google/brya/var/gladios: Update gpio table Based on the latest schematic to update the gpio table. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69463 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/brya/variants/gladios/Makefile.inc A src/mainboard/google/brya/variants/gladios/gpio.c 2 files changed, 185 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/gladios/Makefile.inc b/src/mainboard/google/brya/variants/gladios/Makefile.inc new file mode 100644 index 0000000..d38141c --- /dev/null +++ b/src/mainboard/google/brya/variants/gladios/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/gladios/gpio.c b/src/mainboard/google/brya/variants/gladios/gpio.c new file mode 100644 index 0000000..1dfef5c --- /dev/null +++ b/src/mainboard/google/brya/variants/gladios/gpio.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> NC */ + PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG), + /* A15 : USB_OC2# ==> NC */ + PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG), + /* A18 : DDSP_HPDB ==> HDMIB_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), + + /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> GPI */ + PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E14 : DDSP_HPDA ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* H19 : SRCCLKREQ4# ==> CLKREQ_4 */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H21 : IMGCLKOUT2 ==> EMMC_PE_WAKE_ODL */ + PAD_CFG_GPO(GPP_H21, 1, DEEP), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f Gerrit-Change-Number: 69463 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/var/gaelin: Configure devicetree settings
by Felix Held (Code Review) 24 Nov '22

24 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69137 ) Change subject: mb/google/brya/var/gaelin: Configure devicetree settings ...................................................................... mb/google/brya/var/gaelin: Configure devicetree settings Override devicetree configuration based on the latest gaelin schematic. BUG=b:249000573, b:254375472 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69137 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/gaelin/overridetree.cb 1 file changed, 222 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Raymond Chung: Looks good to me, but someone else must approve Derek Huang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index caa874b..dcb695f 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -1,7 +1,207 @@ chip soc/intel/alderlake + + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + # Enable eDP in Port A + register "ddi_portA_config" = "1" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + device ref pcie_rp5 on + # Enable PCIE 5 using clk 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end #PCIE5 WLAN + device ref pcie_rp7 on + # Enable PCIE 7 using clk 6 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/net + register "customized_leds" = "0x0843" + register "wake" = "GPE0_DW0_07" #GPP_A7 + register "device_index" = "0" + device pci 00.0 on end + end + end #PCIE7 RTL8111K Ethernet NIC + device ref pcie_rp8 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256 Gerrit-Change-Number: 69137 Gerrit-PatchSet: 7 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bruce Chiang <brucechiang(a)msi.corp-partner.google.com> Gerrit-CC: Eason Chang <easonchang(a)msi.corp-partner.google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/google/brya/var/gladios: Update devicetree setting
by Felix Held (Code Review) 24 Nov '22

24 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69423 ) Change subject: mb/google/brya/var/gladios: Update devicetree setting ...................................................................... mb/google/brya/var/gladios: Update devicetree setting Update devicetree setting per the schematic. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69423 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/gladios/overridetree.cb 1 file changed, 327 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 4f2c04a..ae099c3 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -1,6 +1,313 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | NC | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | NC | + #| I2C5 | NC | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A1(DCI) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A3 + + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # USB TYPE C + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" + register "enable_aspm_l1_2" = "1" + device pci 00.0 on end + end + end # RTL8111 Ethernet NIC + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref pcie_rp12 on + # Enable PCIE eMMC bridge 12 using clk 4 + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + }" + end #PCIE12 EMMC + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3 Gerrit-Change-Number: 69423 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: ec/google/chromeec: Refresh ec_commands.h
by Caveh Jalali (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Nick Vaccaro. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69375 ) Change subject: ec/google/chromeec: Refresh ec_commands.h ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/69375/comment/fab2c8e3_bb0dac7d PS4, Line 116: #define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ : #define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ : #define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ : #define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ : #define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ : #define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ : #define EC_LPC_CMDR_SMI BIT(6) /* S > Did you remove the alignment on purpose? It's harder to read without the alignment. we run all files in the EC repo through clang format now, so that's where these formatting changes originated. -- To view, visit https://review.coreboot.org/c/coreboot/+/69375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72620c4365fb1d53bb8161ecbbc041a32614e1ea Gerrit-Change-Number: 69375 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 21:31:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/adl/acpi: add FSPI to DSDT
by Eran Mitrani (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Subrata Banik, Eric Lai. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69920 ) Change subject: soc/intel/adl/acpi: add FSPI to DSDT ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69920/comment/aceef5e3_2419b5ea PS2, Line 10: SHA > commit Done https://review.coreboot.org/c/coreboot/+/69920/comment/8d3cd4d9_3030bfbf PS2, Line 15: i > chipset. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Gerrit-Change-Number: 69920 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 20:36:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/adl/acpi: add FSPI to DSDT
by Eran Mitrani (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Eran Mitrani, Subrata Banik. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69920 to look at the new patch set (#3). Change subject: soc/intel/adl/acpi: add FSPI to DSDT ...................................................................... soc/intel/adl/acpi: add FSPI to DSDT A previous CL ("Add missing ACPI device path names", commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors from the Kernel on Brya devices (see Tim's comment on patchset 8): > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI FSPI is defined in src/soc/intel/alderlake/chipset.cb: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. TEST=Built and tested on brya by verifying the error is gone. BUG=b:231582182 Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c --- M src/soc/intel/alderlake/acpi/serialio.asl 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69920/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Gerrit-Change-Number: 69920 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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