coreboot-gerrit November 2022

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[M] Change in coreboot[master]: soc/amd: Define post codes
by Felix Held (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69867 ) Change subject: soc/amd: Define post codes ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Gerrit-Change-Number: 69867 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 14:21:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/fsp_m_params: rework local USB PHY table update
by Fred Reitberger (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69896 ) Change subject: soc/amd/*/fsp_m_params: rework local USB PHY table update ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d Gerrit-Change-Number: 69896 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Nov 2022 14:19:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/*/Makefile: fix readelf parameters to get bootblock size
by Fred Reitberger (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69895 ) Change subject: soc/amd/*/Makefile: fix readelf parameters to get bootblock size ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Gerrit-Change-Number: 69895 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Nov 2022 14:18:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add Vrm setting for SMT
by Felix Held (Code Review) 23 Nov '22

23 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69830 ) Change subject: mb/google/skyrim/var/winterhold: Add Vrm setting for SMT ...................................................................... mb/google/skyrim/var/winterhold: Add Vrm setting for SMT All parameters of DPTC_INPUT() need to be configured on devicetree when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without configurations on devicetree would be 0 when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document #57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA and vrm_soc_current_limit_mA on devicetree with thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoidany thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:258572474, b:248976976, b:259167917, b:257394883 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 2078df8..f0c04ab 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -26,6 +26,14 @@ register "stt_error_coeff" = "0x21" register "stt_error_rate_coefficient" = "0xCCD" + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + # Throttle (e.g., Low/No Battery) + register "vrm_current_limit_throttle_mA" = "20000" + register "vrm_maximum_current_limit_throttle_mA" = "20000" + register "vrm_soc_current_limit_throttle_mA" = "10000" + device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller -- To view, visit https://review.coreboot.org/c/coreboot/+/69830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680 Gerrit-Change-Number: 69830 Gerrit-PatchSet: 10 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/wifi, mb/google: Rename is_untrusted to add_acpi_dma_property
by Kapil Porwal (Code Review) 23 Nov '22

23 Nov '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69937 ) Change subject: drivers/wifi, mb/google: Rename is_untrusted to add_acpi_dma_property ...................................................................... drivers/wifi, mb/google: Rename is_untrusted to add_acpi_dma_property Rename is_untrusted to add_acpi_dma_property. BUG=b:259716145 TEST=Verified that the _DSD object is still present in the SSDT. Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696 --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb M src/mainboard/google/brya/variants/joxer/overridetree.cb M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/pujjo/overridetree.cb M src/mainboard/google/brya/variants/xivu/overridetree.cb M src/mainboard/google/brya/variants/yaviks/overridetree.cb M src/mainboard/google/rex/variants/rex0/overridetree.cb 12 files changed, 27 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/69937/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 869b92a..57b7f5f 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -522,7 +522,7 @@ acpigen_write_PRW(config->wake, ACPI_S3); /* Add _DSD for DmaProperty property. */ - if (config->is_untrusted) { + if (config->add_acpi_dma_property) { struct acpi_dp *dsd, *pkg; dsd = acpi_dp_new_table("_DSD"); diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h index 56a4afc..2729a35 100644 --- a/src/drivers/wifi/generic/chip.h +++ b/src/drivers/wifi/generic/chip.h @@ -11,7 +11,7 @@ unsigned int wake; /* When set to true, this will add a _DSD which contains a single property, `DmaProperty`, set to 1, under the ACPI Device. */ - bool is_untrusted; + bool add_acpi_dma_property; /* * Applicable for Intel chipsets that use CNVi WiFi only. Set this to 1 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 29fb5d0..38535a4 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -119,7 +119,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b6ede38..70e7779 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -136,7 +136,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 24b5b70..16c7ce0 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -161,7 +161,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb index c861c9b..6ca0c9e 100644 --- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb @@ -140,7 +140,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb index 0aaeda2..5ae8a2f 100644 --- a/src/mainboard/google/brya/variants/joxer/overridetree.cb +++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb @@ -176,7 +176,7 @@ }" chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device pci 00.0 on end end end diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index 4baca1d..ef9bca7 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -208,7 +208,7 @@ }" chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device pci 00.0 on end end end diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 4bc96f9..e3d8acc 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -528,7 +528,7 @@ }" chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device pci 00.0 on end end end diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index 3c45ff4..0c8ed39 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -328,7 +328,7 @@ }" chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device pci 00.0 on end end end diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb index 6b57ada..6c58e4e 100644 --- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb @@ -207,7 +207,7 @@ }" chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" device pci 00.0 on end end end diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index f3b0fab..a1baf0a 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -228,7 +228,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" - register "is_untrusted" = "true" + register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696 Gerrit-Change-Number: 69937 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden
by Michał Żygowski (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69950 ) Change subject: soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden ...................................................................... soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden Set the P2SB device as hidden as FSP-S is hiding the PCI configuration space from coreboot on Alder Lake systems. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d --- M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/chipset_pch_s.cb 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/69950/1 diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 09dc970..86514047 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -204,7 +204,7 @@ device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index 2ade381..8effd21 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -206,7 +206,7 @@ device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end -- To view, visit https://review.coreboot.org/c/coreboot/+/69950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d Gerrit-Change-Number: 69950 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up P2SB PCI ops
by Michał Żygowski (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69949 ) Change subject: soc/intel/alderlake: Hook up P2SB PCI ops ...................................................................... soc/intel/alderlake: Hook up P2SB PCI ops P2SB device is being hidden from coreboot by FSP-S. This breaks the resouce allocator which does not report P2SB BAR via intel common block P2SB driver. Hook up the common block P2SB driver ops to soc_enable function so that the resources will be reported. The P2SB device must be set as hidden in the devicetree. This fixes the silent resource allocation conflicts on machines with devices having big BARs which accidentally overlapped P2SB BAR. TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big BARs and see resource conflicts no longer occur. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7c59441268676a8aab075abbc036e651b9426057 --- M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/p2sb.h 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/69949/1 diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index f84d2cb..98e2ea0 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -15,6 +15,7 @@ #include <soc/hsphy.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> +#include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcie.h> #include <soc/ramstage.h> @@ -232,6 +233,7 @@ static void soc_enable(struct device *dev) { + struct device_operations *soc_p2sb_ops = (struct device_operations *)&p2sb_ops; /* * Set the operations if it is a special bus type or a hidden PCI * device. @@ -243,6 +245,9 @@ else if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCH_DEVFN_PMC) dev->ops = &pmc_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCH_DEVFN_P2SB) + dev->ops = soc_p2sb_ops; else if (dev->path.type == DEVICE_PATH_GPIO) block_gpio_enable(dev); } diff --git a/src/soc/intel/alderlake/include/soc/p2sb.h b/src/soc/intel/alderlake/include/soc/p2sb.h index 2726851..367ace2 100644 --- a/src/soc/intel/alderlake/include/soc/p2sb.h +++ b/src/soc/intel/alderlake/include/soc/p2sb.h @@ -14,4 +14,6 @@ #define PCH_P2SB_EPMASK0 0x220 +extern const struct device_operations p2sb_ops; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c59441268676a8aab075abbc036e651b9426057 Gerrit-Change-Number: 69949 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S
by Michał Żygowski (Code Review) 23 Nov '22

23 Nov '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69948 ) Change subject: soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S ...................................................................... soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8 --- M src/soc/intel/alderlake/include/soc/iomap.h 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/69948/1 diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 94fb5be..59019d4 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -100,6 +100,10 @@ #define TCO_BASE_SIZE 0x20 #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define P2SB_SIZE (256 * MiB) +#else #define P2SB_SIZE (16 * MiB) +#endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8 Gerrit-Change-Number: 69948 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Select X86_INIT_NEED_1_SIPI Kconfig
by Subrata Banik (Code Review) 23 Nov '22

23 Nov '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69851 ) Change subject: soc/intel/meteorlake: Select X86_INIT_NEED_1_SIPI Kconfig ...................................................................... soc/intel/meteorlake: Select X86_INIT_NEED_1_SIPI Kconfig This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Port the Alder Lake 'commit 6526e7896727 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake. Additionally, no performance degradation is observed while running benchmarks. BUG=b:211770003 TEST=Able to boot Google, Rex to ChromeOS with all cores enabled. Without this patch: 30:device enumeration 1,480,217 (28,232) With this patch: 30:device enumeration 1,472,466 (18,334) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index b8e4052..dcb2556 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -90,6 +90,7 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202111_BINDING + select X86_INIT_NEED_1_SIPI config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/69851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5 Gerrit-Change-Number: 69851 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSD
by Subrata Banik (Code Review) 23 Nov '22

23 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Rajat Jain. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69932 ) Change subject: drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05b8c3bf23cc43863527bc514d9a96096d45003c Gerrit-Change-Number: 69932 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-Comment-Date: Wed, 23 Nov 2022 13:30:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022