coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Update DPTF parameters
by Ian Feng (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Ian Feng, Reka Norman, Sumeet R Pawnikar. Hello build bot (Jenkins), Tarun Tuli, Dtrain Hsu, Kangheui Won, Reka Norman, Sumeet R Pawnikar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69960 to look at the new patch set (#2). Change subject: mb/google/nissa/var/xivu: Update DPTF parameters ...................................................................... mb/google/nissa/var/xivu: Update DPTF parameters Follow thermal table from thermal team. 1. Modify TS1 passive policy to 68. BUG=b:249446156 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69960/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d Gerrit-Change-Number: 69960 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: sb/intel: Use "sb/intel/common/tco.h" macros
by Elyes Haouas (Code Review) 24 Nov '22

24 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69980 ) Change subject: sb/intel: Use "sb/intel/common/tco.h" macros ...................................................................... sb/intel: Use "sb/intel/common/tco.h" macros Also use read_pmbase{16,32}() in bd82x6x/elog.c. Change-Id: Ie8e6d4817ea706fc7058ec15893afb0168c1a2cb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/early_init.c 7 files changed, 44 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/69980/1 diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 684f830..ec1f71c 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/io.h> #include <acpi/acpi.h> +#include <arch/io.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> -#include <stdint.h> +#include <device/pci.h> #include <elog.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> +#include <stdint.h> + #include "pch.h" void pch_log_state(void) @@ -20,10 +22,10 @@ if (!lpc) return; - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); - tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); + pm1_sts = read_pmbase16(PM1_STS); + gpe0_sts = read_pmbase32(GPE0_STS); + gpe0_en = read_pmbase32(GPE0_EN); + tco2_sts = read_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS); gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 6fb27bb..4b27ceb 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -5,6 +5,8 @@ #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/tco.h> + #include <spi-generic.h> #include "finalize.h" @@ -48,7 +50,8 @@ if (CONFIG(BOOTMEDIA_SMM_BWP)) write_pmbase16(SMI_EN, read_pmbase16(SMI_EN) | TCO_EN); - write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, + read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT) | TCO_LOCK); post_code(POST_OS_BOOT); } diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 8ecb74c..c89dc9f 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> +#include <types.h> #include "pmutil.h" @@ -148,14 +149,14 @@ { u32 reg32; - reg32 = read_pmbase32(TCO1_STS); + reg32 = read_pmbase32(PMBASE_TCO_OFFSET + TCO1_STS); /* * set status bits are cleared by writing 1 to them, but don't * clear BOOT_STS before SECOND_TO_STS. */ - write_pmbase32(TCO1_STS, reg32 & ~BOOT_STS); + write_pmbase32(PMBASE_TCO_OFFSET + TCO2_STS, reg32 & ~BOOT_STS); if (reg32 & BOOT_STS) - write_pmbase32(TCO1_STS, BOOT_STS); + write_pmbase32(PMBASE_TCO_OFFSET + TCO2_STS, BOOT_STS); return reg32; } diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 5cf76b6..a9edcd8 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -104,14 +104,6 @@ #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) -#define BOOT_STS (1 << 18) -#define TCO2_STS 0x66 -#define TCO1_CNT 0x68 -#define TCO_LOCK (1 << 12) -#define TCO2_CNT 0x6a - u16 get_pmbase(void); u16 reset_pm1_status(void); diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 03d3122..4690320 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -6,9 +6,13 @@ #define PMBASE_TCO_OFFSET 0x60 #define TCO1_STS 0x04 #define TCO1_TIMEOUT (1 << 3) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x06 #define SECOND_TO_STS (1 << 1) +#define BOOT_STS (1 << 2) #define TCO1_CNT 0x08 #define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO2_CNT 0x0a #endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index b8bc9d8..34717b99 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -4,6 +4,8 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> + #include "i82801ix.h" #include "chip.h" @@ -64,8 +66,8 @@ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); /* Reset watchdog. */ - outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ - outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index f7e880c..b79b352 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -6,6 +6,8 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> + #include "i82801jx.h" #include "chip.h" @@ -63,8 +65,6 @@ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); } -#define TCO_BASE 0x60 - void i82801jx_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); @@ -80,9 +80,9 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ - write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ - write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); printk(BIOS_DEBUG, " done.\n"); /* Enable IOAPIC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8e6d4817ea706fc7058ec15893afb0168c1a2cb Gerrit-Change-Number: 69980 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h
by Saurabh Mishra (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Saurabh Mishra, Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69884 to look at the new patch set (#10). Change subject: vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h ...................................................................... vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h Changes include: - FirmwareVersionInfoHob.h is removed to use new header file FirmwareVersionInfo.h. BUG=b:260183604 TEST=Verify MTL Rex0 build with all the patch in relation chain and verify the version output prints no junk data observed. Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b --- D src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfoHob.h 1 file changed, 18 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/69884/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b Gerrit-Change-Number: 69884 Gerrit-PatchSet: 10 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2
by Saurabh Mishra (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Saurabh Mishra, Tarun Tuli, Subrata Banik, Kapil Porwal, Balaji Manigandan, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Balaji Manigandan, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69883 to look at the new patch set (#10). Change subject: soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2 ...................................................................... soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2 Changes include: - Select DISPLAY_FSP_VERSION_INFO_2 for Meteor Lake soc to use new header file FirmwareVersionInfo.h. BUG=b:260183604 TEST=Verify MTL Rex0 build with all the patch in relation chain and verify the version output prints no junk data observed. Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/69883/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf Gerrit-Change-Number: 69883 Gerrit-PatchSet: 10 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.h
by Saurabh Mishra (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Saurabh Mishra, Tarun Tuli, Subrata Banik, Kapil Porwal, Balaji Manigandan, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Balaji Manigandan, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69882 to look at the new patch set (#15). Change subject: vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.h ...................................................................... vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.h Changes include: - Add header file FirmwareVersionInfo.h BUG=b:260183604 BRANCH=None TEST=Verify MTL Rex0 build with all the patch in relation chain and verify the version output prints no junk data observed. Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c --- A src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfo.h 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/69882/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/69882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c Gerrit-Change-Number: 69882 Gerrit-PatchSet: 15 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vendorcode/intel/edk2/edk2-stable202111: Update MdePkg/Include/Indust...
by Saurabh Mishra (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Saurabh Mishra. Saurabh Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69961 ) Change subject: vendorcode/intel/edk2/edk2-stable202111: Update MdePkg/Include/IndustryStandard/SmBios.h ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69961/comment/dc3567fb_2adb3c27 PS3, Line 7: edk2-stable202111: > vendorcode/intel/edk2/edk2-stable202111: Done https://review.coreboot.org/c/coreboot/+/69961/comment/f763a47f_f8c08018 PS3, Line 9: Back-ported from 'https://review.coreboot.org/q/commit:f7e8adac7b3123' > I have shown you what to write but still you have added the link directly here? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Gerrit-Change-Number: 69961 Gerrit-PatchSet: 3 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Vikrant Jadeja Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 09:29:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vendorcode/intel/edk2/edk2-stable202111: Update MdePkg/Include/Indust...
by Saurabh Mishra (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Saurabh Mishra, Tarun Tuli, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Saurabh Mishra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69961 to look at the new patch set (#4). Change subject: vendorcode/intel/edk2/edk2-stable202111: Update MdePkg/Include/IndustryStandard/SmBios.h ...................................................................... vendorcode/intel/edk2/edk2-stable202111: Update MdePkg/Include/IndustryStandard/SmBios.h Back-ported from 'commit f7e8adac7b3123 ("edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h")' to fix compilation issue due to enum macro redefinition. Changes include: - Safeguarding enum macro definitions with DISPLAY_FSP_VERSION_INFO_2 Kconfig. BUG=b:260183604 TEST=Verify MTL Rex0 build with the patch and verify the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae --- M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBios.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69961/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Gerrit-Change-Number: 69961 Gerrit-PatchSet: 4 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Vikrant Jadeja Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Update DPTF parameters
by Kangheui Won (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Ian Feng, Reka Norman, Sumeet R Pawnikar. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69960 ) Change subject: mb/google/nissa/var/xivu: Update DPTF parameters ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69960/comment/5faf5ebd_1ec4e6cc PS1, Line 9: DTT_setting_20221122_V04_PR.xlsx What's this? Can you replace filename with more descriptive words? -- To view, visit https://review.coreboot.org/c/coreboot/+/69960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d Gerrit-Change-Number: 69960 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 09:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: edk2-stable202111: Update MdePkg/Include/IndustryStandard/SmBios.h
by Subrata Banik (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Saurabh Mishra, Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69961 ) Change subject: edk2-stable202111: Update MdePkg/Include/IndustryStandard/SmBios.h ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69961/comment/fd54ce5c_35e22744 PS3, Line 7: edk2-stable202111: vendorcode/intel/edk2/edk2-stable202111: https://review.coreboot.org/c/coreboot/+/69961/comment/c083d70b_943f9134 PS3, Line 9: Back-ported from 'https://review.coreboot.org/q/commit:f7e8adac7b3123' I have shown you what to write but still you have added the link directly here? back-ported from 'commit f7e8adac7b3123 ("edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h")' to fix compilation issue due to enum macro redefinition. -- To view, visit https://review.coreboot.org/c/coreboot/+/69961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Gerrit-Change-Number: 69961 Gerrit-PatchSet: 3 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant Jadeja Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 09:11:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Update DPTF parameters
by Dtrain Hsu (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Ian Feng, Kangheui Won, Reka Norman, Sumeet R Pawnikar. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69960 ) Change subject: mb/google/nissa/var/xivu: Update DPTF parameters ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d Gerrit-Change-Number: 69960 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 09:07:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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