coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add...
by build bot (Jenkins) (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Nick Vaccaro. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69970 ) Change subject: {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add_acpi_external_facing_port` ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164475): https://review.coreboot.org/c/coreboot/+/69970/comment/f6bd0831_c94d9808 PS1, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/69970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 Gerrit-Change-Number: 69970 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 24 Nov 2022 12:36:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add...
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69970 ) Change subject: {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add_acpi_external_facing_port` ...................................................................... {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add_acpi_external_facing_port` Name a variable based on its utility. This variable adds `ExternalFacingPort` _DSD property to an ACPI device. BUG=b:259716145 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 3 files changed, 18 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/69970/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 9f3987e..3a54d3b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -489,7 +489,7 @@ chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" register "srcclk_pin" = "3" - register "is_external" = "1" + register "add_acpi_external_facing_port" = "1" device generic 1 on probe DB_SD SD_RTS5261 end diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h index 652aaff..8b62406 100644 --- a/src/soc/intel/common/block/pcie/rtd3/chip.h +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -44,7 +44,7 @@ * Add device property indicating the device provides an external PCI port * for the OS to apply security restrictions. */ - bool is_external; + bool add_acpi_external_facing_port; /* * Allow a device to add the RuntimeD3Storage property even if the detected diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 7a64734..85ee24f 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -479,7 +479,7 @@ acpi_dp_add_package(dsd, pkg); /* Indicate to the OS if the device provides an External facing port. */ - if (config->is_external) { + if (config->add_acpi_external_facing_port) { pkg = acpi_dp_new_table(PCIE_EXTERNAL_PORT_UUID); acpi_dp_add_integer(pkg, PCIE_EXTERNAL_PORT_PROPERTY, 1); acpi_dp_add_package(dsd, pkg); -- To view, visit https://review.coreboot.org/c/coreboot/+/69970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 Gerrit-Change-Number: 69970 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Paul Menzel, Rizwan Qureshi, Sridhar Siricilla. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69698 ) Change subject: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/meteorlake/me.c: https://review.coreboot.org/c/coreboot/+/69698/comment/8f5d5a1f_a605616a PS1, Line 79: is_manuf_mode > What is the point of not writing `is_manufacturing_mode()`? It’d be great, if you improved that in a […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/69698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Gerrit-Change-Number: 69698 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 12:14:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Rizwan Qureshi, Sridhar Siricilla. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69698 to look at the new patch set (#3). Change subject: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode ...................................................................... soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode BUG=none TEST=Build and boot to google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b --- M src/soc/intel/meteorlake/me.c 1 file changed, 27 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69698/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Gerrit-Change-Number: 69698 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Use common code CSE-Lite API for WP information
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Ivy Jian, Eric Lai. Kapil Porwal has uploaded a new patch set (#2) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/69969 ) Change subject: soc/intel/alderlake: Use common code CSE-Lite API for WP information ...................................................................... soc/intel/alderlake: Use common code CSE-Lite API for WP information This patch drops the local implementation `log_me_ro_write_protection_info` and adopts the API from IA common code (cse_lite.c). BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899 --- M src/soc/intel/alderlake/me.c 1 file changed, 19 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/69969/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899 Gerrit-Change-Number: 69969 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vendorcode/intel/edk2/edk2-stable202111: Update MdePkg/Include/Indust...
by Paul Menzel (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Saurabh Mishra, Tarun Tuli, Subrata Banik, Kapil Porwal. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69961 ) Change subject: vendorcode/intel/edk2/edk2-stable202111: Update MdePkg/Include/IndustryStandard/SmBios.h ...................................................................... Patch Set 4: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69961/comment/795f1eaa_35691e33 PS4, Line 7: Update MdePkg/Include/IndustryStandard/SmBios.h Please be more specific. https://review.coreboot.org/c/coreboot/+/69961/comment/72faa145_8648096d PS4, Line 7: vendorcode vc https://review.coreboot.org/c/coreboot/+/69961/comment/33aa7d52_65d3a0b2 PS4, Line 8: Please start by describing the problem. https://review.coreboot.org/c/coreboot/+/69961/comment/112bd46d_d459ca12 PS4, Line 9: Please use only one space. https://review.coreboot.org/c/coreboot/+/69961/comment/1d605b5e_8d0296ac PS4, Line 9: ' Remove. https://review.coreboot.org/c/coreboot/+/69961/comment/fd1938c3_bdfa74df PS4, Line 13: Changes include: Not needed. https://review.coreboot.org/c/coreboot/+/69961/comment/80f0a83c_5674727f PS4, Line 15: Kconfig. Safe guard enum macro with …. -- To view, visit https://review.coreboot.org/c/coreboot/+/69961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Gerrit-Change-Number: 69961 Gerrit-PatchSet: 4 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Vikrant Jadeja Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 11:50:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > @Kapil, can u please use this CL to rebase https://review.coreboot. […] done -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 8 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 11:43:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69571 to look at the new patch set (#8). Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... soc/intel/meteorlake: Log CSE RO write protection info for MTL The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 --- M src/soc/intel/meteorlake/me.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69571/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 8 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Use common code CSE-Lite API for WP information
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Ivy Jian, Eric Lai. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69969 ) Change subject: soc/intel/alderlake: Use common code CSE-Lite API for WP information ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899 Gerrit-Change-Number: 69969 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 10:44:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Create API to get CSE Lite WP Information
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Ivy Jian, Angel Pons, Eric Lai. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69968 ) Change subject: soc/intel/cmn/cse: Create API to get CSE Lite WP Information ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8 Gerrit-Change-Number: 69968 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 10:43:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022