coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Allow to perform essential post CSE operations
by Subrata Banik (Code Review) 24 Nov '22

24 Nov '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69978 ) Change subject: soc/intel/cmn/cse: Allow to perform essential post CSE operations ...................................................................... soc/intel/cmn/cse: Allow to perform essential post CSE operations This patch allows to send late EOP cmd to CSE (after CSE .final) using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD) if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config. BUG=none TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69978/1 diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index b8b8e36..38ec0cffe 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -240,7 +240,9 @@ static void set_cse_end_of_post(void *unused) { - return do_send_end_of_post(); + do_send_end_of_post(); + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + cse_late_finalize(); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/69978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Gerrit-Change-Number: 69978 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Create API to perform essential post EOP operations
by Subrata Banik (Code Review) 24 Nov '22

24 Nov '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69977 ) Change subject: soc/intel/cmn/cse: Create API to perform essential post EOP operations ...................................................................... soc/intel/cmn/cse: Create API to perform essential post EOP operations This patch creates an API that can perform essential CSE operation after sending the EOP command to the CSE and before booting to OS. Lists of operation are - Perform global reset lock - Put HECI1 to D0i3 and disable the HECI1 if the user selects - Set D0I3 for all HECI devices. Additionally, ensures that CSE .final operation is not sending EOP and other essential operations if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config. BUG=none TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/69977/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index fdeb01e..6434371 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1256,11 +1256,34 @@ } /* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void) +{ + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + return; + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) + cse_final_ready_to_boot(); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + cse_final_end_of_firmware(); +} + +/* * `cse_final` function is native implementation of equivalent events performed by * each FSP NotifyPhase() API invocations. */ static void cse_final(struct device *dev) { + /* + * SoC user decided to send EOP late hence, the `cse_late_finalize()` will + * take care of essential post EOP cse related operations. + */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + return; + /* 1. Send EOP to CSE if not done.*/ if (CONFIG(SOC_INTEL_CSE_SET_EOP)) cse_send_end_of_post(); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f7aae1c..564ff48 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -542,6 +542,12 @@ void cse_send_end_of_post(void); /* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void); + +/* * SoC override API to make heci1 disable using PCR. * * Allow SoC to implement heci1 disable override due to PSF registers being -- To view, visit https://review.coreboot.org/c/coreboot/+/69977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Gerrit-Change-Number: 69977 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Create another config for sending CSE EOP cmd late
by Subrata Banik (Code Review) 24 Nov '22

24 Nov '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69976 ) Change subject: soc/intel/cmn/cse: Create another config for sending CSE EOP cmd late ...................................................................... soc/intel/cmn/cse: Create another config for sending CSE EOP cmd late Presently, coreboot supports two instances of sending EOP cmd to the Intel CSE. 1. Sending EOP cmd to CSE during `.final` operation from cse pci driver. 2. Starting with Alder Lake, the recommendation was to send EOP to CSE earlier than CSE `.final` operation. Since then it's referred to as `Sending EOP Early`. This method helped to save the CSE EOP response time significantly. During Meteor Lake platform, CSE EOP response time has become non-deterministic and we have figured that sending EOP command later than CSE .final operation is actually helping to optimize the boot time significantly (around ~150ms savings compared to sending from `.final` ops and ~5sec compared to sending CSE early). Hence, this patch intended to create yet another kconfig for sending CSE late (specifically after `.final` operation). The idea for this newer config is to use the boot state machine for sending CSE EOP cmd. The patch train in this series would add the specific changes to allow sending EOP late and perform other essential operations required prior booting to OS as coreboot decided to skip calling into FSP Notify phase. The current plan is that Intel Meteor Lake platform will select this newer config from SoC code. BUG=none TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/69976/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55a2b49..cdc4db4 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -54,6 +54,17 @@ In later stages, CSE might be busy and might require more time to process EOP command. SoC can use this Kconfig to send EOP earlier by itself. +config SOC_INTEL_CSE_SEND_EOP_LATE + bool + depends on SOC_INTEL_COMMON_BLOCK_CSE + help + Use this config to send End Of Post (EOP) late (even after CSE `final` operation) + using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code + in order to reduce time required to send EOP and getting CSE response. + It has been observed that CSE might be busy and might require more time to + process the EOP command. + SoC can use this Kconfig to send EOP later by itself. + config SOC_INTEL_CSE_LITE_SKU bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/69976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f Gerrit-Change-Number: 69976 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Send EOP cmd from .final aka `cse final()`
by Subrata Banik (Code Review) 24 Nov '22

24 Nov '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69975 ) Change subject: soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()` ...................................................................... soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()` This patch refactors common code to allow cse_final() function to send EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig. This patch helps cse_final_ready_to_boot() and cse_final_end_of_firmware() function for being meaningful with its operation and let cse_final() being that outer layer to perform three operations based on the selected kconfig. 1. send cse eop command 2. perform cse_final_end_of_firmware() operations 3. perform cse_final_end_of_firmware() operations BUG=none TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I412291c9378011509d3825f9b01e81bfced53303 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 31 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/69975/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c2d4484..fdeb01e 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1228,17 +1228,13 @@ * performed by FSP NotifyPhase(Ready To Boot) API invocations. * * Operations are: - * 1. Send EOP to CSE if not done. - * 2. Perform global reset lock. - * 3. Put HECI1 to D0i3 and disable the HECI1 if the user selects + * 1. Perform global reset lock. + * 2. Put HECI1 to D0i3 and disable the HECI1 if the user selects * DISABLE_HECI1_AT_PRE_BOOT config or CSE HFSTS1 Operation Mode is * `Software Temporary Disable`. */ static void cse_final_ready_to_boot(void) { - if (CONFIG(SOC_INTEL_CSE_SET_EOP)) - cse_send_end_of_post(); - cse_control_global_reset_lock(); if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) { @@ -1265,6 +1261,10 @@ */ static void cse_final(struct device *dev) { + /* 1. Send EOP to CSE if not done.*/ + if (CONFIG(SOC_INTEL_CSE_SET_EOP)) + cse_send_end_of_post(); + if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) cse_final_ready_to_boot(); -- To view, visit https://review.coreboot.org/c/coreboot/+/69975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412291c9378011509d3825f9b01e81bfced53303 Gerrit-Change-Number: 69975 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [NEEDS TEST] util/superiotool: Replace iopl with ioperm
by Nicholas Chin (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Felix Held. Hello Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69981 to look at the new patch set (#2). Change subject: [NEEDS TEST] util/superiotool: Replace iopl with ioperm ...................................................................... [NEEDS TEST] util/superiotool: Replace iopl with ioperm The iopl system call is marked as deprecated, and on some distributions the call no longer seems to be implemented. Replace it with ioperm. Resolves: https://ticket.coreboot.org/issues/440 TEST: Run superiotool sucessfully on Ubuntu 22.10, which does not seem to have iopl implemented Change-Id: I6671023b09d22ff38e578d11d04674fb6ae763c9 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/superiotool/superiotool.c 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/69981/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6671023b09d22ff38e578d11d04674fb6ae763c9 Gerrit-Change-Number: 69981 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: [NEEDS TEST] util/superiotool: Replace iopl with ioperm
by Nicholas Chin (Code Review) 24 Nov '22

24 Nov '22

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69981 ) Change subject: [NEEDS TEST] util/superiotool: Replace iopl with ioperm ...................................................................... [NEEDS TEST] util/superiotool: Replace iopl with ioperm The iopl system call is marked as deprecated, and on some distributions the call no longer seems to be implemented. Replace it with ioperm. Resolves: https://ticket.coreboot.org/issues/440 Change-Id: I6671023b09d22ff38e578d11d04674fb6ae763c9 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/superiotool/superiotool.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/69981/1 diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index ed18c13..f7b96f6 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -324,7 +324,7 @@ if ((io_fd = open("/dev/io", O_RDWR)) < 0) { perror("/dev/io"); #else - if (iopl(3) < 0) { + if (ioperm(0, 65536, 1) < 0) { perror("iopl"); #endif printf("Superiotool must be run as root.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/69981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6671023b09d22ff38e578d11d04674fb6ae763c9 Gerrit-Change-Number: 69981 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h
by Saurabh Mishra (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Kapil Porwal. Saurabh Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69961 ) Change subject: vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h ...................................................................... Patch Set 4: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69961/comment/fde418b5_8b1d8ac5 PS4, Line 7: vendorcode > vc Done https://review.coreboot.org/c/coreboot/+/69961/comment/ab44790f_43e9afc0 PS4, Line 7: Update MdePkg/Include/IndustryStandard/SmBios.h > Please be more specific. Done https://review.coreboot.org/c/coreboot/+/69961/comment/29551e39_43c7e72d PS4, Line 8: > Please start by describing the problem. Done https://review.coreboot.org/c/coreboot/+/69961/comment/10e8fce5_51b66259 PS4, Line 9: > Please use only one space. Done https://review.coreboot.org/c/coreboot/+/69961/comment/11b35e32_efbda633 PS4, Line 9: ' > Remove. Done https://review.coreboot.org/c/coreboot/+/69961/comment/36bf11ef_b0c75d9b PS4, Line 13: Changes include: > Not needed. Done https://review.coreboot.org/c/coreboot/+/69961/comment/3130aa62_cfa747a8 PS4, Line 15: Kconfig. > Safe guard enum macro with …. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Gerrit-Change-Number: 69961 Gerrit-PatchSet: 4 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant Jadeja Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 18:21:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h
by Saurabh Mishra (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Saurabh Mishra, Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Saurabh Mishra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69961 to look at the new patch set (#5). Change subject: vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h ...................................................................... vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h Fix compilation issue due to enum macro redefinition by safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig. Back-ported from commit f7e8adac7b3123 ("edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due to enum macro redefinition. BUG=b:260183604 TEST=Verify MTL Rex0 build with the patch and verify the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae --- M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBios.h 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69961/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Gerrit-Change-Number: 69961 Gerrit-PatchSet: 5 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant Jadeja Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/lint: Ignore fmd files when evaluating Kconfig symbols
by Martin L Roth (Code Review) 24 Nov '22

24 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69918 ) Change subject: util/lint: Ignore fmd files when evaluating Kconfig symbols ...................................................................... util/lint: Ignore fmd files when evaluating Kconfig symbols Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69918 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/lint/kconfig_lint 1 file changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index f2a732d..9c9a8a9 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -34,7 +34,7 @@ my $exclude_dirs_and_files = '^build/\|^coreboot-builds/\|^configs/\|^util/\|^\.git/\|^payloads\|^Documentation\|^3rdparty' . '\|' . # directories to exclude when searching for used symbols - '\.config\|\.txt$\|\.tex$\|\.tags\|/kconfig.h'; #files to exclude when looking for symbols + '\.config\|\.txt$\|\.tex$\|\.tags\|/kconfig.h\|\.fmd'; #files to exclude when looking for symbols my $payload_files_to_check='payloads/Makefile.inc payloads/external/Makefile.inc'; my $config_file = ""; # name of config file to load symbol values from. my @wholeconfig; # document the entire kconfig structure -- To view, visit https://review.coreboot.org/c/coreboot/+/69918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310 Gerrit-Change-Number: 69918 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/system76: Reset Realtek codec before configuring
by Martin L Roth (Code Review) 24 Nov '22

24 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66918 ) Change subject: mb/system76: Reset Realtek codec before configuring ...................................................................... mb/system76: Reset Realtek codec before configuring Perform a codec reset before configuring to avoid potential issues like oryp5 had before 86f410479ca9 ("mb/system76/oryp5: Reset HDA before configuring"). Inspecting proprietary firmware for multiple boards shows that this is always done as well. Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66918 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/addw1/variants/addw1/hda_verb.c M src/mainboard/system76/addw1/variants/addw2/hda_verb.c M src/mainboard/system76/bonw14/hda_verb.c M src/mainboard/system76/cml-u/variants/darp6/hda_verb.c M src/mainboard/system76/cml-u/variants/galp4/hda_verb.c M src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c M src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c M src/mainboard/system76/gaze16/variants/gaze16-3050/hda_verb.c M src/mainboard/system76/gaze16/variants/gaze16-3060/hda_verb.c M src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c M src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c M src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c M src/mainboard/system76/lemp9/hda_verb.c M src/mainboard/system76/oryp5/hda_verb.c M src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c M src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c M src/mainboard/system76/oryp8/hda_verb.c M src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c M src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c M src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c M src/mainboard/system76/whl-u/variants/darp5/hda_verb.c M src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c 22 files changed, 64 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c index ca440e4..aedd285 100644 --- a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c +++ b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC1220 */ 0x10ec1220, /* Vendor ID */ 0x155865d1, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155865d1), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D) AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A) diff --git a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c index 9b1cb63..8175c9b 100644 --- a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c +++ b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC1220 */ 0x10ec1220, /* Vendor ID */ 0x155865e1, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155865e1), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D) AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A) diff --git a/src/mainboard/system76/bonw14/hda_verb.c b/src/mainboard/system76/bonw14/hda_verb.c index 00f5fdb..dfe3187 100644 --- a/src/mainboard/system76/bonw14/hda_verb.c +++ b/src/mainboard/system76/bonw14/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC1220 */ 0x10ec1220, /* Vendor ID */ 0x15587714, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15587714), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x40000000), AZALIA_PIN_CFG(0, 0x15, 0x411111f0), diff --git a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c index 09d8357..95f9d43 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek ALC293 */ 0x10ec0293, /* Vendor ID */ 0x15581404, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581404), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c b/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c index 1b04604..2030d00 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek ALC293 */ 0x10ec0293, /* Vendor ID */ 0x15581403, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581403), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c index 367d647..6bc881b 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c +++ b/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC269VC */ 0x10ec0269, /* Vendor ID */ 0x15588560, /* Subsystem ID */ - 11, /* Number of entries */ + 12, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15588560), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), diff --git a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c index 1540485..761386a 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c +++ b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC293 */ 0x10ec0293, /* Vendor ID */ 0x15588520, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15588520), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/hda_verb.c b/src/mainboard/system76/gaze16/variants/gaze16-3050/hda_verb.c index 28127f3..35c27a1 100644 --- a/src/mainboard/system76/gaze16/variants/gaze16-3050/hda_verb.c +++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC256 */ 0x10ec0256, /* Vendor ID */ 0x15585017, /* Subsystem ID */ - 11, /* Number of entries */ + 12, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15585017), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/hda_verb.c b/src/mainboard/system76/gaze16/variants/gaze16-3060/hda_verb.c index 4a4fc0e..491e32b 100644 --- a/src/mainboard/system76/gaze16/variants/gaze16-3060/hda_verb.c +++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC256 */ 0x10ec0256, /* Vendor ID */ 0x155850e2, /* Subsystem ID */ - 11, /* Number of entries */ + 12, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155850e2), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c index 8e5012b..208107c 100644 --- a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC269VC */ 0x10ec0269, /* Vendor ID */ 0x15581303, /* Subsystem ID */ - 11, /* Number of entries */ + 12, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581303), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170120), AZALIA_PIN_CFG(0, 0x15, 0x02211010), diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c index a7c927f..2e43bef 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC269VC */ 0x10ec0269, /* Vendor ID */ 0x15581414, /* Subsystem ID */ - 11, /* Number of entries */ + 12, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581414), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170120), AZALIA_PIN_CFG(0, 0x15, 0x02211010), diff --git a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c index 83cd41d..de588d5 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC269VC */ 0x10ec0269, /* Vendor ID */ 0x15581313, /* Subsystem ID */ - 11, /* Number of entries */ + 12, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581313), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170120), AZALIA_PIN_CFG(0, 0x15, 0x02211010), diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/lemp9/hda_verb.c index 7bb0736..1b9386d 100644 --- a/src/mainboard/system76/lemp9/hda_verb.c +++ b/src/mainboard/system76/lemp9/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek ALC293 */ 0x10ec0293, /* Vendor ID */ 0x15581401, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581401), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/oryp5/hda_verb.c b/src/mainboard/system76/oryp5/hda_verb.c index 2d10725..575c839 100644 --- a/src/mainboard/system76/oryp5/hda_verb.c +++ b/src/mainboard/system76/oryp5/hda_verb.c @@ -6,7 +6,7 @@ /* Realtek, ALC1220 */ 0x10ec1220, /* Vendor ID */ 0x155896e1, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155896e1), AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), // DMIC diff --git a/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c index b36ad82..2f30d40 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC1220 */ 0x10ec1220, /* Vendor ID */ 0x155850d3, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155850d3), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), diff --git a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c index cc959b8..d251b33 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c +++ b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC1220 */ 0x10ec1220, /* Vendor ID */ 0x155865e5, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155865e5), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), diff --git a/src/mainboard/system76/oryp8/hda_verb.c b/src/mainboard/system76/oryp8/hda_verb.c index 47d28dd..2a32f01 100644 --- a/src/mainboard/system76/oryp8/hda_verb.c +++ b/src/mainboard/system76/oryp8/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC1220 */ 0x10ec1220, /* Vendor ID */ 0x155865f1, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155865f1), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), diff --git a/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c b/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c index dc5f72e..53a47bd 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC293 */ 0x10ec0293, /* Vendor ID */ 0x155851a1, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155851a1), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c index 1f21ff7..c0afb19 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC293 */ 0x10ec0293, /* Vendor ID */ 0x15584018, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15584018), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c index 1259ba1..43a0ee5 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek, ALC293 */ 0x10ec0293, /* Vendor ID */ 0x155814a1, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x155814a1), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c index c363590..3372f9c 100644 --- a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c +++ b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek ALC293 */ 0x10ec0293, /* Vendor ID */ 0x15581325, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581325), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c index fe94926..03f2f8c 100644 --- a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c +++ b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c @@ -6,8 +6,9 @@ /* Realtek ALC293 */ 0x10ec0293, /* Vendor ID */ 0x15581323, /* Subsystem ID */ - 12, /* Number of entries */ + 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x15581323), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), -- To view, visit https://review.coreboot.org/c/coreboot/+/66918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61 Gerrit-Change-Number: 66918 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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