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[S] Change in coreboot[master]: google/*/*/sdram_configs.c: Add function argument
by Felix Held (Code Review) 24 Nov '22

24 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69748 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: google/*/*/sdram_configs.c: Add function argument ...................................................................... google/*/*/sdram_configs.c: Add function argument A function declaration without a prototype is deprecated in all versions of C. Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69748 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/foster/sdram_configs.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/nyan/sdram_configs.c M src/mainboard/google/nyan_big/sdram_configs.c M src/mainboard/google/nyan_blaze/sdram_configs.c M src/mainboard/google/smaug/sdram_configs.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/sdram_configs.c 9 files changed, 25 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/mainboard/google/foster/sdram_configs.c b/src/mainboard/google/foster/sdram_configs.c index 25d6403..c42d787 100644 --- a/src/mainboard/google/foster/sdram_configs.c +++ b/src/mainboard/google/foster/sdram_configs.c @@ -11,7 +11,7 @@ #include "bct/sdram-unused.inc" /* ram_code = 0011 */ }; -const struct sdram_params *get_sdram_config() +const struct sdram_params *get_sdram_config(void) { uint32_t ramcode = sdram_get_ram_code(); /* diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 2aceb9f..aae3377 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -44,7 +44,7 @@ return dram_928MHz; } -const struct rk3399_sdram_params *get_sdram_config() +const struct rk3399_sdram_params *get_sdram_config(void) { char config_file[64]; uint32_t ramcode; diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c index 241fbce..a7ab4c7 100644 --- a/src/mainboard/google/nyan/sdram_configs.c +++ b/src/mainboard/google/nyan/sdram_configs.c @@ -24,7 +24,7 @@ #include "bct/sdram-unused.inc" /* ram_code = 1111 */ }; -const struct sdram_params *get_sdram_config() +const struct sdram_params *get_sdram_config(void) { uint32_t ramcode = sdram_get_ram_code(); /* diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c index 15ed489..ee3816a 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.c +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -24,7 +24,7 @@ #include "bct/sdram-unused.inc" /* ram_code = 1111 */ }; -const struct sdram_params *get_sdram_config() +const struct sdram_params *get_sdram_config(void) { uint32_t ramcode = sdram_get_ram_code(); /* diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index 7972255..02a374c 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -24,7 +24,7 @@ #include "bct/sdram-unused.inc" /* ram_code = 1111 */ }; -const struct sdram_params *get_sdram_config() +const struct sdram_params *get_sdram_config(void) { uint32_t ramcode = sdram_get_ram_code(); /* diff --git a/src/mainboard/google/smaug/sdram_configs.c b/src/mainboard/google/smaug/sdram_configs.c index 8d45211..92e00d6 100644 --- a/src/mainboard/google/smaug/sdram_configs.c +++ b/src/mainboard/google/smaug/sdram_configs.c @@ -22,7 +22,7 @@ #include "bct/sdram-unused.inc" /* ram_code = 1111 */ }; -const struct sdram_params *get_sdram_config() +const struct sdram_params *get_sdram_config(void) { uint32_t ramcode = sdram_get_ram_code(); /* diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index b76ed09..4b04492 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -34,7 +34,7 @@ _Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!"); -const struct rk3288_sdram_params *get_sdram_config() +const struct rk3288_sdram_params *get_sdram_config(void) { u32 ramcode = ram_code(); diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index b76ed09..4b04492 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -34,7 +34,7 @@ _Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!"); -const struct rk3288_sdram_params *get_sdram_config() +const struct rk3288_sdram_params *get_sdram_config(void) { u32 ramcode = ram_code(); diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 6a97c17..91b9439 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -34,7 +34,7 @@ _Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!"); -const struct rk3288_sdram_params *get_sdram_config() +const struct rk3288_sdram_params *get_sdram_config(void) { u32 ramcode = ram_code(); -- To view, visit https://review.coreboot.org/c/coreboot/+/69748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158 Gerrit-Change-Number: 69748 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd: Define post codes
by Felix Held (Code Review) 24 Nov '22

24 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69867 ) Change subject: soc/amd: Define post codes ...................................................................... soc/amd: Define post codes For the most part, this doesn't change any post codes, simply making the existing post-codes into macros. picasso/romstage.c did get a couple of post codes removed to match the other files. The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global at some point, while the POST_AGESA and POST_PSP codes would stay AMD specific. Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/noncar/pre_c.S A src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/morgana/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 11 files changed, 89 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 251e23a..b38ce80 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,6 +8,7 @@ ****************************************************************************** */ +#include <amdblocks/post_codes.h> #include <cpu/x86/post_code.h> .section .init @@ -27,7 +28,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -41,7 +42,7 @@ pushl %eax /* tsc[31:0] */ before_carstage: - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 503de3b..e123c36 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/post_codes.h> #include <cpu/x86/post_code.h> .section .init, "ax", @progbits .global bootblock_resume_entry bootblock_resume_entry: - post_code(0xb0) + post_code(POST_BOOTBLOCK_RESUME_ENTRY) /* Get an early timestamp */ rdtsc @@ -23,7 +24,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) #if ENV_X86_64 #include <cpu/x86/64bit/entry64.inc> @@ -56,7 +57,7 @@ pushl %eax /* tsc[31:0] */ #endif - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h new file mode 100644 index 0000000..5251769 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_POST_CODES_H +#define AMD_BLOCK_POST_CODES_H + +#define POST_AGESA_AMDINITRESET 0x37 +#define POST_AGESA_AMDINITEARLY 0x38 + +#define POST_ROMSTAGE_MAIN 0x40 + +#define POST_AGESA_AMDINITPOST 0x40 +#define POST_AGESA_AMDINITPOST_DONE 0x41 + +#define POST_PSP_NOTIFY_DRAM 0x42 +#define POST_PSP_NOTIFY_DRAM_DONE 0x43 + +#define POST_ROMSTAGE_RUN_POSTCAR 0x44 + +#define POST_PSP_LOAD_SMU 0x46 +#define POST_AGESA_AMDINITENV 0x47 +#define POST_AGESA_AMDS3LATERESTORE 0x48 + +#define POST_AGESA_AMDINITRESUME 0x60 +#define POST_AGESA_AMDINITRESUME_DONE 0x61 + +#define POST_BOOTBLOCK_SOC_EARLY_INIT 0x90 + + +#define POST_BOOTBLOCK_RESUME_ENTRY 0xb0 +#define POST_BOOTBLOCK_PRE_C_ENTRY 0xa0 +#define POST_BOOTBLOCK_PRE_C_DONE 0xa2 + +#endif diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/glinda/romstage.c +++ b/src/soc/amd/glinda/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c index 3548a79..0ca32ba 100644 --- a/src/soc/amd/mendocino/romstage.c +++ b/src/soc/amd/mendocino/romstage.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <amdblocks/stb.h> #include <console/console.h> #include <cpu/cpu.h> @@ -15,7 +16,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) write_stb_to_console(); diff --git a/src/soc/amd/morgana/romstage.c b/src/soc/amd/morgana/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/morgana/romstage.c +++ b/src/soc/amd/morgana/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 9958af2..846460d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/cpu.h> @@ -13,16 +14,14 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call. */ fill_chipset_state(); - post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3()); memmap_stash_early_dram_usage(); - post_code(0x44); run_ramstage(); } diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 0a67d9b..f5451f85 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -13,6 +13,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <amdblocks/iomap.h> +#include <amdblocks/post_codes.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/southbridge.h> @@ -77,7 +78,7 @@ void bootblock_soc_early_init(void) { bootblock_fch_early_init(); - post_code(0x90); + post_code(POST_BOOTBLOCK_SOC_EARLY_INIT); } void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 1633ecd..0a530fc 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -15,6 +15,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <amdblocks/i2c.h> +#include <amdblocks/post_codes.h> #include "chip.h" @@ -115,15 +116,15 @@ static void earliest_ramstage(void *unused) { if (!acpi_is_wakeup_s3()) { - post_code(0x46); + post_code(POST_PSP_LOAD_SMU); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); - post_code(0x47); + post_code(POST_AGESA_AMDINITENV); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ - post_code(0x46); + post_code(POST_AGESA_AMDS3LATERESTORE); do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 54fc51e..efa256f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -5,6 +5,7 @@ #include <amdblocks/agesawrapper_call.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/biosram.h> +#include <amdblocks/post_codes.h> #include <amdblocks/psp.h> #include <arch/romstage.h> #include <cbmem.h> @@ -35,10 +36,10 @@ static void agesa_call(void) { - post_code(0x37); + post_code(POST_AGESA_AMDINITRESET); do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - post_code(0x38); + post_code(POST_AGESA_AMDINITEARLY); /* APs will not exit amdinitearly */ do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } @@ -66,10 +67,10 @@ bsp_agesa_call(); if (!s3_resume) { - post_code(0x40); + post_code(POST_AGESA_AMDINITPOST); do_agesawrapper(AMD_INIT_POST, "amdinitpost"); - post_code(0x41); + post_code(POST_AGESA_AMDINITPOST_DONE); /* * TODO: This is a hack to work around current AGESA behavior. * AGESA needs to change to reflect that coreboot owns @@ -99,16 +100,16 @@ wrmsr(SYSCFG_MSR, sys_cfg); } else { printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); + post_code(POST_AGESA_AMDINITRESUME); do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); - post_code(0x61); + post_code(POST_AGESA_AMDINITRESUME_DONE); } - post_code(0x42); + post_code(POST_PSP_NOTIFY_DRAM); psp_notify_dram(); - post_code(0x43); + post_code(POST_PSP_NOTIFY_DRAM_DONE); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) @@ -117,7 +118,7 @@ if (CONFIG(SMM_TSEG)) smm_list_regions(); - post_code(0x44); + post_code(POST_ROMSTAGE_RUN_POSTCAR); prepare_and_run_postcar(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Gerrit-Change-Number: 69867 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: arch/arm: Use unified assembly syntax
by Felix Held (Code Review) 24 Nov '22

24 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63058 ) ( 28 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/arm: Use unified assembly syntax ...................................................................... arch/arm: Use unified assembly syntax Taken from Linux which also updated these files. Clang only works with this syntax, so this fixes builds for arm. TESTED on qemu vexpress-a9 and verstage on google/vilboz with BUILD_TIMELESS=1, binaries remain the same. Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63058 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/arm/libgcc/lib1funcs.S M src/arch/arm/memcpy.S M src/arch/arm/memmove.S M src/arch/arm/memset.S 4 files changed, 62 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/arch/arm/libgcc/lib1funcs.S b/src/arch/arm/libgcc/lib1funcs.S index 7a8fedf..a520ad3 100644 --- a/src/arch/arm/libgcc/lib1funcs.S +++ b/src/arch/arm/libgcc/lib1funcs.S @@ -8,6 +8,8 @@ #include <arch/asm.h> +.syntax unified + .macro ARM_DIV_BODY dividend, divisor, result, curbit #if __COREBOOT_ARM_ARCH__ >= 5 @@ -67,7 +69,7 @@ subhs \dividend, \dividend, \divisor, lsr #3 orrhs \result, \result, \curbit, lsr #3 cmp \dividend, #0 @ Early termination? - movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? + movsne \curbit, \curbit, lsr #4 @ No, any more bits to do? movne \divisor, \divisor, lsr #4 bne 1b @@ -153,7 +155,7 @@ subhs \dividend, \dividend, \divisor, lsr #3 cmp \dividend, #1 mov \divisor, \divisor, lsr #4 - subges \order, \order, #4 + subsge \order, \order, #4 bge 1b tst \order, #3 diff --git a/src/arch/arm/memcpy.S b/src/arch/arm/memcpy.S index d5e28ac..b46944a 100644 --- a/src/arch/arm/memcpy.S +++ b/src/arch/arm/memcpy.S @@ -6,6 +6,8 @@ #include <arch/asm.h> #include "asmlib.h" +.syntax unified + #define LDR1W_SHIFT 0 #define STR1W_SHIFT 0 @@ -22,7 +24,7 @@ .endm .macro ldr1b ptr reg cond=al abort - ldr\cond\()b \reg, [\ptr], #1 + ldrb\cond \reg, [\ptr], #1 .endm .macro str1w ptr reg abort @@ -34,7 +36,7 @@ .endm .macro str1b ptr reg cond=al abort - str\cond\()b \reg, [\ptr], #1 + strb\cond \reg, [\ptr], #1 .endm .macro enter reg1 reg2 @@ -197,7 +199,7 @@ orr r9, r9, ip, push #\push mov ip, ip, pull #\pull orr ip, ip, lr, push #\push - str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f + str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, abort=19f bge 12b PLD( cmn r2, #96 ) PLD( bge 13b ) diff --git a/src/arch/arm/memmove.S b/src/arch/arm/memmove.S index 6595bee..f5f6340b 100644 --- a/src/arch/arm/memmove.S +++ b/src/arch/arm/memmove.S @@ -4,6 +4,8 @@ #include <arch/asm.h> #include "asmlib.h" +.syntax unified + /* * Prototype: void *memmove(void *dest, const void *src, size_t n); * @@ -88,20 +90,20 @@ 7: ldmfd sp!, {r5 - r8} 8: movs r2, r2, lsl #31 - ldrneb r3, [r1, #-1]! - ldrcsb r4, [r1, #-1]! - ldrcsb ip, [r1, #-1] - strneb r3, [r0, #-1]! - strcsb r4, [r0, #-1]! - strcsb ip, [r0, #-1] + ldrbne r3, [r1, #-1]! + ldrbcs r4, [r1, #-1]! + ldrbcs ip, [r1, #-1] + strbne r3, [r0, #-1]! + strbcs r4, [r0, #-1]! + strbcs ip, [r0, #-1] ldmfd sp!, {r0, r4, pc} 9: cmp ip, #2 - ldrgtb r3, [r1, #-1]! - ldrgeb r4, [r1, #-1]! + ldrbgt r3, [r1, #-1]! + ldrbge r4, [r1, #-1]! ldrb lr, [r1, #-1]! - strgtb r3, [r0, #-1]! - strgeb r4, [r0, #-1]! + strbgt r3, [r0, #-1]! + strbge r4, [r0, #-1]! subs r2, r2, ip strb lr, [r0, #-1]! blt 8b diff --git a/src/arch/arm/memset.S b/src/arch/arm/memset.S index 5da5353..4a29646 100644 --- a/src/arch/arm/memset.S +++ b/src/arch/arm/memset.S @@ -8,6 +8,8 @@ #include <arch/asm.h> #include "asmlib.h" +.syntax unified + ENTRY(memset) ands r3, r0, #3 @ 1 unaligned? mov ip, r0 @ preserve r0 as return value @@ -31,20 +33,20 @@ mov lr, r1 2: subs r2, r2, #64 - stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time. - stmgeia ip!, {r1, r3, r8, lr} - stmgeia ip!, {r1, r3, r8, lr} - stmgeia ip!, {r1, r3, r8, lr} + stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time. + stmiage ip!, {r1, r3, r8, lr} + stmiage ip!, {r1, r3, r8, lr} + stmiage ip!, {r1, r3, r8, lr} bgt 2b - ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. + ldmfdeq sp!, {r8, pc} @ Now <64 bytes to go. /* * No need to correct the count; we're only testing bits from now on */ tst r2, #32 - stmneia ip!, {r1, r3, r8, lr} - stmneia ip!, {r1, r3, r8, lr} + stmiane ip!, {r1, r3, r8, lr} + stmiane ip!, {r1, r3, r8, lr} tst r2, #16 - stmneia ip!, {r1, r3, r8, lr} + stmiane ip!, {r1, r3, r8, lr} ldmfd sp!, {r8, lr} #else @@ -77,21 +79,21 @@ strne r1, [ip], #4 3: subs r2, r2, #64 - stmgeia ip!, {r1, r3-r8, lr} - stmgeia ip!, {r1, r3-r8, lr} + stmiage ip!, {r1, r3-r8, lr} + stmiage ip!, {r1, r3-r8, lr} bgt 3b - ldmeqfd sp!, {r4-r8, pc} + ldmfdeq sp!, {r4-r8, pc} tst r2, #32 - stmneia ip!, {r1, r3-r8, lr} + stmiane ip!, {r1, r3-r8, lr} tst r2, #16 - stmneia ip!, {r4-r7} + stmiane ip!, {r4-r7} ldmfd sp!, {r4-r8, lr} #endif 4: tst r2, #8 - stmneia ip!, {r1, r3} + stmiane ip!, {r1, r3} tst r2, #4 strne r1, [ip], #4 /* @@ -99,17 +101,17 @@ * may have an unaligned pointer as well. */ 5: tst r2, #2 - strneb r1, [ip], #1 - strneb r1, [ip], #1 + strbne r1, [ip], #1 + strbne r1, [ip], #1 tst r2, #1 - strneb r1, [ip], #1 + strbne r1, [ip], #1 mov pc, lr 6: subs r2, r2, #4 @ 1 do we have enough blt 5b @ 1 bytes to align with? cmp r3, #2 @ 1 - strltb r1, [ip], #1 @ 1 - strleb r1, [ip], #1 @ 1 + strblt r1, [ip], #1 @ 1 + strble r1, [ip], #1 @ 1 strb r1, [ip], #1 @ 1 add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) b 1b -- To view, visit https://review.coreboot.org/c/coreboot/+/63058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750 Gerrit-Change-Number: 63058 Gerrit-PatchSet: 30 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: update pch_espi setting
by Felix Held (Code Review) 24 Nov '22

24 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69785 ) Change subject: mb/google/brya/var/marasov: update pch_espi setting ...................................................................... mb/google/brya/var/marasov: update pch_espi setting Add conn0/conn1 for pch_espi. BUG=b:254365935 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot. Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69785 Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index cb77335..70787c6 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -184,6 +184,13 @@ device spi 0 on end end # FPMCU end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden chip drivers/intel/pmc_mux device generic 0 on @@ -195,7 +202,7 @@ chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port3 as usb3_port - device generic 2 alias conn2 on end + device generic 1 alias conn1 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f Gerrit-Change-Number: 69785 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Refactor heci finalize functions
by Subrata Banik (Code Review) 24 Nov '22

24 Nov '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69974 ) Change subject: soc/intel/meteorlake: Refactor heci finalize functions ...................................................................... soc/intel/meteorlake: Refactor heci finalize functions This patch creates a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again FSP config. Currently, `heci_set_to_d0i3()` function is getting called twice. TEST=Able to build google/rex with this patch and observe coreboot log modification as below: Without this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms With this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e --- M src/soc/intel/meteorlake/finalize.c 1 file changed, 59 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/69974/1 diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index d3ae16a..f30a6ac 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -64,6 +64,13 @@ sa_lock_pam(); } +static void heci_finalize(void) +{ + heci_set_to_d0i3(); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + heci1_disable(); +} + static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); @@ -72,9 +79,9 @@ apm_control(APM_CNT_FINALIZE); tbt_finalize(); sa_finalize(); - heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci1_disable(); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && + CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + heci_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/69974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e Gerrit-Change-Number: 69974 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex: Disable SATA from the devicetree
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69973 ) Change subject: mb/google/rex: Disable SATA from the devicetree ...................................................................... mb/google/rex: Disable SATA from the devicetree SATA is not supported on google/rex hence disable it. BUG=none TEST=Build and boot to google/rex. Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I35a742ab9782feed86c3af514505d870d181b34b --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/69973/1 diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index f3b0fab..3ab5c3c 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -373,7 +373,6 @@ device i2c 15 on end end end - device ref sata on end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" -- To view, visit https://review.coreboot.org/c/coreboot/+/69973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a742ab9782feed86c3af514505d870d181b34b Gerrit-Change-Number: 69973 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Disable GSPI2 controller
by Mario Scheithauer (Code Review) 24 Nov '22

24 Nov '22

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69972 ) Change subject: mb/siemens/mc_ehl2: Disable GSPI2 controller ...................................................................... mb/siemens/mc_ehl2: Disable GSPI2 controller GSPI2 controller is disabled in FSP-S and not used on this mainboard. This also allows it to be removed from devicetree, so that the warning for leftover static devices disappears in the log. Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/69972/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 74d0f26..c922e9e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -142,8 +142,6 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 12.0 on end # GSPI2 - device pci 14.0 on end # USB3.1 xHCI device pci 15.0 on end # I2C0 -- To view, visit https://review.coreboot.org/c/coreboot/+/69972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Gerrit-Change-Number: 69972 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/intel/mtlrvp: align directory structure to chrome project
by Harsha B R (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Ronak Kanabar, Usha P. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69971 ) Change subject: mb/intel/mtlrvp: align directory structure to chrome project ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/69971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82acb6879fecb242014258f2c358804d5abbbd48 Gerrit-Change-Number: 69971 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 13:22:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add...
by Kapil Porwal (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Nick Vaccaro. Hello Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69970 to look at the new patch set (#2). Change subject: {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add_acpi_external_facing_port` ...................................................................... {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` to `add_acpi_external_facing_port` Name a variable based on its utility. This variable adds `ExternalFacingPort` _DSD property to an ACPI device. BUG=b:259716145 TEST=Build google/rex with this flag and verify it in SSDT at runtime. SSDT snippet: Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), Package (0x01) { Package (0x02) { "HotPlugSupportInD3", One } }, ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package (0x01) { Package (0x02) { "ExternalFacingPort", One } } }) Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 3 files changed, 44 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/69970/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 Gerrit-Change-Number: 69970 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/apollolake/acpi: Set PMAX to base of PCI MMIO
by Sean Rhodes (Code Review) 24 Nov '22

24 Nov '22

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/66239 ) Change subject: soc/intel/apollolake/acpi: Set PMAX to base of PCI MMIO ...................................................................... Abandoned Broke -- To view, visit https://review.coreboot.org/c/coreboot/+/66239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25b149152f1ed6cabf562d7b3864ad567f8734ca Gerrit-Change-Number: 66239 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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coreboot-gerrit November 2022