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Change subject: sb/intel/common/gpio.c: Clean up includes
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Patch Set 1: Code-Review+2
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Change subject: sb/intel/i82801gx/bootblock.c: Clean up includes
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Patch Set 1: Code-Review+2
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Change subject: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field
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Patch Set 2: Code-Review+2
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Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events
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Patch Set 1:
(2 comments)
File src/soc/amd/common/block/xhci/elog.c:
https://review.coreboot.org/c/coreboot/+/67936/comment/a16cb80a_ba7d365e
PS1, Line 17: read32
`read32p`
https://review.coreboot.org/c/coreboot/+/67936/comment/d617bfa5_dd48be4e
PS1, Line 64: info[i].usb_info
Can you decalre a local to make this easier to read
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Change subject: mb/google/skyrim: Enable amdfw separation
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Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events
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Patch Set 1:
(1 comment)
Patchset:
PS1:
Just FYI, SMM elogging just scares me. b/244736845
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Change subject: device/xhci: Factor out common PORTSC code
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Patch Set 1:
(1 comment)
File src/soc/intel/common/block/xhci/elog.c:
https://review.coreboot.org/c/coreboot/+/67933/comment/a69fb9f6_b250b3a5
PS1, Line 23: xhci_csc_set
You could make these `static inline` and move them into the header.
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Change subject: mb/google/skyrim/var/winterhold: Expend EC share memory register define for Dynamic Thermal Table Switching Proposal
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Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68077/comment/b4d33a8f_4a0ff24e
PS2, Line 7: mb/google/skyrim/var/winterhold: Expend EC share memory
: register define for Dynamic Thermal Table Switching Proposal
ec/google/chromeec/acpi/ec: Add STTT, STTB
https://review.coreboot.org/c/coreboot/+/68077/comment/b059d3d4_939f6661
PS2, Line 10: Define offset 0x09 bit 5 for temperature status of thermal
: table switch
nit: Add "STTT", to clarify which this is.
https://review.coreboot.org/c/coreboot/+/68077/comment/6bf013c8_03289599
PS2, Line 12: Define offset 0x09 bit 6 for body detection status of thermal
: table switch
Same. Add "STTB".
File src/ec/google/chromeec/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/68077/comment/f061b7db_9906226e
PS2, Line 59: RSV1, 1, // Reserved bit
Why is 1 bit being reserved? Why can't these be bits 4 and 5?
https://review.coreboot.org/c/coreboot/+/68077/comment/315ab149_a5c57cc4
PS2, Line 61:
whitespace: use tab here
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Change subject: src/drivers: Add SMMBARSTORE driver
......................................................................
Patch Set 1:
(3 comments)
File src/drivers/smmbarstore/Kconfig:
https://review.coreboot.org/c/coreboot/+/67931/comment/26d132a8_38548669
PS1, Line 3: SMMBARSTORE
Can you use _? `SMM_BAR_STORE`. Or should it be `SMM_PCI_BAR_STORE`?
File src/drivers/smmbarstore/ramstage.c:
https://review.coreboot.org/c/coreboot/+/67931/comment/af2e846c_64458273
PS1, Line 16: "outb %%al, %%dx"
I'm honestly not the biggest fan of having to invoke SMM from ramstage. Arthur just got rid of the code that has to invoke SMM to set the SMBASE.
Can we define a Kconfig `CHIPSET_SMM_STORE`. This will include a `struct chipset_smm_data` into the `struct smm_runtime`. Then the `smm_module_loader` calls `load_chipset_smm_data`, and in smm we can have a public`get_shipset_smm_data` that any module can use.
File src/include/smmbarstore.h:
https://review.coreboot.org/c/coreboot/+/67931/comment/4b87b0fa_3196dd3f
PS1, Line 9: enum smmbarstore_type_t {
> trailing whitespace
Please fix.
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Change subject: sb/intel/i82801gx/early_init.c: Include common/rcba.h
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Patch Set 1: Code-Review+2
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