coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[S] Change in coreboot[master]: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field
by Nick Vaccaro (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Tarun Tuli, YH Lin, Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68025 to look at the new patch set (#3). Change subject: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field ...................................................................... mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field Add a new THERMAL FW_CONFIG bitfield for describing power consumption category of SoC. BUG=b:250089101 TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0 and skolas to kernel. Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/68025/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Gerrit-Change-Number: 68025 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG
by Nick Vaccaro (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Varshit Pandya, Noga Smith, Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, AlanKY Lee. Hello Varshit Pandya, build bot (Jenkins), Noga Smith, YH Lin, Tarun Tuli, Subrata Banik, Tim Wawrzynczak, AlanKY Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67929 to look at the new patch set (#4). Change subject: mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG ...................................................................... mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG 1) Make the skolas FW_CONFIG field defintions compatible with the brya0 FW_CONFIG field definitions to support skolas being a SKU of brya0, and in sync with the config.star definitions for the FW_CONFIG field for brya0 and skolas. - brya0 specific changes: 1) remove WFC_MIPI_OVTI5675 definition (was 1) 2) redefine WFC_MIPI_OVTI8856 from 2 to 1 3) define new WFC_MIPI_KBAE350 camera type as 2 - skolas specific changes: 1) remove WFC_MIPI_OVTI5675 definition (was 1) 2) redefine WFC_MIPI_OVTI8856 from 2 to 1 3) define new WFC_MIPI_KBAE350 camera type as 2 2) Add support back in for UFC_MIPI_OVTI5675 in brya0 now that FW_CONFIG defines are fixed. BUG=b:248126749 TEST="emerge-brya coreboot chromeos-bootimage", flash brya0 and verify it boots successfully to kernel and that WFC, UFC, and audio works on skolas and brya0. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859 --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb 2 files changed, 205 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/67929/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/67929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859 Gerrit-Change-Number: 67929 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Noga Smith <nogasmith(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/apollolake: Remove SD Card interrupt for GLK
by Matt DeVillier (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Sean Rhodes, Andrey Petrov. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67679 ) Change subject: soc/intel/apollolake: Remove SD Card interrupt for GLK ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: assuming this is coming from the public datasheet? If so, note in commit msg? -- To view, visit https://review.coreboot.org/c/coreboot/+/67679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Gerrit-Change-Number: 67679 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Oct 2022 16:30:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/apollolake: Add UFS Interrupt
by Matt DeVillier (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Sean Rhodes, Andrey Petrov. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67680 ) Change subject: soc/intel/apollolake: Add UFS Interrupt ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: assuming this is coming from the public datasheet? If so, note in commit msg? -- To view, visit https://review.coreboot.org/c/coreboot/+/67680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Gerrit-Change-Number: 67680 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Oct 2022 16:30:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Fix unknown max speed in SMBIOS
by Jérémy Compostella (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Zhixing Ma, Bora Guvendik, Selma Bensaid, Nick Vaccaro. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67913 ) Change subject: soc/intel/alderlake: Fix unknown max speed in SMBIOS ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09bcccc6f97238f7328224af8b852751114896fe Gerrit-Change-Number: 67913 Gerrit-PatchSet: 5 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 03 Oct 2022 16:26:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in amd_blobs[master]: mendocino: Rename patchset file
by Jon Murphy (Code Review) 03 Oct '22

03 Oct '22

Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/amd_blobs/+/68021 ) Change subject: mendocino: Rename patchset file ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > This needs to be more than just renamed, the .sbin needs to be replaced with the equivalent . […] Ack -- To view, visit https://review.coreboot.org/c/amd_blobs/+/68021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: amd_blobs Gerrit-Branch: master Gerrit-Change-Id: I97781d235be60851aa9b4e49884d70b483093f88 Gerrit-Change-Number: 68021 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Oct 2022 16:15:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: Documentation: document the new smbus console feature
by Martin L Roth (Code Review) 03 Oct '22

03 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67386 ) Change subject: Documentation: document the new smbus console feature ...................................................................... Documentation: document the new smbus console feature This explains how to enable the SMBus console in coreboot and its Kconfigs. Change-Id: I50cafbbaaea133c9ea50131e455151287c96176a Signed-off-by: Husni Faiz <ahamedhusni73(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67386 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- A Documentation/technotes/console.md M Documentation/technotes/index.md 2 files changed, 84 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/Documentation/technotes/console.md b/Documentation/technotes/console.md new file mode 100644 index 0000000..8cc5b38 --- /dev/null +++ b/Documentation/technotes/console.md @@ -0,0 +1,66 @@ +# coreboot Console + +coreboot supports multiple ways to access its console. +https://www.coreboot.org/Console_and_outputs + + +## SMBus Console + +SMBus is a two-wire interface which is based on the principles of +operation of I2C. SMBus, was first was designed to allow a battery to +communicate with the charger, the system host, and/or other +power-related components in the system. + +Enable the SMBus console with `CONSOLE_I2C_SMBUS` Kconfig. Set +`CONSOLE_I2C_SMBUS_SLAVE_ADDRESS` and +`CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER` configuration values of the +slave I2C device which you will use to capture I2C packets. + +Modern computer Random Access Memory (RAM) slot has SMBus in it +according to the JEDEC standards. We can use a breakout-board to expose +those SMBus pins. Some mainboard have SMBus pins in the PCIe slot as +well. + +This feature has been tested on the following platforms: +```eval_rst ++------------------------------------+ +| Tested platforms | ++====================================+ +| GA-H61M-S2PV + Intel Ivy Bridge | ++---------------------+--------------- +``` + +A minimal DDR3 DIMM breakout board PCB design with only the +SDA(Data line) and SCL(Clock line) pins of I2C/SMBus can be found +[here](https://github.com/drac98/ram-breakout-board). +See the PCB layout [here](https://archive.org/details/ddr3-dimm-F_Cu) + +NOTE: +To capture the I2C packets, an I2C slave device is required. The easiest +way to capture the log message is to use a I2C to UART converter chip +with a UART to USB converter chip. The setup would be as follows. +```text ++---------+ +-------------+ +-------------+ ++ PC +----+ UART to USB +----+ I2C to UART | ++---------+ +-------------+ +-------------+ + | | +------------------------------------------------+-- System Management +----------------------------------------------+---- Bus +``` + +Watch this [video](https://youtu.be/Q0dK41n9db8) to see how it is set +up. A backup of the video is available +[here](https://web.archive.org/web/20220916172605/https://www.youtube.com/watch?v=Q0dK41n9db8) + +If you are using any of the `SC16IS740/750/760` I2C to UART converter +chip, you can enable the `SC16IS7XX_INIT` option to initialize the chip. + +If not we can use other I2C slave devices like an Arduino or a +Beagleboard. +* [Linux I2C Slave interface](https://web.archive.org/web/20220926173943/https://www.kernel.or… +* [BeagleBone Black I2C Slave](https://web.archive.org/web/20220926171211/https://forum.beagleboard… + +This feature was added as part of a GSoC 2022 project. Checkout the +following blog posts for more details. +* [coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38… +* [coreboot Console via SMBus — Part II](https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324f… diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index fda8bd6..da5b864 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -5,3 +5,4 @@ * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) * [Unit Test Code Coverage](2021-05-code-coverage.md) * [Address Sanitizer](asan.md) +* [coreboot Consoles](console.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/67386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cafbbaaea133c9ea50131e455151287c96176a Gerrit-Change-Number: 67386 Gerrit-PatchSet: 13 Gerrit-Owner: Ahamed Husni <ahamedhusni73(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/skyrim: Update Kconfig to point to SPL
by Jon Murphy (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Jason Nien, Jon Murphy, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Martin Roth, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67928 to look at the new patch set (#11). Change subject: mb/google/skyrim: Update Kconfig to point to SPL ...................................................................... mb/google/skyrim: Update Kconfig to point to SPL ChromeOS requires a custom SPL table. Update Kconfig to point to the ChromeOS version of the SPL resident in the blobs directory. Bug=b:245727030 Test=Boots Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I70dcb19983c970283ee887b78a18c0668e83d4b0 --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/67928/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/67928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70dcb19983c970283ee887b78a18c0668e83d4b0 Gerrit-Change-Number: 67928 Gerrit-PatchSet: 11 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: drivers/smbus: initialize SC16IS7XX I2C to UART converter chip
by Martin L Roth (Code Review) 03 Oct '22

03 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67342 ) Change subject: drivers/smbus: initialize SC16IS7XX I2C to UART converter chip ...................................................................... drivers/smbus: initialize SC16IS7XX I2C to UART converter chip This patch adds the functionality to initialize the sc16is750 i2c to uart converter chip with a 14.7MHz input clock to support 115200 baud rate. Change-Id: Ib31188b8c0f9b0ce9454da984e630eca9101d145 Signed-off-by: Husni Faiz <ahamedhusni73(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67342 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/console/Kconfig M src/drivers/smbus/Makefile.inc M src/drivers/smbus/i2c_smbus_console.c A src/drivers/smbus/sc16is7xx_init.c A src/drivers/smbus/sc16is7xx_init.h 5 files changed, 117 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/console/Kconfig b/src/console/Kconfig index 9b8e9f8..c6aec18 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -311,14 +311,29 @@ config CONSOLE_I2C_SMBUS_SLAVE_ADDRESS hex "I2C slave address of the logging device" + default 0x48 if SC16IS7XX_INIT help I2C address of the device which logs the data. config CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER hex "Data register address of the I2C logging device" + default 0x00 if SC16IS7XX_INIT help This an 8-bit data register. +config SC16IS7XX_INIT + bool "Initialize SC16IS7XX I2C to UART converter chip" + help + SC16IS7XX is a slave I2C to UART converter chip. Enabling + this option will initialize the chip. + + The default I2C slave address value 0x48 is the address of + SC16IS7XX I2C to UART converter chip when the A1 and A0 pins + are set to Vcc. + + The default data register address value 0x00 is the data + register address of SC16IS7XX I2C to UART converter chip. + endif # CONSOLE_I2C_SMBUS config CONSOLE_QEMU_DEBUGCON diff --git a/src/drivers/smbus/Makefile.inc b/src/drivers/smbus/Makefile.inc index e14d59c..d478889 100644 --- a/src/drivers/smbus/Makefile.inc +++ b/src/drivers/smbus/Makefile.inc @@ -1,3 +1,8 @@ +ifeq ($(CONFIG_SC16IS7XX_INIT),y) +bootblock-y += sc16is7xx_init.c +romstage-y += sc16is7xx_init.c +endif + ifeq ($(CONFIG_CONSOLE_I2C_SMBUS),y) all-y += i2c_smbus_console.c endif diff --git a/src/drivers/smbus/i2c_smbus_console.c b/src/drivers/smbus/i2c_smbus_console.c index c223028..d651790 100644 --- a/src/drivers/smbus/i2c_smbus_console.c +++ b/src/drivers/smbus/i2c_smbus_console.c @@ -3,8 +3,13 @@ #include <console/i2c_smbus.h> #include <device/smbus_host.h> #include <southbridge/intel/bd82x6x/pch.h> +#include "sc16is7xx_init.h" -void i2c_smbus_console_init(void) {} +void i2c_smbus_console_init(void) +{ + if (CONFIG(SC16IS7XX_INIT)) + sc16is7xx_init(); +} void i2c_smbus_console_tx_byte(unsigned char c) { diff --git a/src/drivers/smbus/sc16is7xx_init.c b/src/drivers/smbus/sc16is7xx_init.c new file mode 100644 index 0000000..c350b25 --- /dev/null +++ b/src/drivers/smbus/sc16is7xx_init.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/i2c_smbus.h> +#include <device/i2c.h> +#include <device/smbus_host.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include "sc16is7xx_init.h" + +/* + * Datasheet - SC16IS740/750/760, Rev. 7 - 9 June 2011 + * https://web.archive.org/web/20210612105830/https://www.nxp.com/docs/en/data… + */ + +// Bits [6:3] of the subaddress is to address device internal registers +#define INTERNAL_REG_SUB_ADDR_SHIFT 3 + +#define REG_THR 0x00 // Transmit Holding Register +#define REG_LCR 0x03 // Line Control Register + +// Special Register Set is accessible only when LCR[7] is logic 1 +#define REG_DLL 0x00 // divisor latch LSB +#define REG_DLH 0x01 // divisor latch MSB + +#define LCR_WORD_LEN_BIT_0 BIT(0) +#define LCR_WORD_LEN_BIT_1 BIT(1) +#define LCR_STOP_BIT BIT(2) +#define LCR_PARITY_BIT_0 BIT(3) +#define LCR_PARITY_BIT_1 BIT(4) +#define LCR_PARITY_BIT_2 BIT(5) +#define LCR_BREAK_CTL_BIT BIT(6) +#define LCR_SPEC_REG_SET_EN BIT(7) + +#define UART_8_N_1 (LCR_WORD_LEN_BIT_0 | LCR_WORD_LEN_BIT_1) + +/* + * UART configuration: 8 bit word length, No parity, 1 stop bit (8-N-1) + * Divisor value set here is calculated for 115200 baud rate + * in 14.7MHz clock input to chip. + */ + +#define BAUD_115200_DLL 0x08 +#define BAUD_115200_DLH 0x00 + +void sc16is7xx_write_byte(uint8_t reg, unsigned char c) +{ + do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, + CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS, reg, c); +} + +void sc16is7xx_init(void) +{ + // Configure 8-N-1 and enable special register set + sc16is7xx_write_byte(REG_LCR << INTERNAL_REG_SUB_ADDR_SHIFT, + (UART_8_N_1 | LCR_SPEC_REG_SET_EN)); + + sc16is7xx_write_byte(REG_DLL << INTERNAL_REG_SUB_ADDR_SHIFT, BAUD_115200_DLL); + sc16is7xx_write_byte(REG_DLH << INTERNAL_REG_SUB_ADDR_SHIFT, BAUD_115200_DLH); + + // Disable special register set + sc16is7xx_write_byte(REG_LCR << INTERNAL_REG_SUB_ADDR_SHIFT, + (UART_8_N_1 & ~LCR_SPEC_REG_SET_EN)); +} diff --git a/src/drivers/smbus/sc16is7xx_init.h b/src/drivers/smbus/sc16is7xx_init.h new file mode 100644 index 0000000..f57c82a --- /dev/null +++ b/src/drivers/smbus/sc16is7xx_init.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SMBUS_SC16IS7XX_INIT__ +#define __DRIVERS_SMBUS_SC16IS7XX_INIT__ + +#include <types.h> + +void sc16is7xx_write_byte(uint8_t reg, unsigned char c); +void sc16is7xx_init(void); + +#endif /* __DRIVERS_SMBUS_SC16IS7XX_INIT__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/67342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib31188b8c0f9b0ce9454da984e630eca9101d145 Gerrit-Change-Number: 67342 Gerrit-PatchSet: 15 Gerrit-Owner: Ahamed Husni <ahamedhusni73(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: console/die.c: Add <stdarg.h>
by Martin L Roth (Code Review) 03 Oct '22

03 Oct '22

Attention is currently required from: Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68036 ) Change subject: console/die.c: Add <stdarg.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ee8ef017d8a3409cbf47f1ed252a512dead224e Gerrit-Change-Number: 68036 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Oct 2022 16:11:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2022