coreboot-gerrit October 2022

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[S] Change in coreboot[master]: treewide: use helpers to check for enabled pci devices
by Fabio Aiuto (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Stefan Reinauer, Vanessa Eusebio. Fabio Aiuto has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68102 ) Change subject: treewide: use helpers to check for enabled pci devices ...................................................................... treewide: use helpers to check for enabled pci devices use helpers to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83(a)gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 --- M src/arch/x86/mpspec.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c A util/ifdtool/backup-3.rom 11 files changed, 26 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/68102/1 diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 2e65e25..739d185 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -575,7 +575,7 @@ for (dev = all_devices; dev; dev = dev->next) { - if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) + if (!is_enabled_pci(dev)) continue; have_fixed_entries = 0; diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 5c4103d..5a1623f 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -86,7 +86,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 99e3749..d499918 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -436,7 +436,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { uint8_t int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN); diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 1fc1ea3..5d1eda5 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -254,7 +254,7 @@ int8_t original_int_pin = 0, new_int_pin = 0, swiz_int_pin = 0; uint8_t int_line = 0xff; - if (irq_dev->path.type != DEVICE_PATH_PCI || !irq_dev->enabled) { + if (!is_enabled_pci(irq_dev)) { printk(BIOS_ERR, "%s for non pci device?\n", __func__); goto dnv_get_int_line_done; } @@ -380,7 +380,7 @@ int devfn = irq_dev->path.pci.devfn; u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b2e6344..4635189 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -104,7 +104,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a12e36b..4d82706 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -86,7 +86,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 9f70d1f..e39c95a 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -89,7 +89,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e3881ff..41bcccd 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -98,7 +98,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 1735020..d4e3098 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -96,7 +96,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7ae847b..20e40cb 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -120,7 +120,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/util/ifdtool/backup-3.rom b/util/ifdtool/backup-3.rom new file mode 100644 index 0000000..4213f1c --- /dev/null +++ b/util/ifdtool/backup-3.rom Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/68102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Gerrit-Change-Number: 68102 Gerrit-PatchSet: 1 Gerrit-Owner: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: include/device/device_util.c: add helpers to check pci device enabled
by Fabio Aiuto (Code Review) 04 Oct '22

04 Oct '22

Fabio Aiuto has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68101 ) Change subject: include/device/device_util.c: add helpers to check pci device enabled ...................................................................... include/device/device_util.c: add helpers to check pci device enabled add helper functions to check whether a device is enabled pci device or a pci device on a specific bus number. TEST: compile and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83(a)gmail.com> Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 --- M src/device/device_util.c M src/include/device/device.h 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68101/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 0be6cfb..8bba781 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -965,3 +965,18 @@ { return is_cpu(cpu) && cpu->enabled; } + +bool is_pci(const struct device *pci) +{ + return pci->bus->dev->path.type == DEVICE_PATH_PCI; +} + +bool is_enabled_pci(const struct device *pci) +{ + return is_pci(pci) && pci->enabled; +} + +bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus) +{ + return is_pci(pci) && pci->bus->secondary == bus; +} diff --git a/src/include/device/device.h b/src/include/device/device.h index a375639..0f9c39f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -209,6 +209,9 @@ bool is_devfn_enabled(unsigned int devfn); bool is_cpu(const struct device *cpu); bool is_enabled_cpu(const struct device *cpu); +bool is_pci(const struct device *pci); +bool is_enabled_pci(const struct device *pci); +bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus); /* Returns whether there is a hotplug port on the path to the given device. */ extern bool dev_path_hotplug(const struct device *); -- To view, visit https://review.coreboot.org/c/coreboot/+/68101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Gerrit-Change-Number: 68101 Gerrit-PatchSet: 1 Gerrit-Owner: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Host event support of Dynamic Therma...
by EricKY Cheng (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Martin Roth, Tim Van Patten, Moises Garcia, Eric Peers, Karthik Ramasubramanian. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67793 ) Change subject: mb/google/skyrim/var/winterhold: Host event support of Dynamic Thermal Table Switching Proposal ...................................................................... Patch Set 9: Code-Review+1 (2 comments) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/67793/comment/8ecc90d9_281b4c8f PS8, Line 547: #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) > It's not strictly necessary, and the code will work fine if they are all removed (including around t […] Done File src/mainboard/google/skyrim/Kconfig: https://review.coreboot.org/c/coreboot/+/67793/comment/edde07ed_3774ff35 PS8, Line 45: select SOC_AMD_COMMON_BLOCK_ACPI_DPTC > The only concern is regarding testing. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Gerrit-Change-Number: 67793 Gerrit-PatchSet: 9 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 11:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in libgfxinit[master]: dp training: Fix `EQ_Delay` function
by Angel Pons (Code Review) 04 Oct '22

04 Oct '22

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67447 ) Change subject: dp training: Fix `EQ_Delay` function ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Angel, are you able to submit for libgfxinit? I think you should, just checking... Yes, we're pretty sure we can submit stuff. We simply forget about it... -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I18d118ff1bf013175290a1c9fba4d449c7b00cb4 Gerrit-Change-Number: 67447 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 04 Oct 2022 11:24:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/protectli/vault_cml: Add Comet Lake 6 port board support
by Michał Żygowski (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Angel Pons, Piotr Król. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67940 ) Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ...................................................................... Patch Set 12: (1 comment) File src/mainboard/protectli/vault_cml/devicetree.cb: https://review.coreboot.org/c/coreboot/+/67940/comment/0eb0b58c_3b74ec6b PS7, Line 287: device pci 1f.1 on end # P2SB : device pci 1f.2 on end # Power Management Controller > There are some hardware differences between Sunrise/Union Point (SPT is 100 series PCHs, UPT is 200 […] Marked them both as hidden. Is that fine for you? -- To view, visit https://review.coreboot.org/c/coreboot/+/67940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Gerrit-Change-Number: 67940 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 11:19:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: pc80/i8254: Add speaker beep function
by build bot (Jenkins) (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68100 ) Change subject: pc80/i8254: Add speaker beep function ...................................................................... Patch Set 1: (1 comment) File src/drivers/pc80/pc/i8254.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159641): https://review.coreboot.org/c/coreboot/+/68100/comment/d7732c4f_1ee54f51 PS1, Line 129: /* Block for specified miliseconds */ 'miliseconds' may be misspelled - perhaps 'milliseconds'? -- To view, visit https://review.coreboot.org/c/coreboot/+/68100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2 Gerrit-Change-Number: 68100 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 11:18:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/protectli/vault_cml: Add Comet Lake 6 port board support
by Michał Żygowski (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Michał Żygowski, Piotr Król. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67940 ) Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ...................................................................... Patch Set 11: (1 comment) File src/mainboard/protectli/vault_cml/mainboard.c: https://review.coreboot.org/c/coreboot/+/67940/comment/05634643_e3d72500 PS7, Line 72: beep(1500); > Cool, thanks! Made it optional with Kconfig. Additionally implemented the die notify plus separated beep functon in i8254 driver - CB:68100 -- To view, visit https://review.coreboot.org/c/coreboot/+/67940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Gerrit-Change-Number: 67940 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 11:18:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/protectli/vault_cml: Add Comet Lake 6 port board support
by build bot (Jenkins) (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Michał Żygowski, Piotr Król. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67940 ) Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ...................................................................... Patch Set 12: (1 comment) File src/mainboard/protectli/vault_cml/die.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159640): https://review.coreboot.org/c/coreboot/+/67940/comment/96327787_788ddfa9 PS12, Line 12: static uint8_t beep_count = 0;; Statements terminations use 1 semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/67940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Gerrit-Change-Number: 67940 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 11:17:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: pc80/i8254: Add speaker beep function
by Michał Żygowski (Code Review) 04 Oct '22

04 Oct '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68100 ) Change subject: pc80/i8254: Add speaker beep function ...................................................................... pc80/i8254: Add speaker beep function Some platforms have an onboard speaker which could be used as an indicator of successful boot or critical error, e.g. in die_notify function. The function assumes that SPKR GPIO is properly configured by the platform code. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2 --- M src/drivers/pc80/pc/i8254.c M src/include/pc80/i8254.h 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/68100/1 diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 914c9ae..4721059 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -4,6 +4,7 @@ #include <commonlib/helpers.h> #include <cpu/x86/tsc.h> #include <pc80/i8254.h> +#include <delay.h> /* Initialize i8254 timers */ @@ -110,3 +111,24 @@ return timer_tsc; } #endif + +void beep(unsigned int frequency, unsigned int duration_msec) +{ + unsigned int count = CLOCK_TICK_RATE / frequency; + + /* Switch on the speaker */ + outb(inb(PPC_PORTB) | (PPCB_T2GATE | PPCB_SPKR), PPC_PORTB); + + /* Set command for counter 2, 2 byte write, mode 3 */ + outb(TIMER2_SEL | WORD_ACCESS | MODE3, TIMER_MODE_PORT); + + /* Select desired Hz */ + outb(count & 0xff, TIMER2_PORT); + outb((count >> 8) & 0xff, TIMER2_PORT); + + /* Block for specified miliseconds */ + mdelay(duration_msec); + + /* Switch off the speaker */ + outb(inb(PPC_PORTB) & ~(PPCB_T2GATE | PPCB_SPKR), PPC_PORTB); +} diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index a9c0bae..bf4e990 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -43,5 +43,6 @@ void setup_i8254(void); unsigned long calibrate_tsc_with_pit(void); +void beep(unsigned int frequency, unsigned int duration_msec); #endif /* PC80_I8254_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2 Gerrit-Change-Number: 68100 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: mb/protectli/vault_cml: Add Comet Lake 6 port board support
by Michał Żygowski (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Michał Żygowski, Piotr Król. Hello build bot (Jenkins), Angel Pons, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67940 to look at the new patch set (#12). Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ...................................................................... mb/protectli/vault_cml: Add Comet Lake 6 port board support Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/vp46xx.md A Documentation/mainboard/protectli/vp46xx_back.jpg A Documentation/mainboard/protectli/vp46xx_flash.jpg A Documentation/mainboard/protectli/vp46xx_front.jpg A src/mainboard/protectli/vault_cml/Kconfig A src/mainboard/protectli/vault_cml/Kconfig.name A src/mainboard/protectli/vault_cml/Makefile.inc A src/mainboard/protectli/vault_cml/acpi/ec.asl A src/mainboard/protectli/vault_cml/acpi/superio.asl A src/mainboard/protectli/vault_cml/board.fmd A src/mainboard/protectli/vault_cml/board_info.txt A src/mainboard/protectli/vault_cml/bootblock.c A src/mainboard/protectli/vault_cml/cmos.default A src/mainboard/protectli/vault_cml/cmos.layout A src/mainboard/protectli/vault_cml/data.vbt A src/mainboard/protectli/vault_cml/devicetree.cb A src/mainboard/protectli/vault_cml/die.c A src/mainboard/protectli/vault_cml/dsdt.asl A src/mainboard/protectli/vault_cml/gma-mainboard.ads A src/mainboard/protectli/vault_cml/gpio.c A src/mainboard/protectli/vault_cml/gpio.h A src/mainboard/protectli/vault_cml/hda_verb.c A src/mainboard/protectli/vault_cml/mainboard.c A src/mainboard/protectli/vault_cml/romstage.c A src/mainboard/protectli/vault_cml/vboot-rwa.fmd 26 files changed, 1,306 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/67940/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/67940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Gerrit-Change-Number: 67940 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022