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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67833 )
Change subject: Fix "unnecessary with of ancestor [-gnatwr]"
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Most files compile with this, but I'm running into a bug with my host GCC 12:
raised STORAGE_ERROR : stack overflow or erroneous memory access
make: *** [../libhwbase/dest/Makefile:254: build/common/hw-gfx-gma-pch-transcoder.o] Error 1
Does this also happen with the coreboot toolchain?
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/67447 )
Change subject: dp training: Fix `EQ_Delay` function
......................................................................
dp training: Fix `EQ_Delay` function
The DisplayPort v2.0 specification does not mention anything about the
delay being dependent on the link bandwidth.
Change-Id: I18d118ff1bf013175290a1c9fba4d449c7b00cb4
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/67447
Tested-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M common/hw-gfx-dp_training.adb
1 file changed, 17 insertions(+), 2 deletions(-)
Approvals:
Nico Huber: Verified; Looks good to me, approved
diff --git a/common/hw-gfx-dp_training.adb b/common/hw-gfx-dp_training.adb
index d613d85..7b06679 100644
--- a/common/hw-gfx-dp_training.adb
+++ b/common/hw-gfx-dp_training.adb
@@ -310,8 +310,7 @@
function EQ_Delay return Natural is
Result : Natural := 400; -- DP spec: 400us
begin
- if Link.Bandwidth = DP_Bandwidth_5_4 and
- Link.Receiver_Caps.Aux_RD_Interval /= 0
+ if Link.Receiver_Caps.Aux_RD_Interval /= 0
then
Result := Natural (Link.Receiver_Caps.Aux_RD_Interval) * 4_000;
end if;
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Change subject: dp training: Fix `EQ_Delay` function
......................................................................
Patch Set 2: Verified+1 Code-Review+2
(1 comment)
Patchset:
PS2:
Angel, are you able to submit for libgfxinit? I think you should, just checking...
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Nico Huber has uploaded a new patch set (#3) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/libgfxinit/+/67833 )
Change subject: Fix "unnecessary with of ancestor [-gnatwr]"
......................................................................
Fix "unnecessary with of ancestor [-gnatwr]"
These warnings are a bit overeager as some of them only apply once
unnecessary `use type ...` clauses are adapted. So we do both in
one patch. This partially fixes building with GCC 12.
Change-Id: Id7e88fe9a3ef7cb10cbc427a052e21f12578a3fd
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M common/hw-gfx-dp_aux_ch.adb
M common/hw-gfx-edid.adb
M common/hw-gfx-framebuffer_filler.ads
M common/hw-gfx-gma-config_helpers.ads
M common/hw-gfx-gma-registers.ads
M common/hw-gfx-gma.ads
M common/hw-gfx.ads
7 files changed, 18 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/33/67833/3
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68099 )
Change subject: mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPU
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159639):
https://review.coreboot.org/c/coreboot/+/68099/comment/6a3c43ba_4ef05541
PS1, Line 10:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159639):
https://review.coreboot.org/c/coreboot/+/68099/comment/50cc020e_e7859ac0
PS1, Line 12: +-01.0-[01]--
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Hello Angel Pons,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/68099
to review the following change.
Change subject: mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPU
......................................................................
mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPU
An optional dGPU can be connected to the second PEG bridge:
-[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
+-01.0-[01]--
+-01.1-[02]----00.0 NVIDIA Corporation GK208M [GeForce GT 730M]
It's possible that the 01.0 bridge is never populated, but we have to
leave it on anyway so 01.1 can be enumerated.
Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
1 file changed, 21 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/68099/1
diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
index b7588ea..c8772cc 100644
--- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
@@ -23,8 +23,8 @@
subsystemid 0x17aa 0x220e inherit
device pci 00.0 on end # Host bridge
- device pci 01.0 on end # PCIe Bridge for discrete graphics
- device pci 01.1 off end # Unused PCIe Bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics (optional)
+ device pci 01.1 on end # PCIe Bridge for discrete graphics (optional)
device pci 02.0 on end # Internal graphics VGA controller
device pci 03.0 on end # Mini-HD audio
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EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68076 )
Change subject: mb/google/skyrim/var/winterhold: Enable DPTC support for Winterhold
......................................................................
Patch Set 3: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68076/comment/74a79f16_1f6172e1
PS1, Line 8: for Winterhold
> nit: Unless someone else objects, this can be removed since the file name prefix already indicates t […]
Done
https://review.coreboot.org/c/coreboot/+/68076/comment/366e0007_dd026248
PS1, Line 13: TEST=emerge-skyrim coreboot
> Are you booting these devices with these changes also, to ensure the CLs don't break anything?
Hi Tim, I have no idea on how to ensure the CLs don't break anything
File src/mainboard/google/skyrim/Kconfig:
https://review.coreboot.org/c/coreboot/+/68076/comment/030c6402_92971ad0
PS1, Line 39: select SOC_AMD_COMMON_BLOCK_ACPI_DPTC if !BOARD_GOOGLE_MORTHAL
> As Karthik pointed out in another CL, this can be moved to `Kconfig. […]
Done
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67833 )
Change subject: [for test] Fix "unnecessary with of ancestor [-gnatwr]"
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/libgfxinit/+/67833/comment/552b0291_bfab3903
PS2, Line 9: But it failed ...
> The warnings seem to think a little ahead without telling us... There are […]
Thank you
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Change subject: [for test] Fix "unnecessary with of ancestor [-gnatwr]"
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/libgfxinit/+/67833/comment/e2019a12_36816697
PS2, Line 9: But it failed ...
The warnings seem to think a little ahead without telling us... There are
unnecessary `use type ...` clauses and iff we remove those, then the `with`
is also unnecessary.
I'm going to adapt this change to do both at once.
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