coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[master]: mb/protectli/vault_cml: Add Comet Lake 6 port board support
by Angel Pons (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Michał Żygowski, Piotr Król. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67940 ) Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ...................................................................... Patch Set 11: (1 comment) File src/mainboard/protectli/vault_cml/devicetree.cb: https://review.coreboot.org/c/coreboot/+/67940/comment/f4b084a2_083b17bc PS7, Line 287: device pci 1f.1 on end # P2SB : device pci 1f.2 on end # Power Management Controller > Many boards keep it enabled. […] There are some hardware differences between Sunrise/Union Point (SPT is 100 series PCHs, UPT is 200 series PCHs and some rebranded 300 series PCHs supported by AmberLakeFspBinPkg) and Cannon/Comet Point (CNP is most 300 series PCHs, CMP is 400 series PCHs), mainly regarding the PMC and P2SB. In SPT/UPT PCHs (supported by soc/intel/skylake), the P2SB and PMC can be discovered and behave like PCI devices. However, starting with CNP/CMP PCHs (supported by soc/intel/cannonlake) the P2SB and PMC no longer behave like regular PCI devices, and need some special handling. The PMC is not discoverable, and needs to be marked as "hidden" so that coreboot can properly initialize it. Others should be able to explain it better. -- To view, visit https://review.coreboot.org/c/coreboot/+/67940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Gerrit-Change-Number: 67940 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 10:19:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in libhwbase[master]: Fix "unnecessary with of ancestor [-gnatwr]"
by Nico Huber (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Thomas Heijligen, Elyes Haouas. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/67832 ) Change subject: Fix "unnecessary with of ancestor [-gnatwr]" ...................................................................... Patch Set 2: Verified+1 Code-Review+2 (1 comment) Patchset: PS2: Thanks! -- To view, visit https://review.coreboot.org/c/libhwbase/+/67832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I3a8a161a5fd6f8f261d101f1752b452d3706a2df Gerrit-Change-Number: 67832 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 04 Oct 2022 09:46:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/protectli/vault_cml: Add Comet Lake 6 port board support
by Michał Żygowski (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Angel Pons, Piotr Król. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67940 ) Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ...................................................................... Patch Set 11: (1 comment) File src/mainboard/protectli/vault_cml/mainboard.c: https://review.coreboot.org/c/coreboot/+/67940/comment/83cadddf_50614465 PS7, Line 78: * when the screen goes blank/inactive/idle in the OS */ > I am still checking if the newer revisions of the boards still reproduce it. […] Apparently the issue is not present anymore, so I removed the workaround. -- To view, visit https://review.coreboot.org/c/coreboot/+/67940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Gerrit-Change-Number: 67940 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 09:15:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/protectli/vault_cml: Add Comet Lake 6 port board support
by Michał Żygowski (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Angel Pons, Piotr Król. Hello build bot (Jenkins), Angel Pons, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67940 to look at the new patch set (#11). Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support ...................................................................... mb/protectli/vault_cml: Add Comet Lake 6 port board support Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/vp46xx.md A Documentation/mainboard/protectli/vp46xx_back.jpg A Documentation/mainboard/protectli/vp46xx_flash.jpg A Documentation/mainboard/protectli/vp46xx_front.jpg A src/mainboard/protectli/vault_cml/Kconfig A src/mainboard/protectli/vault_cml/Kconfig.name A src/mainboard/protectli/vault_cml/Makefile.inc A src/mainboard/protectli/vault_cml/acpi/ec.asl A src/mainboard/protectli/vault_cml/acpi/superio.asl A src/mainboard/protectli/vault_cml/board.fmd A src/mainboard/protectli/vault_cml/board_info.txt A src/mainboard/protectli/vault_cml/bootblock.c A src/mainboard/protectli/vault_cml/cmos.default A src/mainboard/protectli/vault_cml/cmos.layout A src/mainboard/protectli/vault_cml/data.vbt A src/mainboard/protectli/vault_cml/devicetree.cb A src/mainboard/protectli/vault_cml/dsdt.asl A src/mainboard/protectli/vault_cml/gma-mainboard.ads A src/mainboard/protectli/vault_cml/gpio.c A src/mainboard/protectli/vault_cml/gpio.h A src/mainboard/protectli/vault_cml/hda_verb.c A src/mainboard/protectli/vault_cml/mainboard.c A src/mainboard/protectli/vault_cml/romstage.c A src/mainboard/protectli/vault_cml/vboot-rwa.fmd 25 files changed, 1,284 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/67940/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/67940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Gerrit-Change-Number: 67940 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[L] Change in libgfxinit[master]: common: Begin Tiger Lake integration
by Sean Rhodes (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/65087 ) Change subject: common: Begin Tiger Lake integration ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Tested on StarBook Mk V (i7-1165G7) and no issues found. Seems to break building for older SOCs though: `hw-gfx-gma-power_and_clocks.adb:226:34: "DBUF_CTL" not declared in "Registers"` -- To view, visit https://review.coreboot.org/c/libgfxinit/+/65087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ic8d32598e5611453ce53f1deaeab981b9f2a952f Gerrit-Change-Number: 65087 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 04 Oct 2022 08:49:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz
by Leo Chou (Code Review) 04 Oct '22

04 Oct '22

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68098 ) Change subject: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz ...................................................................... mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz Change the TPM I2C freqeuncy to 1 MHz for pujjo. BUG=b:249953707 TEST=On pujjo, all timing requirements in the spec are met. Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 --- M src/mainboard/google/brya/variants/pujjo/overridetree.cb 1 file changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/68098/1 diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 14164bc..0abc2ab 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -81,11 +81,11 @@ register "common_soc_config" = "{ .i2c[0] = { .early_init = 1, - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST_PLUS, .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 160, - .scl_hcnt = 79, + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, .sda_hold = 7, } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/68098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Gerrit-Change-Number: 68098 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/yaviks: Config I2C frequency
by Wisley Chen (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Kangheui Won, Chen Wisley, Reka Norman, Tim Wawrzynczak, Shou-Chieh Hsu. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68082 ) Change subject: mb/google/nissa/var/yaviks: Config I2C frequency ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/yaviks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68082/comment/920e889e_0c4f941f PS5, Line 46: 55 > I'd recommend increasing this to 56 to reduce the frequency a bit. […] OK,we will revise and measure again. -- To view, visit https://review.coreboot.org/c/coreboot/+/68082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7 Gerrit-Change-Number: 68082 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 07:57:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/ehl: Support maximum memory frequency selection
by build bot (Jenkins) (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Lean Sheng Tan, Werner Zeh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68097 ) Change subject: soc/intel/ehl: Support maximum memory frequency selection ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159635): https://review.coreboot.org/c/coreboot/+/68097/comment/a0352694_915281e4 PS2, Line 13: - Define maximum memory frequency in mainboard devicetree.cb Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28 Gerrit-Change-Number: 68097 Gerrit-PatchSet: 2 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 07:42:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/ehl: Support maximum memory frequency selection
by build bot (Jenkins) (Code Review) 04 Oct '22

04 Oct '22

Attention is currently required from: Lean Sheng Tan, Werner Zeh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68097 ) Change subject: soc/intel/ehl: Support maximum memory frequency selection ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159634): https://review.coreboot.org/c/coreboot/+/68097/comment/29a92be6_12f584ce PS1, Line 13: - Define maximum memory frequency in mainboard devicetree.cb Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28 Gerrit-Change-Number: 68097 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 04 Oct 2022 07:41:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/ehl: Support maximum memory frequency selection
by Christian Gmeiner (Code Review) 04 Oct '22

04 Oct '22

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68097 ) Change subject: soc/intel/ehl: Support maximum memory frequency selection ...................................................................... soc/intel/ehl: Support maximum memory frequency selection Makes it possible to configure the maximum allwed/supported DDR memory frequency on a per mainboard basis. Test - Define maximum memory frequency in mainboard devicetree.cb - Boot into Linux and run 'sudo dmidecode --type 17' to check memory speed - Boot into Linux and run 'phoronix-test-suite benchmark ramspeed' Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/romstage/fsp_params.c 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/68097/1 diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 68810f4..d63844f 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -444,6 +444,16 @@ bool PsePwmPinEn[16]; /* PSE Console Shell */ bool PseShellEn; + + /* + * DDR Frequency Limit + * + * Maximum Memory Frequency Selections in Mhz. + * Values: 1067, 1200, 1333, 1400, 1600, 1800, 1867, 2000, 2133, + * 2200, 2400, 2600, 2667, 2800, 2933, 3000, 3200, 3467, + * 3600, 3733, 4000, 4200, 4267 and 0 for Auto. + */ + uint16_t max_dram_speed_mts; }; typedef struct soc_intel_elkhartlake_config config_t; diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 5c8c995..d2d118a 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -123,6 +123,12 @@ } /* PSE (Intel Programmable Services Engine) switch */ m_cfg->PchPseEnable = CONFIG(PSE_ENABLE) && cbfs_file_exists("pse.bin"); + + /* DDR Frequency Limit */ + if (config->max_dram_speed_mts) { + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + m_cfg->DdrSpeedControl = 1; + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/68097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28 Gerrit-Change-Number: 68097 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022