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Change subject: mb/google/nissa/var/yaviks: Config I2C frequency
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68082/comment/247a9eb7_05ebddf9
PS5, Line 11: I2C0: TPM: 997.7 Khz
: I2C1: Touchscreen: 392.6 Khz
: I2C3: Audio: 394.9 Khz
: I2C5: Touchpad: 391.6 Khz
nit: no need to duplicate these
File src/mainboard/google/brya/variants/yaviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68082/comment/bde877b2_650f3eff
PS5, Line 46: 55
I'd recommend increasing this to 56 to reduce the frequency a bit. This will help ensure it doesn't go over 1 MHz if the rise/fall times vary slightly between devices.
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Change subject: mb/google/brya/var/mithrax: adjust I2C5 times for TP
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Patch Set 5: Code-Review+2
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Change subject: mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_config
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68075/comment/df6e3818_82c17a29
PS1, Line 7: mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on
: fw_config
> nit: please combine these into one line
Done
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Change subject: mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_config
......................................................................
mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_config
BUG=b:250470706
TEST=Boot to OS on pujjo and check that stylus GPIO are
configured based on fw_config.
Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>
Change-Id: I4218748cb06426a918d89f688599c652062ac78c
---
M src/mainboard/google/brya/variants/pujjo/fw_config.c
1 file changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/68075/2
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John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67944 )
Change subject: mb/google/nissa/var/xivu: Add DPTF parameters for Xivu
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> @Ian Feng, what's the reason to keep pl1_min and pl1_max both values to the same 6W ? […]
Hi Sumeet,
From our thermal team feedback, they want to test & import next phase for throttling.
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Change subject: coreboot: Add support for include-what-you-use
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
> Short answer: yes, it can, and it can actually help enforce those rules. […]
Cool, that sounds very promising!
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Change subject: mb/google/brya/var/mithrax: adjust I2C5 times for TP
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67920/comment/aee9ecd4_4287c626
PS4, Line 17: TEST=emerge-brya coreboot chromeos-bootimage
> Could we add some details of what was tested/presumably we confirmed touchpad was still functional? […]
Done
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Change subject: mb/google/brya/var/mithrax: adjust I2C5 times for TP
......................................................................
mb/google/brya/var/mithrax: adjust I2C5 times for TP
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to
follow I2C specification.
I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us.
I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us.
BUG=b:249031186
BRANCH=brya
TEST=EE check OK with test FW and TP function is normal.
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940
---
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
1 file changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/67920/5
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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/brya0: use RPL FSP headers
......................................................................
mb/google/brya/var/brya0: use RPL FSP headers
To support an RPL SKU on brya0, brya0 must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for brya0 so that it will use the RPL
FSP headers for brya0.
BUG=b:248126749
BRANCH=firmware-brya-14505.B
TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
flash and boot brya0 to kernel.
Cq-Depend: chromium:3893035, chrome-internal:4983198
Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/68094/2
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