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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/amd/*: Hook up GPU ops in devicetree
......................................................................
soc/amd/*: Hook up GPU ops in devicetree
This removes the need for a PCI driver.
Change-Id: I4b499013a80f5c1bd6ac265a5ae8e635598d9e6c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/cezanne/chipset.cb
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/mendocino/chipset_mendocino.cb
M src/soc/amd/mendocino/chipset_rembrandt.cb
M src/soc/amd/picasso/chipset.cb
5 files changed, 17 insertions(+), 22 deletions(-)
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Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68147
to look at the new patch set (#6).
Change subject: soc/amd/*: Hook up GPP bridges ops to devicetree
......................................................................
soc/amd/*: Hook up GPP bridges ops to devicetree
This removes the need for a PCI driver.
Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/cezanne/chipset.cb
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/mendocino/chipset_mendocino.cb
M src/soc/amd/mendocino/chipset_rembrandt.cb
M src/soc/amd/picasso/chipset.cb
5 files changed, 51 insertions(+), 60 deletions(-)
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/amd/*: Hook up LPC ops in devicetree
......................................................................
soc/amd/*: Hook up LPC ops in devicetree
This removes the need for a PCI driver.
Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/cezanne/chipset.cb
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/mendocino/chipset_mendocino.cb
M src/soc/amd/mendocino/chipset_rembrandt.cb
M src/soc/amd/picasso/chipset.cb
5 files changed, 17 insertions(+), 19 deletions(-)
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Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68143
to look at the new patch set (#6).
Change subject: soc/amd/cezanne: Use devicetree ops over pci driver
......................................................................
soc/amd/cezanne: Use devicetree ops over pci driver
Cezanne is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.
Change-Id: If535221335217cee53bca956747e7f17f0a5fd8d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/cezanne/chipset.cb
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
3 files changed, 24 insertions(+), 46 deletions(-)
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/amd/sata.c: Hook up directly in devicetree
......................................................................
soc/amd/sata.c: Hook up directly in devicetree
Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/picasso/chipset.cb
2 files changed, 12 insertions(+), 19 deletions(-)
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Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68141
to look at the new patch set (#6).
Change subject: soc/amd/mendocino: Use devicetree ops over pci driver
......................................................................
soc/amd/mendocino: Use devicetree ops over pci driver
Mendocino is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.
Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/mendocino/chipset_mendocino.cb
M src/soc/amd/mendocino/chipset_rembrandt.cb
M src/soc/amd/mendocino/data_fabric.c
M src/soc/amd/mendocino/root_complex.c
4 files changed, 33 insertions(+), 45 deletions(-)
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/amd/*: Hook up smbus ops to devicetree
......................................................................
soc/amd/*: Hook up smbus ops to devicetree
Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/cezanne/chipset.cb
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/mendocino/chipset_mendocino.cb
M src/soc/amd/mendocino/chipset_rembrandt.cb
M src/soc/amd/picasso/chipset.cb
5 files changed, 15 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/68140/5
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Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: soc/amd/picasso: Use devicetree ops over pci driver
......................................................................
soc/amd/picasso: Use devicetree ops over pci driver
Picasso is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.
Change-Id: Ide747c9d386731af89b27630b200676c6e439910
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/picasso/chipset.cb
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
3 files changed, 24 insertions(+), 36 deletions(-)
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
......................................................................
soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
This commit enables GPP clk req disabling for disabled PCIe devices.
Having clk req enabled when the PCIe device is actually disabled may
interfere with the SoC suspending.
BUG=b:250009974
TEST=Ran on skyrim proto device, verified that clk reqs are set
appropriately
Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/mainboard/amd/chausie/Makefile.inc
M src/mainboard/google/skyrim/Makefile.inc
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fch.c
5 files changed, 26 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/68139/3
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Factor out common GPP clk req code
......................................................................
soc/amd/cezanne: Factor out common GPP clk req code
This commit factors out the `gpp_dxio_update_clk_req_config` function
as it will be useful for other AMD SoCs.
BUG=b:250009974
TEST=Ran on nipperkin device, verified clk req settings match enabled
devices
Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
A src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
M src/soc/amd/common/block/pci/Kconfig
M src/soc/amd/common/block/pci/Makefile.inc
A src/soc/amd/common/block/pci/pcie_clk_req.c
M src/soc/amd/common/block/pci/pcie_gpp.c
8 files changed, 143 insertions(+), 94 deletions(-)
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Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newpatchset