coreboot-gerrit October 2022

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[S] Change in coreboot[master]: soc/amd/*: Hook up iommu ops in devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68146 to look at the new patch set (#2). Change subject: soc/amd/*: Hook up iommu ops in devicetree ...................................................................... soc/amd/*: Hook up iommu ops in devicetree This removed the need to maintain a PCI driver. Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/picasso/chipset.cb 5 files changed, 17 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/68146/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d Gerrit-Change-Number: 68146 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/mendocino: Use devicetree ops over pci driver
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68141 to look at the new patch set (#2). Change subject: soc/amd/mendocino: Use devicetree ops over pci driver ...................................................................... soc/amd/mendocino: Use devicetree ops over pci driver Picasso is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/mendocino/data_fabric.c M src/soc/amd/mendocino/root_complex.c 4 files changed, 33 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68141/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211 Gerrit-Change-Number: 68141 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: TESTONLY: Remove non ramstage i2c
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68149 ) Change subject: TESTONLY: Remove non ramstage i2c ...................................................................... TESTONLY: Remove non ramstage i2c Who breaks?? Change-Id: Ib5cc50020904c81ee4927dd33bf168ad8808a202 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/i2c/Makefile.inc M src/soc/intel/common/block/i2c/i2c.c 2 files changed, 14 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68149/1 diff --git a/src/soc/intel/common/block/i2c/Makefile.inc b/src/soc/intel/common/block/i2c/Makefile.inc index db26538..14a6dee 100644 --- a/src/soc/intel/common/block/i2c/Makefile.inc +++ b/src/soc/intel/common/block/i2c/Makefile.inc @@ -1,9 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_I2C),y) -bootblock-y += i2c.c -romstage-y += i2c.c -verstage-y += i2c.c -postcar-y += i2c.c ramstage-y += i2c.c endif diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 481ba7b..3db1435 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -141,13 +141,8 @@ */ static void dw_i2c_device_init(struct device *dev) { - uintptr_t base_address; - int bus = dw_i2c_soc_dev_to_bus(dev); - - if (bus < 0) - return; - - base_address = dw_i2c_base_address(bus); + struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); + uintptr_t base_address = res->base; if (!base_address) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/68149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5cc50020904c81ee4927dd33bf168ad8808a202 Gerrit-Change-Number: 68149 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz
by Reka Norman (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Tim Wawrzynczak, Shou-Chieh Hsu, Leo Chou. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68098 ) Change subject: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Gerrit-Change-Number: 68098 Gerrit-PatchSet: 3 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Oct 2022 20:55:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/lenovo/h8/acpi: Fix wrongly used operator
by build bot (Jenkins) (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Felix Singer, Nico Huber, Sean Rhodes, Alexander Couzens. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66380 ) Change subject: ec/lenovo/h8/acpi: Fix wrongly used operator ...................................................................... Patch Set 3: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159729): https://review.coreboot.org/c/coreboot/+/66380/comment/2873516b_46a04d1f PS3, Line 8: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'Commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax")' -- To view, visit https://review.coreboot.org/c/coreboot/+/66380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa848aafb5480acaac4fabffcf90a3dbf5248e43 Gerrit-Change-Number: 66380 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Wed, 05 Oct 2022 20:53:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Config I2C frequency
by Reka Norman (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Kangheui Won, Chen Wisley, Tim Wawrzynczak, Shou-Chieh Hsu. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68082 ) Change subject: mb/google/nissa/var/yaviks: Config I2C frequency ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7 Gerrit-Change-Number: 68082 Gerrit-PatchSet: 6 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Wed, 05 Oct 2022 20:47:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*: Hook up GPU ops in devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

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[M] Change in coreboot[master]: soc/amd/*: Hook up GPP bridges ops to devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68147 ) Change subject: soc/amd/*: Hook up GPP bridges ops to devicetree ...................................................................... soc/amd/*: Hook up GPP bridges ops to devicetree This removes the need for a PCI driver. Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/common/block/pci/pcie_gpp.c M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/picasso/chipset.cb 5 files changed, 51 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/68147/1 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 1e3b946..3a9bd72 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -13,16 +13,17 @@ device pci 01.3 alias gpp_gfx_bridge_2 off end device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off end - device pci 02.2 alias gpp_bridge_1 off end - device pci 02.3 alias gpp_bridge_2 off end - device pci 02.4 alias gpp_bridge_3 off end - device pci 02.5 alias gpp_bridge_4 off end - device pci 02.6 alias gpp_bridge_5 off end - device pci 02.7 alias gpp_bridge_6 off end + device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -81,12 +82,14 @@ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata_0 off ops amd_sata_ops end # first SATA controller; AHCI Mode device pci 0.1 alias sata_1 off ops amd_sata_ops end # second SATA Controller; SATA Raid/AHCI Mode device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) end device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + ops amd_internal_pcie_gpp_ops device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio end diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 2e37935..0ce3268 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -7,7 +7,6 @@ #include <assert.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pciexp.h> #include <soc/pci_devs.h> #include <stdio.h> @@ -48,7 +47,7 @@ acpigen_pop_len(); /* Scope */ } -static struct device_operations internal_pcie_gpp_ops = { +struct device_operations amd_internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -58,21 +57,7 @@ .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; -static const unsigned short internal_pci_gpp_ids[] = { - PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, - PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, - PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, - PCI_DID_AMD_FAM17H_MODELA0H_PCIE_GPP_BUSABC, - 0 -}; - -static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { - .ops = &internal_pcie_gpp_ops, - .vendor = PCI_VID_AMD, - .devices = internal_pci_gpp_ids, -}; - -static struct device_operations external_pcie_gpp_ops = { +struct device_operations amd_external_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -81,17 +66,3 @@ .acpi_name = pcie_gpp_acpi_name, .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; - -static const unsigned short external_pci_gpp_ids[] = { - PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP, - PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1, - PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2, - PCI_DID_AMD_FAM17H_MODELA0H_PCIE_GPP, - 0 -}; - -static const struct pci_driver external_pcie_gpp_driver __pci_driver = { - .ops = &external_pcie_gpp_ops, - .vendor = PCI_VID_AMD, - .devices = external_pci_gpp_ids, -}; diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 3715306..139ee84 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -10,15 +10,16 @@ device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off end - device pci 02.2 alias gpp_bridge_1 off end - device pci 02.3 alias gpp_bridge_2 off end - device pci 02.4 alias gpp_bridge_3 off end - device pci 02.5 alias gpp_bridge_4 off end - device pci 02.6 alias gpp_bridge_5 off end + device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -65,7 +66,9 @@ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index b81890f..e000f40 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -10,15 +10,16 @@ device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off end - device pci 02.2 alias gpp_bridge_1 off end - device pci 02.3 alias gpp_bridge_2 off end - device pci 02.4 alias gpp_bridge_3 off end - device pci 02.5 alias gpp_bridge_4 off end - device pci 02.6 alias gpp_bridge_5 off end + device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -64,8 +65,8 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B + device pci 08.3 alias gpp_bridge_c ops amd_internal_pcie_gpp_ops off # Internal GPP Bridge 2 to Bus C device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID end diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index 9a69189..756a7f4 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -9,15 +9,16 @@ device pci 00.0 alias gnb on ops picasso_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end device pci 01.0 on end # Dummy Host Bridge, do not disable - device pci 01.1 alias gpp_bridge_0 off end - device pci 01.2 alias gpp_bridge_1 off end - device pci 01.3 alias gpp_bridge_2 off end - device pci 01.4 alias gpp_bridge_3 off end - device pci 01.5 alias gpp_bridge_4 off end - device pci 01.6 alias gpp_bridge_5 off end - device pci 01.7 alias gpp_bridge_6 off end + device pci 01.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 01.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 01.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 01.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 01.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias internal_bridge_a off # internal bridge to bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # internal GPU device pci 0.1 alias gfx_hda off end # display HD Audio controller device pci 0.2 alias crypto off end # cryptography coprocessor @@ -28,6 +29,7 @@ device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) end device pci 08.2 alias internal_bridge_b off # internal bridge to bus B + ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata off ops amd_sata_ops end device pci 0.1 alias xgbe_0 off end device pci 0.2 alias xgbe_1 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/68147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d Gerrit-Change-Number: 68147 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*: Hook up iommu ops in devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

1 0

[S] Change in coreboot[master]: soc/amd/acp: Hook up ops in devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

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coreboot-gerrit October 2022