coreboot-gerrit October 2022

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[S] Change in coreboot[master]: mb/google/brya/var/brya0: use RPL FSP headers
by Nick Vaccaro (Code Review) 05 Oct '22

05 Oct '22

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68094 ) Change subject: mb/google/brya/var/brya0: use RPL FSP headers ...................................................................... mb/google/brya/var/brya0: use RPL FSP headers To support an RPL SKU on brya0, brya0 must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for brya0 so that it will use the RPL FSP headers for brya0. BUG=b:248126749 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot brya0 to kernel. Cq-Depend: chromium:3893035, chrome-internal:4983198 Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68094 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved YH Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index df94b20..b19bdc5 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -37,6 +37,7 @@ config BOARD_GOOGLE_BRYA0 bool "-> Brya 0" select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU -- To view, visit https://review.coreboot.org/c/coreboot/+/68094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e Gerrit-Change-Number: 68094 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field
by Nick Vaccaro (Code Review) 05 Oct '22

05 Oct '22

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68025 ) Change subject: mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field ...................................................................... mb/google/brya/var/brya0: add new THERMAL FW_CONFIG field Add a new THERMAL FW_CONFIG bitfield for describing power consumption category of SoC. BUG=b:250089101 TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0 and skolas to kernel. Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb 2 files changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved YH Lin: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 63ec9a1..8decc06 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -37,6 +37,10 @@ option HPS_ABSENT 0 option HPS_PRESENT 1 end + field THERMAL 18 18 + option THERMAL_28W 0 + option THERMAL_15W 1 + end end chip soc/intel/alderlake diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index bcc66f8..110ca42 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -37,6 +37,10 @@ option HPS_ABSENT 0 option HPS_PRESENT 1 end + field THERMAL 18 18 + option THERMAL_28W 0 + option THERMAL_15W 1 + end end chip soc/intel/alderlake -- To view, visit https://review.coreboot.org/c/coreboot/+/68025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Gerrit-Change-Number: 68025 Gerrit-PatchSet: 5 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG
by Nick Vaccaro (Code Review) 05 Oct '22

05 Oct '22

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67929 ) Change subject: mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG ...................................................................... mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIG 1) Make the skolas FW_CONFIG field defintions compatible with the brya0 FW_CONFIG field definitions to support skolas being a SKU of brya0, and in sync with the config.star definitions for the FW_CONFIG field for brya0 and skolas. - brya0 specific changes: 1) remove WFC_MIPI_OVTI5675 definition (was 1) 2) redefine WFC_MIPI_OVTI8856 from 2 to 1 3) define new WFC_MIPI_KBAE350 camera type as 2 - skolas specific changes: 1) remove WFC_MIPI_OVTI5675 definition (was 1) 2) redefine WFC_MIPI_OVTI8856 from 2 to 1 3) define new WFC_MIPI_KBAE350 camera type as 2 2) Add support back in for UFC_MIPI_OVTI5675 in brya0 now that FW_CONFIG defines are fixed. BUG=b:248126749 TEST="emerge-brya coreboot chromeos-bootimage", flash brya0 and verify it boots successfully to kernel and that WFC, UFC, and audio works on skolas and brya0. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67929 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb 2 files changed, 208 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 74884d4..63ec9a1 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -30,8 +30,8 @@ end field WFC 15 16 option WFC_ABSENT 0 - option WFC_MIPI_OVTI5675 1 - option WFC_MIPI_OVTI8856 2 + option WFC_MIPI_OVTI8856 1 + option WFC_MIPI_KBAE350 2 end field HPS 17 17 option HPS_ABSENT 0 @@ -379,7 +379,9 @@ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 10 on end + device i2c 10 on + probe WFC WFC_MIPI_OVTI8856 + end end chip drivers/intel/mipi_camera register "acpi_uid" = "2" @@ -390,7 +392,9 @@ register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9768"" - device i2c 0C on end + device i2c 0C on + probe WFC WFC_MIPI_OVTI8856 + end end chip drivers/intel/mipi_camera register "acpi_uid" = "1" @@ -406,7 +410,84 @@ register "nvm_readonly" = "0x01" register "nvm_width" = "0x10" - device i2c 58 on end + device i2c 58 on + probe WFC WFC_MIPI_OVTI8856 + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360 * MHz" # 360 MHz + register "link_freq[1]" = "180 * MHz" # 180 MHz + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on + probe WFC WFC_MIPI_KBAE350 + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on + probe WFC WFC_MIPI_KBAE350 + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c08"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x10" + + device i2c 50 on + probe WFC WFC_MIPI_KBAE350 + end end end #I2C0 device ref i2c1 on diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index 41effb6..bcc66f8 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -30,8 +30,8 @@ end field WFC 15 16 option WFC_ABSENT 0 - option WFC_MIPI_OVTI5675 1 - option WFC_MIPI_OVTI8856 2 + option WFC_MIPI_OVTI8856 1 + option WFC_MIPI_KBAE350 2 end field HPS 17 17 option HPS_ABSENT 0 @@ -379,7 +379,84 @@ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 36 on end + device i2c 10 on + probe WFC WFC_MIPI_OVTI8856 + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9768 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9768"" + + device i2c 0C on + probe WFC WFC_MIPI_OVTI8856 + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""AT24 EEPROM"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x10" + + device i2c 58 on + probe WFC WFC_MIPI_OVTI8856 + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360 * MHz" # 360 MHz + register "link_freq[1]" = "180 * MHz" # 180 MHz + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on + probe WFC WFC_MIPI_KBAE350 + end end chip drivers/intel/mipi_camera register "acpi_uid" = "2" @@ -390,7 +467,9 @@ register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" - device i2c 0C on end + device i2c 0C on + probe WFC WFC_MIPI_KBAE350 + end end chip drivers/intel/mipi_camera register "acpi_uid" = "1" @@ -406,7 +485,9 @@ register "nvm_readonly" = "0x01" register "nvm_width" = "0x10" - device i2c 50 on end + device i2c 50 on + probe WFC WFC_MIPI_KBAE350 + end end end #I2C0 device ref i2c1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/67929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859 Gerrit-Change-Number: 67929 Gerrit-PatchSet: 6 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Ofer Fried <oferfried(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/variant/brya0: Add power limits for RPL SoC
by Nick Vaccaro (Code Review) 05 Oct '22

05 Oct '22

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67880 ) Change subject: mb/google/brya/variant/brya0: Add power limits for RPL SoC ...................................................................... mb/google/brya/variant/brya0: Add power limits for RPL SoC Add the RPL CPU power limits to brya0's power limit table to support both the brya0 ADL sku and the new RPL sku. BUG=b:248126749 TEST="emerge-brya coreboot chromeos-bootimage", flash skolas with image-brya0.serial.bin and verify skolas boots successfully to kernel. Change-Id: I2ac067f98f1ff8f86cff0ed0e15010f454d9c91c Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67880 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/ramstage.c 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/ramstage.c b/src/mainboard/google/brya/variants/brya0/ramstage.c index 970c628..2aa9ec8 100644 --- a/src/mainboard/google/brya/variants/brya0/ramstage.c +++ b/src/mainboard/google/brya/variants/brya0/ramstage.c @@ -11,6 +11,10 @@ { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, + /* Following values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, }; void variant_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/67880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ac067f98f1ff8f86cff0ed0e15010f454d9c91c Gerrit-Change-Number: 67880 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: MAINTAINERS: Update maintainers for several Google projects
by Tarun Tuli (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Noga Smith, Caveh Jalali, Boris Mittelberg. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67289 ) Change subject: MAINTAINERS: Update maintainers for several Google projects ...................................................................... Patch Set 5: (1 comment) File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/67289/comment/b059087d_ac4274c4 PS4, Line 568: caveh(a)google.com > actually, shouldn't this be caveh@chromium. […] yup if you prefer that, ive updated it. -- To view, visit https://review.coreboot.org/c/coreboot/+/67289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973b0abf8a82189df1495e3bcd9bae452a5be827 Gerrit-Change-Number: 67289 Gerrit-PatchSet: 5 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Noga Smith <nogasmith(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 05 Oct 2022 19:04:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: MAINTAINERS: Update maintainers for several Google projects
by Caveh Jalali (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Noga Smith, Tarun Tuli, Boris Mittelberg. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67289 ) Change subject: MAINTAINERS: Update maintainers for several Google projects ...................................................................... Patch Set 4: -Code-Review (1 comment) File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/67289/comment/68e9460e_c5d246cb PS4, Line 568: caveh(a)google.com actually, shouldn't this be caveh(a)chromium.org? -- To view, visit https://review.coreboot.org/c/coreboot/+/67289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973b0abf8a82189df1495e3bcd9bae452a5be827 Gerrit-Change-Number: 67289 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Noga Smith <nogasmith(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 05 Oct 2022 19:02:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: MAINTAINERS: Update maintainers for several Google projects
by Caveh Jalali (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Noga Smith, Tarun Tuli, Boris Mittelberg. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67289 ) Change subject: MAINTAINERS: Update maintainers for several Google projects ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973b0abf8a82189df1495e3bcd9bae452a5be827 Gerrit-Change-Number: 67289 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Noga Smith <nogasmith(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 05 Oct 2022 18:55:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: MAINTAINERS: Update maintainers for several Google projects
by Tarun Tuli (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Noga Smith, Caveh Jalali, Boris Mittelberg. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67289 ) Change subject: MAINTAINERS: Update maintainers for several Google projects ...................................................................... Patch Set 4: (1 comment) File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/67289/comment/2d464fae_27d19fc9 PS2, Line 567: S: Maintained > Add owner Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973b0abf8a82189df1495e3bcd9bae452a5be827 Gerrit-Change-Number: 67289 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Noga Smith <nogasmith(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 05 Oct 2022 18:32:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by build bot (Jenkins) (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... Patch Set 48: (32 comments) File payloads/cbui/NuklearUI/NuklearDatePicker.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/57519c29_f2c2c61a PS48, Line 36: case 6: /* fallthrough */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/92a77e65_d7e51dcd PS48, Line 37: case 9: /* fallthrough */ Prefer 'fallthrough;' over fallthrough comment File payloads/cbui/NuklearUI/NuklearRW.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/beb648f5_96ffc2d5 PS48, Line 247: static const char *titles[] = { "Hex-View", "Header", "Index/Data" }; static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/7c773eac_f1d314f6 PS48, Line 281: static const char *entries[] = { "NVRAM" }; static const char * array should probably be static const char * const File payloads/cbui/arch/x86/int32.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/40d834b5_dd0048d2 PS48, Line 20: typedef struct __attribute__ ((packed)) { Prefer __packed over __attribute__((packed)) File payloads/cbui/arch/x86/int32.nasm: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/7c0f5062_45533f94 PS48, Line 38: struc regs16_t 'struc' may be misspelled - perhaps 'struct'? File payloads/cbui/gfx/vbe.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/375473df_7744ac39 PS48, Line 24: static u8 low_mem[0x1000] __attribute__ ((section(".lowmem"))); Prefer __section(".lowmem") over __attribute__((section(".lowmem"))) File payloads/cbui/lang/de.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/70dea133_30d9e8c7 PS48, Line 39: "Kein Framebuffer gefunden. CBUI funktioniert nicht" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/7f114a86_38ab2fc3 PS48, Line 44: "Der coreboot framebuffer hat keine physikalische " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/492d775d_7ef978cd PS48, Line 47: "Kein Platz auf dem Heap.\nBitte vergroBere den" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/df439de4_6f93ef31 PS48, Line 50: "Konnte die nuklear Bibliothek nicht intitialisieren.\nBitte" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/e0dffe04_0efaf519 PS48, Line 52: "stelle sicher, das der Framebuffer entweder das RGBX8 oder " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/da7e4fb2_6a9c5a62 PS48, Line 65: "Fehler: Keine CMOS Eintrage gefunden. Bitte schalte die " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/c7f6b1ef_3edeae34 PS48, Line 86: "Fehler: Keine Zeitstempel gefunden. Bitte schalte die " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/f4043a95_8f02a1e5 PS48, Line 89: "Fehler: Bootlog nicht gefunden. Bitte schalte die Kconfig " \ Avoid unnecessary line continuations File payloads/cbui/lang/en.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/b9318fde_621628b8 PS48, Line 38: "No framebuffer found. CBUI doesn't work in text mode.\n" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/bcd4f021_3bb6c09b PS48, Line 46: "Failed to init nuklear library.\nMake sure you have enough " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/21840f1a_7269e201 PS48, Line 60: "ERROR: No CMOS options found. Please make sure to enable " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/3805d271_31f69a53 PS48, Line 81: "ERROR: No timestamps found. Please make sure to enable " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/ef4da02c_b937955c PS48, Line 84: "ERROR: Bootlog not found. Please make sure to enable " \ Avoid unnecessary line continuations File payloads/cbui/modules/bootlog_module.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/14c6ceaa_6b43a525 PS48, Line 28: } __attribute__ ((__packed__)); Prefer __packed over __attribute__((__packed__)) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/455bf682_22953c11 PS48, Line 82: } void function return statements are not generally useful File payloads/cbui/modules/cbfs_module.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/2a4e8ec2_6ff7f986 PS48, Line 50: } __attribute__ ((packed)); Prefer __packed over __attribute__((packed)) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/020969e9_1bcc0dc4 PS48, Line 59: } __attribute__ ((packed)); Prefer __packed over __attribute__((packed)) File payloads/cbui/modules/cpuinfo_module.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/67eb0623_aa7fa0ea PS48, Line 35: static const char *intel_cap_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/44d48bf2_7609e0d9 PS48, Line 43: static const char *amd_cap_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/940a117e_8f07cd91 PS48, Line 51: static const char *intel_cap_ecx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/cc44a8a7_5f706ee0 PS48, Line 59: static const char *amd_cap_ecx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/f9358977_9b604ee2 PS48, Line 67: static const char *intel_cap_extended_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/9ecafadc_59a42701 PS48, Line 75: static const char *intel_cap_extended_ecx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/e43b2e59_9ada2688 PS48, Line 83: static const char *amd_cap_extended_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159710): https://review.coreboot.org/c/coreboot/+/23586/comment/78b61b0f_54a40095 PS48, Line 92: static const char *amd_cap_extended_ecx_flags[] = { static const char * array should probably be static const char * const -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 48 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 Oct 2022 18:12:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#48) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearPciHeader.c A payloads/cbui/NuklearUI/NuklearPciHeader.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 88 files changed, 12,349 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/48 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 48 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022