coreboot-gerrit October 2022

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[S] Change in coreboot[master]: soc/amd/*: Hook up LPC ops in devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68144 ) Change subject: soc/amd/*: Hook up LPC ops in devicetree ...................................................................... soc/amd/*: Hook up LPC ops in devicetree This removes the need for a PCI driver. Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/picasso/chipset.cb 5 files changed, 17 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/68144/1 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 8271d24..3190cc7 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -92,7 +92,7 @@ end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function - device pci 14.3 alias lpc_bridge on end + device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end device pci 18.0 alias data_fabric_0 on ops cezanne_data_fabric_ops end device pci 18.1 alias data_fabric_1 on ops cezanne_data_fabric_ops end diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 3d1b2d4..26e0c26 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pnp.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> @@ -319,7 +318,7 @@ } #endif -static struct device_operations lpc_ops = { +struct device_operations amd_lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, @@ -331,16 +330,3 @@ .scan_bus = scan_static_bus, .ops_pci = &pci_dev_ops_pci, }; - -static const unsigned short pci_device_ids[] = { - /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ - PCI_DID_AMD_SB900_LPC, - /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ - PCI_DID_AMD_CZ_LPC, - 0 -}; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VID_AMD, - .devices = pci_device_ids, -}; diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 06c5db2..876b09e 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -70,7 +70,7 @@ end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function - device pci 14.3 alias lpc_bridge on end + device pci 14.3 alias lpc_bridge on ops amd_lpc_opsend device pci 18.0 alias data_fabric_0 on ops mendocino_data_fabric_ops end device pci 18.1 alias data_fabric_1 on ops mendocino_data_fabric_ops end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 441db75..04fb8be 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -70,7 +70,7 @@ end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function - device pci 14.3 alias lpc_bridge on end + device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end device pci 18.0 alias data_fabric_0 on ops mendocino_data_fabric_ops end device pci 18.1 alias data_fabric_1 on ops mendocino_data_fabric_ops end diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index 6fcfd41..c1959dc 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -33,7 +33,7 @@ device pci 0.2 alias xgbe_1 off end end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function - device pci 14.3 alias lpc_bridge on end + device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end device pci 14.6 alias sdhci off end device pci 18.0 alias data_fabric_0 on ops picasso_data_fabric_ops end device pci 18.1 alias data_fabric_1 on ops picasso_data_fabric_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/68144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d Gerrit-Change-Number: 68144 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/cezanne: Use devicetree ops over pci driver
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68143 ) Change subject: soc/amd/cezanne: Use devicetree ops over pci driver ...................................................................... soc/amd/cezanne: Use devicetree ops over pci driver Picasso is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: If535221335217cee53bca956747e7f17f0a5fd8d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/cezanne/data_fabric.c M src/soc/amd/cezanne/root_complex.c 3 files changed, 24 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/68143/1 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index d975fcf..8271d24 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -4,7 +4,7 @@ end device domain 0 on ops cezanne_pci_domain_ops - device pci 00.0 alias gnb on end + device pci 00.0 alias gnb on ops cezanne_root_complex_operations end device pci 00.2 alias iommu off end device pci 01.0 on end # Dummy Host Bridge, do not disable @@ -94,14 +94,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on end - device pci 18.0 alias data_fabric_0 on end - device pci 18.1 alias data_fabric_1 on end - device pci 18.2 alias data_fabric_2 on end - device pci 18.3 alias data_fabric_3 on end - device pci 18.4 alias data_fabric_4 on end - device pci 18.5 alias data_fabric_5 on end - device pci 18.6 alias data_fabric_6 on end - device pci 18.7 alias data_fabric_7 on end + device pci 18.0 alias data_fabric_0 on ops cezanne_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops cezanne_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops cezanne_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops cezanne_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops cezanne_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops cezanne_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops cezanne_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops cezanne_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c index 43894e9..336b7eb 100644 --- a/src/soc/amd/cezanne/data_fabric.c +++ b/src/soc/amd/cezanne/data_fabric.c @@ -7,7 +7,6 @@ #include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <soc/data_fabric.h> #include <soc/iomap.h> #include <types.h> @@ -132,37 +131,9 @@ return NULL; } -static struct device_operations data_fabric_ops = { +struct device_operations cezanne_data_fabric_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .acpi_name = data_fabric_acpi_name, .acpi_fill_ssdt = acpi_device_write_pci_dev, }; - -static const unsigned short pci_device_ids[] = { - /* Renoir DF devices */ - PCI_DID_AMD_FAM17H_MODEL60H_DF0, - PCI_DID_AMD_FAM17H_MODEL60H_DF1, - PCI_DID_AMD_FAM17H_MODEL60H_DF2, - PCI_DID_AMD_FAM17H_MODEL60H_DF3, - PCI_DID_AMD_FAM17H_MODEL60H_DF4, - PCI_DID_AMD_FAM17H_MODEL60H_DF5, - PCI_DID_AMD_FAM17H_MODEL60H_DF6, - PCI_DID_AMD_FAM17H_MODEL60H_DF7, - /* Cezanne DF devices */ - PCI_DID_AMD_FAM19H_MODEL51H_DF0, - PCI_DID_AMD_FAM19H_MODEL51H_DF1, - PCI_DID_AMD_FAM19H_MODEL51H_DF2, - PCI_DID_AMD_FAM19H_MODEL51H_DF3, - PCI_DID_AMD_FAM19H_MODEL51H_DF4, - PCI_DID_AMD_FAM19H_MODEL51H_DF5, - PCI_DID_AMD_FAM19H_MODEL51H_DF6, - PCI_DID_AMD_FAM19H_MODEL51H_DF7, - 0 -}; - -static const struct pci_driver data_fabric_driver __pci_driver = { - .ops = &data_fabric_ops, - .vendor = PCI_VID_AMD, - .devices = pci_device_ids, -}; diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 8ea5c9f..ed919b1 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -11,7 +11,6 @@ #include <cpu/amd/msr.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <fsp/util.h> #include <soc/iomap.h> #include <stdint.h> @@ -206,7 +205,7 @@ return "GNB"; } -static struct device_operations root_complex_operations = { +struct device_operations cezanne_root_complex_operations = { .read_resources = read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, @@ -214,9 +213,3 @@ .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; - -static const struct pci_driver family17_root_complex __pci_driver = { - .ops = &root_complex_operations, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_17H_MODEL_606F_NB, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/68143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If535221335217cee53bca956747e7f17f0a5fd8d Gerrit-Change-Number: 68143 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/sata.c: Hook up directly in devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

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[M] Change in coreboot[master]: soc/amd/mendocino: Use devicetree ops over pci driver
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68141 ) Change subject: soc/amd/mendocino: Use devicetree ops over pci driver ...................................................................... soc/amd/mendocino: Use devicetree ops over pci driver Picasso is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/mendocino/data_fabric.c M src/soc/amd/mendocino/root_complex.c 4 files changed, 33 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68141/1 diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 3f0d2f2..06c5db2 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -4,7 +4,7 @@ end device domain 0 on ops mendocino_pci_domain_ops - device pci 00.0 alias gnb on end + device pci 00.0 alias gnb on mendocino_root_complex_operations end device pci 00.2 alias iommu off end device pci 01.0 on end # Dummy Host Bridge @@ -72,14 +72,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on end - device pci 18.0 alias data_fabric_0 on end - device pci 18.1 alias data_fabric_1 on end - device pci 18.2 alias data_fabric_2 on end - device pci 18.3 alias data_fabric_3 on end - device pci 18.4 alias data_fabric_4 on end - device pci 18.5 alias data_fabric_5 on end - device pci 18.6 alias data_fabric_6 on end - device pci 18.7 alias data_fabric_7 on end + device pci 18.0 alias data_fabric_0 on ops mendocino_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops mendocino_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops mendocino_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops mendocino_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops mendocino_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops mendocino_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops mendocino_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops mendocino_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 31499b8..441db75 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -4,7 +4,7 @@ end device domain 0 on ops mendocino_pci_domain_ops - device pci 00.0 alias gnb on end + device pci 00.0 alias gnb on ops mendocino_root_complex_operations end device pci 00.2 alias iommu off end device pci 01.0 on end # Dummy Host Bridge @@ -72,14 +72,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on end - device pci 18.0 alias data_fabric_0 on end - device pci 18.1 alias data_fabric_1 on end - device pci 18.2 alias data_fabric_2 on end - device pci 18.3 alias data_fabric_3 on end - device pci 18.4 alias data_fabric_4 on end - device pci 18.5 alias data_fabric_5 on end - device pci 18.6 alias data_fabric_6 on end - device pci 18.7 alias data_fabric_7 on end + device pci 18.0 alias data_fabric_0 on ops mendocino_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops mendocino_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops mendocino_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops mendocino_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops mendocino_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops mendocino_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops mendocino_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops mendocino_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/mendocino/data_fabric.c b/src/soc/amd/mendocino/data_fabric.c index 0a39959..4195ac0 100644 --- a/src/soc/amd/mendocino/data_fabric.c +++ b/src/soc/amd/mendocino/data_fabric.c @@ -9,7 +9,6 @@ #include <cpu/x86/lapic_def.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <soc/data_fabric.h> #include <soc/iomap.h> #include <types.h> @@ -127,27 +126,9 @@ return NULL; } -static struct device_operations data_fabric_ops = { +struct device_operations mendocino_data_fabric_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .acpi_name = data_fabric_acpi_name, .acpi_fill_ssdt = acpi_device_write_pci_dev, }; - -static const unsigned short pci_device_ids[] = { - PCI_DID_AMD_FAM17H_MODELA0H_DF0, - PCI_DID_AMD_FAM17H_MODELA0H_DF1, - PCI_DID_AMD_FAM17H_MODELA0H_DF2, - PCI_DID_AMD_FAM17H_MODELA0H_DF3, - PCI_DID_AMD_FAM17H_MODELA0H_DF4, - PCI_DID_AMD_FAM17H_MODELA0H_DF5, - PCI_DID_AMD_FAM17H_MODELA0H_DF6, - PCI_DID_AMD_FAM17H_MODELA0H_DF7, - 0 -}; - -static const struct pci_driver data_fabric_driver __pci_driver = { - .ops = &data_fabric_ops, - .vendor = PCI_VID_AMD, - .devices = pci_device_ids, -}; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 7f54bde..6768613 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -13,7 +13,6 @@ #include <cpu/amd/msr.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <fsp/util.h> #include <soc/iomap.h> #include <stdint.h> @@ -236,7 +235,7 @@ return "GNB"; } -static struct device_operations root_complex_operations = { +struct device_operations mendocino_root_complex_operations = { .read_resources = read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, @@ -244,9 +243,3 @@ .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; - -static const struct pci_driver family17_root_complex __pci_driver = { - .ops = &root_complex_operations, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_17H_MODEL_A0AF_NB, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/68141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211 Gerrit-Change-Number: 68141 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*: Hook up smbus ops to devicetree
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

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[M] Change in coreboot[master]: soc/amd/picasso: Use devicetree ops over pci driver
by Arthur Heymans (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67743 to look at the new patch set (#4). Change subject: soc/amd/picasso: Use devicetree ops over pci driver ...................................................................... soc/amd/picasso: Use devicetree ops over pci driver Picasso is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: Ide747c9d386731af89b27630b200676c6e439910 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/chipset.cb M src/soc/amd/picasso/data_fabric.c M src/soc/amd/picasso/root_complex.c 3 files changed, 24 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/67743/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/67743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide747c9d386731af89b27630b200676c6e439910 Gerrit-Change-Number: 67743 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/cezanne: Factor out common GPP clk req code
by Robert Zieba (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68138 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Factor out common GPP clk req code ...................................................................... soc/amd/cezanne: Factor out common GPP clk req code This commit factors out the `gpp_dxio_update_clk_req_config` function as it will be useful for other AMD SoCs. BUG=b:250009974 TEST=Ran on nipperkin device, verified clk req settings match enabled devices Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c A src/soc/amd/common/block/include/amdblocks/pci_gpp.h M src/soc/amd/common/block/pci/pcie_gpp.c 4 files changed, 126 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/68138/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Gerrit-Change-Number: 68138 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/cezanne: Factor out common GPP clk req code
by build bot (Jenkins) (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68138 ) Change subject: soc/amd/cezanne: Factor out common GPP clk req code ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/include/amdblocks/pci_gpp.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159715): https://review.coreboot.org/c/coreboot/+/68138/comment/62fe524c_8ff25ad1 PS1, Line 17: #endif adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/68138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Gerrit-Change-Number: 68138 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 Oct 2022 20:22:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
by Robert Zieba (Code Review) 05 Oct '22

05 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68139 ) Change subject: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices ...................................................................... soc/amd/mendocino: Enable GPP clk req disabling for disabled devices This commit enables GPP clk req disabling for disabled PCIe devices. Having clk req enabled when the PCIe device is actually disabled may interfere with the SoC suspending. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/mainboard/amd/chausie/Makefile.inc M src/mainboard/google/skyrim/Makefile.inc M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fch.c 4 files changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/68139/1 diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc index 2560886..98b2cdd 100644 --- a/src/mainboard/amd/chausie/Makefile.inc +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -8,6 +8,7 @@ ramstage-y += chromeos.c ramstage-y += gpio.c +ramstage-y += port_descriptors.c ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin),) APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index ba175a2..9eb1e46 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += mainboard.c ramstage-y += ec.c +ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 0e656f5..dcd3c70 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -7,6 +7,7 @@ #include <amdblocks/chip.h> #include <amdblocks/i2c.h> +#include <amdblocks/pci_gpp.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -92,11 +93,7 @@ /* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* performance policy for the PCIe links: power consumption vs. link speed */ enum { diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index e86cd31..a04cd1b 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/pci_gpp.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -130,7 +131,7 @@ /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_mendocino_config *cfg = config_of_soc(); + struct soc_amd_mendocino_config *cfg = config_of_soc(); /* look-up table to be able to iterate over the PCIe clock output settings */ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { @@ -145,6 +146,7 @@ uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/68139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Gerrit-Change-Number: 68139 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/cezanne: Factor out common GPP clk req code
by Robert Zieba (Code Review) 05 Oct '22

05 Oct '22

Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68138 ) Change subject: soc/amd/cezanne: Factor out common GPP clk req code ...................................................................... soc/amd/cezanne: Factor out common GPP clk req code This commit factors out the `gpp_dxio_update_clk_req_config` function as it will be useful for other AMD SoCs. BUG=b:250009974 TEST=Ran on nipperkin device, verified clk req settings match enabled devices Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c A src/soc/amd/common/block/include/amdblocks/pci_gpp.h M src/soc/amd/common/block/pci/pcie_gpp.c 4 files changed, 126 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/68138/1 diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 00eb560..14d4a4d 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -5,6 +5,7 @@ #include <amdblocks/chip.h> #include <amdblocks/i2c.h> +#include <amdblocks/pci_gpp.h> #include <gpio.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -12,12 +13,6 @@ #include <types.h> #include <vendorcode/amd/fsp/cezanne/FspUsb.h> -enum gpp_clk_req { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ -}; - struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index b791037..5009fc6 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -3,6 +3,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/pci_gpp.h> #include <amdblocks/gpio.h> #include <amdblocks/i2c.h> #include <amdblocks/smi.h> @@ -134,93 +135,6 @@ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); } -/* Update gpp glk req config based on DXIO descriptors and enabled devices. */ -static void gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, - size_t gpp_clk_config_num) -{ - const fsp_dxio_descriptor *dxio_descs = NULL; - const fsp_ddi_descriptor *ddi_descs = NULL; - size_t dxio_num = 0; - size_t ddi_num = 0; - - mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num); - if (dxio_descs == NULL) { - printk(BIOS_WARNING, - "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n"); - return; - } - - for (int i = 0; i < dxio_num; i++) { - const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i]; - - /* Only consider PCIe and unused engine types. */ - if (dxio_desc->engine_type != PCIE_ENGINE - && dxio_desc->engine_type != UNUSED_ENGINE) - continue; - enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req; - - /* CLK_DISABLE means there's no corresponding clk req line in use */ - if (dxio_clk_req == CLK_DISABLE) - continue; - - /* - * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for - * a descriptor should cause a compiler error. 0xF isn't a - * valid clk_req value according to AMD's internal code either. - * This is here to draw attention in case this code is ever used - * in a situation where this has changed. - */ - if (dxio_clk_req == (CLK_ENABLE & 0xF)) { - printk(BIOS_WARNING, - "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i); - continue; - } - - /* cpm_clk_req 0 is CLK_DISABLE */ - int gpp_req_index = dxio_clk_req - CLK_REQ0; - /* Ensure that our index is valid */ - if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) { - printk(BIOS_ERR, "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n", - dxio_clk_req, dxio_desc->device_number, - dxio_desc->function_number, i); - continue; - } - - const struct device *pci_device = pcidev_path_on_root( - PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number)); - if (pci_device == NULL) { - gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; - printk(BIOS_WARNING, - "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i, - gpp_req_index); - continue; - } - - /* PCIe devices haven't been fully set up yet, so directly read the vendor id - * and device id to determine if a device is physically present. If a device - * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000, - * and 0x0000ffff are there to account for any odd failure cases. */ - u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID); - bool enabled = pci_device->enabled && (id != 0xffffffff) && - (id != 0x00000000) && (id != 0x0000ffff) && (id != 0xffff0000); - - /* Inform of possible mismatches between devices and SoC gpp_clk_config. */ - if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) { - gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; - printk(BIOS_INFO, - "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, - gpp_req_index, i); - } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) { - printk(BIOS_INFO, - "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i); - } - } -} - /* Configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -239,7 +153,7 @@ uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); diff --git a/src/soc/amd/common/block/include/amdblocks/pci_gpp.h b/src/soc/amd/common/block/include/amdblocks/pci_gpp.h new file mode 100644 index 0000000..e205883 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/pci_gpp.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_PCI_GPP_H +#define AMD_BLOCK_PCI_GPP_H + +#include <soc/platform_descriptors.h> + +enum gpp_clk_req { + GPP_CLK_ON, /* GPP clock always on; default */ + GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ + GPP_CLK_OFF, /* GPP clk off */ +}; + +void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, + size_t gpp_clk_config_num); + +#endif \ No newline at end of file diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 2e37935..a222bdb 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -4,12 +4,14 @@ #include <acpi/acpigen.h> #include <acpi/acpigen_pci.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/pci_gpp.h> #include <assert.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pciexp.h> #include <soc/pci_devs.h> +#include <soc/platform_descriptors.h> #include <stdio.h> #include <stdlib.h> @@ -48,6 +50,93 @@ acpigen_pop_len(); /* Scope */ } +/* Update gpp glk req config based on DXIO descriptors and enabled devices. */ +void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, + size_t gpp_clk_config_num) +{ + const fsp_dxio_descriptor *dxio_descs = NULL; + const fsp_ddi_descriptor *ddi_descs = NULL; + size_t dxio_num = 0; + size_t ddi_num = 0; + + mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num); + if (dxio_descs == NULL) { + printk(BIOS_WARNING, + "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n"); + return; + } + + for (int i = 0; i < dxio_num; i++) { + const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i]; + + /* Only consider PCIe and unused engine types. */ + if (dxio_desc->engine_type != PCIE_ENGINE + && dxio_desc->engine_type != UNUSED_ENGINE) + continue; + enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req; + + /* CLK_DISABLE means there's no corresponding clk req line in use */ + if (dxio_clk_req == CLK_DISABLE) + continue; + + /* + * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for + * a descriptor should cause a compiler error. 0xF isn't a + * valid clk_req value according to AMD's internal code either. + * This is here to draw attention in case this code is ever used + * in a situation where this has changed. + */ + if (dxio_clk_req == (CLK_ENABLE & 0xF)) { + printk(BIOS_WARNING, + "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i); + continue; + } + + /* cpm_clk_req 0 is CLK_DISABLE */ + int gpp_req_index = dxio_clk_req - CLK_REQ0; + /* Ensure that our index is valid */ + if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) { + printk(BIOS_ERR, "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n", + dxio_clk_req, dxio_desc->device_number, + dxio_desc->function_number, i); + continue; + } + + const struct device *pci_device = pcidev_path_on_root( + PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number)); + if (pci_device == NULL) { + gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; + printk(BIOS_WARNING, + "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i, + gpp_req_index); + continue; + } + + /* PCIe devices haven't been fully set up yet, so directly read the vendor id + * and device id to determine if a device is physically present. If a device + * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000, + * and 0x0000ffff are there to account for any odd failure cases. */ + u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID); + bool enabled = pci_device->enabled && (id != 0xffffffff) && + (id != 0x00000000) && (id != 0x0000ffff) && (id != 0xffff0000); + + /* Inform of possible mismatches between devices and SoC gpp_clk_config. */ + if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) { + gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; + printk(BIOS_INFO, + "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, + gpp_req_index, i); + } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) { + printk(BIOS_INFO, + "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i); + } + } +} + static struct device_operations internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/68138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Gerrit-Change-Number: 68138 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newchange

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