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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68116 )
Change subject: mb/google/skyrim: Override SPI flash bus speed
......................................................................
Patch Set 1: Code-Review+2
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Iman Bingi has uploaded a new patch set (#46) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 )
Change subject: payloads/cbui: Add new payload CBUI
......................................................................
payloads/cbui: Add new payload CBUI
Depends on libpayload and nuklear.
Features:
* Graphical menus with scrolling.
* Text rendering engine (atm only bitmap font)
* Support for keyboard and mouse
* Support for USB and PS/2 devices
* Ported coreinfo and nvramcui
* Allows to modify NVRAM and RTC
* Works as ELF payload
* Works as Seabios secondary payload
* Basic support for multiple languages
* Hacky support for BIOS calls (depends on NASM)
* Runs in qemu and on real hardware
* Use linker script to allocate low memory
Shortcomings:
* Doesn't work in VGA text mode
* Untested on UEFI
* int32 relocates itself to low memory
Licenses:
* GPLv2 (CBUI + libpayload)
* BSD (libpayload)
* MIT (nuklear)
TODO:
* Test on as much platforms as possible
* Link int32 into low memory
This is Patrick Rudolph's original patch, updated by
Ben Adu-Boahen to:
* Add Read/Write module
* This module allows read/write to any hardware
component that is readable/writeable
Note:
This is work in progress
Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com>
---
M payloads/Kconfig
M payloads/Makefile.inc
A payloads/cbui/.gitignore
A payloads/cbui/Kconfig
A payloads/cbui/Makefile
A payloads/cbui/NuklearUI/NuklearCombo.c
A payloads/cbui/NuklearUI/NuklearCombo.h
A payloads/cbui/NuklearUI/NuklearCommon.h
A payloads/cbui/NuklearUI/NuklearDataGrid.c
A payloads/cbui/NuklearUI/NuklearDataGrid.h
A payloads/cbui/NuklearUI/NuklearDatePicker.c
A payloads/cbui/NuklearUI/NuklearDatePicker.h
A payloads/cbui/NuklearUI/NuklearFieldHex.c
A payloads/cbui/NuklearUI/NuklearFieldHex.h
A payloads/cbui/NuklearUI/NuklearFileChooser.c
A payloads/cbui/NuklearUI/NuklearFileChooser.h
A payloads/cbui/NuklearUI/NuklearGroup.c
A payloads/cbui/NuklearUI/NuklearGroup.h
A payloads/cbui/NuklearUI/NuklearHex.c
A payloads/cbui/NuklearUI/NuklearHex.h
A payloads/cbui/NuklearUI/NuklearIntegerRange.c
A payloads/cbui/NuklearUI/NuklearIntegerRange.h
A payloads/cbui/NuklearUI/NuklearLabel.c
A payloads/cbui/NuklearUI/NuklearLabel.h
A payloads/cbui/NuklearUI/NuklearObject.c
A payloads/cbui/NuklearUI/NuklearObject.h
A payloads/cbui/NuklearUI/NuklearPciHeader.c
A payloads/cbui/NuklearUI/NuklearPciHeader.h
A payloads/cbui/NuklearUI/NuklearRW.c
A payloads/cbui/NuklearUI/NuklearRW.h
A payloads/cbui/NuklearUI/NuklearRoot.c
A payloads/cbui/NuklearUI/NuklearStyle.c
A payloads/cbui/NuklearUI/NuklearStyle.h
A payloads/cbui/NuklearUI/NuklearTabView.c
A payloads/cbui/NuklearUI/NuklearTextView.c
A payloads/cbui/NuklearUI/NuklearTextView.h
A payloads/cbui/NuklearUI/NuklearTextfield.c
A payloads/cbui/NuklearUI/NuklearTextfield.h
A payloads/cbui/NuklearUI/NuklearTimePicker.c
A payloads/cbui/NuklearUI/NuklearTimePicker.h
A payloads/cbui/NuklearUI/NuklearUI.h
A payloads/cbui/NuklearUI/NuklearVector.c
A payloads/cbui/NuklearUI/NuklearVector.h
A payloads/cbui/arch/x86/cpuid.c
A payloads/cbui/arch/x86/cpuid.h
A payloads/cbui/arch/x86/int32.h
A payloads/cbui/arch/x86/int32.ld
A payloads/cbui/arch/x86/int32.nasm
A payloads/cbui/arch/x86/memcpy.c
A payloads/cbui/arch/x86/memcpy.h
A payloads/cbui/arch/x86/vga.c
A payloads/cbui/arch/x86/vga.h
A payloads/cbui/cbui.c
A payloads/cbui/cbui.h
A payloads/cbui/fsys/usbstorage.c
A payloads/cbui/fsys/usbstorage.h
A payloads/cbui/gfx/coreboot.c
A payloads/cbui/gfx/coreboot.h
A payloads/cbui/gfx/gfx.c
A payloads/cbui/gfx/gfx.h
A payloads/cbui/gfx/splash.c
A payloads/cbui/gfx/splash.h
A payloads/cbui/gfx/vbe.c
A payloads/cbui/gfx/vbe.h
A payloads/cbui/lang/de.c
A payloads/cbui/lang/en.c
A payloads/cbui/lang/lang.c
A payloads/cbui/lang/lang.h
A payloads/cbui/logo/cbui.png
A payloads/cbui/lp.config
A payloads/cbui/modules/bootlog_module.c
A payloads/cbui/modules/cbfs_module.c
A payloads/cbui/modules/cmos_module.c
A payloads/cbui/modules/coreboot_module.c
A payloads/cbui/modules/cpuinfo_module.c
A payloads/cbui/modules/license_module.c
A payloads/cbui/modules/modules.c
A payloads/cbui/modules/modules.h
A payloads/cbui/modules/nvram_module.c
A payloads/cbui/modules/pci_module.c
A payloads/cbui/modules/reboot_module.c
A payloads/cbui/modules/rtc_module.c
A payloads/cbui/modules/rw_module.c
A payloads/cbui/modules/timestamps_module.c
A payloads/cbui/modules/usb_module.c
A payloads/libpayload/configs/defconfig-cbui
86 files changed, 12,126 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/46
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67833 )
Change subject: Fix "unnecessary with of ancestor [-gnatwr]"
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> got a same error with gcc-12: […]
Do you have any ideas? It seems to be a problem with the compiler.
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63868 )
Change subject: util/superiotool/nuvoton.c: Add NCT6687D-W register definitions
......................................................................
Patch Set 6:
(1 comment)
File util/superiotool/superiotool.c:
https://review.coreboot.org/c/coreboot/+/63868/comment/d29074fa_e68462d9
PS5, Line 22: /* For Nuvoton EC space */
> Probably Nuvoton-specific.
Moved set_page and dump_page_index_data to nuvoton.c
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Hello build bot (Jenkins), Krystian Hebel, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63868
to look at the new patch set (#6).
Change subject: util/superiotool/nuvoton.c: Add NCT6687D-W register definitions
......................................................................
util/superiotool/nuvoton.c: Add NCT6687D-W register definitions
Based on public NCT6686D hardware datasheet revision 0.5 which should
be similar to NCT6687D.
TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895
---
M util/superiotool/nuvoton.c
1 file changed, 196 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/63868/6
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Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68101 )
Change subject: include/device/device_util.c: add predicates for pci devices
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
thanks for catching this Angel
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Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68133 )
Change subject: util/chromeos/gen_test_hwid.sh: Replace usage of hexdump
......................................................................
util/chromeos/gen_test_hwid.sh: Replace usage of hexdump
Hexdump command is not available in coreboot-sdk. Replace it with
equivalent implementation using commands that are present in the
container.
TEST=Passed "VP46XX" as prefix variable and it produced the same
crc32 result before and after the change.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Icad93933335b8c5ebd8fee74cc9aaed36bb56482
---
M util/chromeos/gen_test_hwid.sh
1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/68133/1
diff --git a/util/chromeos/gen_test_hwid.sh b/util/chromeos/gen_test_hwid.sh
index 9dfbce5..5599806 100755
--- a/util/chromeos/gen_test_hwid.sh
+++ b/util/chromeos/gen_test_hwid.sh
@@ -13,7 +13,7 @@
local prefix="$(echo "${board}" | tr a-z A-Z) TEST"
# gzip has second-to-last 4 bytes in CRC32.
local crc32="$(printf "${prefix}" | gzip -1 | tail -c 8 | head -c 4 | \
- hexdump -e '1/4 "%04u" ""' | tail -c 4)"
+ od -An -vtu4 | xargs | tr -d '\n' | tail -c 4)"
echo "${prefix}" "${crc32}"
}
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67940 )
Change subject: mb/protectli/vault_cml: Add Comet Lake 6 port board support
......................................................................
Patch Set 16:
(7 comments)
File src/mainboard/protectli/vault_cml/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/67940/comment/40603c72_c3646191
PS7, Line 287: device pci 1f.1 on end # P2SB
: device pci 1f.2 on end # Power Management Controller
> > Marked them both as hidden. Is that fine for you? […]
It still works. I don't think having these devices set to 'ON' had anything to do with those issues, as these devices were simply not visible at all. In fact, I recall not including the VBT actually helped, so I could have a buggy VBT earlier.
File src/mainboard/protectli/vault_cml/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/67940/comment/4a1403bd_a260f258
PS13, Line 55: register "SataMode" = "0"
> This should be dropped too. SATA mode should be a Kconfig option instead, anyway.
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/1845cf7a_167a5640
PS13, Line 67: register "PcieRpEnable[13]" = "1"
: register "PcieRpEnable[14]" = "1"
: register "PcieRpEnable[15]" = "1"
> As root port 13 (array index 12) is x4, these three root ports do not have any lanes associated to t […]
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/d9818a92_e787a0fa
PS13, Line 80: register "PcieRpAdvancedErrorReporting[13]" = "1"
: register "PcieRpAdvancedErrorReporting[14]" = "1"
: register "PcieRpAdvancedErrorReporting[15]" = "1"
> Same as above
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/c2cdb44d_ed9981b2
PS13, Line 93: register "PcieRpLtrEnable[13]" = "1"
: register "PcieRpLtrEnable[14]" = "1"
: register "PcieRpLtrEnable[15]" = "1"
> Same as above
Done
https://review.coreboot.org/c/coreboot/+/67940/comment/27f7703c_7b799d07
PS13, Line 202: device pci 1d.5 on end # PCI Express Port 14
: device pci 1d.6 on end # PCI Express Port 15
: device pci 1d.7 on end # PCI Express Port 16
> Same as the FSP settings. These root ports have no lanes associated to them (`device pci 1d. […]
Done
File src/mainboard/protectli/vault_cml/die.c:
https://review.coreboot.org/c/coreboot/+/67940/comment/65ace1e2_7d0e6a08
PS13, Line 12: static uint8_t beep_count = 0;;
> > Statements terminations use 1 semicolon […]
Done
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