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Hello Nico Huber, Sean Rhodes, Angel Pons,
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to look at the new patch set (#7).
Change subject: hw-gfx-gma: Update BDSM register offset for TGL onwards
......................................................................
hw-gfx-gma: Update BDSM register offset for TGL onwards
BDSM moved and is also 64 bits on TGL. If the register indicates
that BSDM is 64-bits, then right now libgfxinit will error out.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I0a3e7a92dcb08ea33e08c9f2c5135d4269c9e0b9
---
M common/hw-gfx-gma.adb
1 file changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/78/65178/7
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Hello Nico Huber, Sean Rhodes, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: common: Begin Tiger Lake integration
......................................................................
common: Begin Tiger Lake integration
Tiger Lake's integrated graphics engine is built off an entirely new
igfx architecture named "Iris Xe". This patch adds just enough support
to compile for Tiger Lake. Fortunately, the backlight programming
hasn't changed since SKL, so with a little bit of hacking, one can
also have libgfxinit turn on the backlight to verify something is
working and running.
The first pass through the support will focus mostly on the eDP panel,
then Type-C ports (both in fixed/native mode [DP/HDMI] and in Type-C
DP Alt Mode). TBT will not be mostly ignored in this first pass, as
it is not as widely used (yet?) as the other protocols.
Tested on google/voxel, with DEBUG_ADA_CODE enabled.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ic8d32598e5611453ce53f1deaeab981b9f2a952f
---
M common/Makefile.inc
M common/hw-gfx-gma-config.ads.template
M common/hw-gfx-gma-config_helpers.adb
M common/hw-gfx-gma.adb
M common/hw-gfx-gma.ads
A common/tigerlake/Makefile.inc
A common/tigerlake/hw-gfx-gma-connectors.adb
A common/tigerlake/hw-gfx-gma-plls.adb
A common/tigerlake/hw-gfx-gma-plls.ads
A common/tigerlake/hw-gfx-gma-port_detect.adb
A common/tigerlake/hw-gfx-gma-power_and_clocks.adb
A common/tigerlake/hw-gfx-gma-power_and_clocks.ads
A configs/tigerlake
13 files changed, 542 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/87/65087/9
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68133 )
Change subject: util/chromeos/gen_test_hwid.sh: Replace usage of hexdump
......................................................................
Patch Set 1:
(1 comment)
File util/chromeos/gen_test_hwid.sh:
https://review.coreboot.org/c/coreboot/+/68133/comment/29fea5cb_4c4117e2
PS1, Line 16: xargs
Not sure what the xargs is supposed to do here? Looks good otherwise.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66561 )
Change subject: cbfs/vboot: Adapt to new vb2_digest API
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> somehow this broke my google/vilboz. No console at all on the PSP verstage. […]
Sorry, wouldn't know why. PSP verstage should print some log output before this code even runs so it doesn't sound likely that this patch alone directly caused that kind of issue. (I assume you have one of the AMD/Google-internal devices with unlocked PSP? Because my understanding is that the PSP verstage binary is normally signed by AMD and cannot be replaced on retail devices. If you tried to do that that would explain why it doesn't boot, but then it should fail with any local build of coreboot, not related to this patch.)
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Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68150 )
Change subject: mb/google/nissa/var/yaviks: Support STORAGE_UNPROVISIONED fw_config
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68150/comment/14f07c38_8d37d58c
PS1, Line 13: TEST
TODO: need to test
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Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68150 )
Change subject: mb/google/nissa/var/yaviks: Support STORAGE_UNPROVISIONED fw_config
......................................................................
mb/google/nissa/var/yaviks: Support STORAGE_UNPROVISIONED fw_config
When set to STORAGE_UNPROVISIONED, coreboot will enable all storage
devices. This is used for the first boot in factory.
BUG=b:251055188
TEST=Boot to OS on yaviks eMMC and UFS SKUs with fw_config set to
STORAGE_UNPROVISIONED.
Change-Id: I500d82d15e3240f1983c0bbaa6167b28bef2ab18
Signed-off-by: Reka Norman <rekanorman(a)chromium.org>
---
M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
M src/mainboard/google/brya/variants/yaviks/overridetree.cb
2 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/68150/1
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index d002db6..5a8ce26 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -3,6 +3,7 @@
option STORAGE_EMMC 0
option STORAGE_NVME 1
option STORAGE_UFS 2
+ option STORAGE_UNPROVISIONED 3
end
end
diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index e30cc06..83ad4c3 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -189,12 +189,15 @@
end
device ref emmc on
probe STORAGE STORAGE_EMMC
+ probe STORAGE STORAGE_UNPROVISIONED
end
device ref ish on
probe STORAGE STORAGE_UFS
+ probe STORAGE STORAGE_UNPROVISIONED
end
device ref ufs on
probe STORAGE STORAGE_UFS
+ probe STORAGE STORAGE_UNPROVISIONED
end
device ref pch_espi on
chip ec/google/chromeec
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66380 )
(
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: ec/lenovo/h8/acpi: Fix wrongly used operator
......................................................................
ec/lenovo/h8/acpi: Fix wrongly used operator
Commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0
syntax") mixed up boolean and bit-wise operators while replacing Not()
with ASL 2.0 syntax. Thus, fix that.
Built dsdt.aml of lenovo/x230 and differs, but it remains the same when
this commit is applied after commit 37a89d519d4e.
Change-Id: Ifa848aafb5480acaac4fabffcf90a3dbf5248e43
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66380
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/ec/lenovo/h8/acpi/thinkpad.asl
1 file changed, 22 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl
index 7c56106..622521a 100644
--- a/src/ec/lenovo/h8/acpi/thinkpad.asl
+++ b/src/ec/lenovo/h8/acpi/thinkpad.asl
@@ -91,7 +91,7 @@
}
Else
{
- DHKN = DHKN & !Local0
+ DHKN = DHKN & ~Local0
}
If (EN)
{
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Factor out common GPP clk req code
......................................................................
soc/amd/cezanne: Factor out common GPP clk req code
This commit factors out the `gpp_dxio_update_clk_req_config` function
as it will be useful for other AMD SoCs.
BUG=b:250009974
TEST=Ran on nipperkin device, verified clk req settings match enabled
devices
Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
A src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
M src/soc/amd/common/block/pci/Kconfig
M src/soc/amd/common/block/pci/Makefile.inc
A src/soc/amd/common/block/pci/pcie_clk_req.c
M src/soc/amd/common/block/pci/pcie_gpp.c
8 files changed, 143 insertions(+), 94 deletions(-)
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Change subject: ec/lenovo/h8/acpi: Fix wrongly used operator
......................................................................
ec/lenovo/h8/acpi: Fix wrongly used operator
Commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0
syntax") mixed up boolean and bit-wise operators while replacing Not()
with ASL 2.0 syntax. Thus, fix that.
Built dsdt.aml of lenovo/x230 and differs, but it remains the same when
this commit is applied after commit 37a89d519d4e.
Change-Id: Ifa848aafb5480acaac4fabffcf90a3dbf5248e43
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/ec/lenovo/h8/acpi/thinkpad.asl
1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/66380/7
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66380 )
Change subject: ec/lenovo/h8/acpi: Fix wrongly used operator
......................................................................
Patch Set 6: Verified-1
(2 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159782):
https://review.coreboot.org/c/coreboot/+/66380/comment/e5e210f2_1c1fbee3
PS6, Line 8:
Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'Commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax")'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159782):
https://review.coreboot.org/c/coreboot/+/66380/comment/c62a65b2_429daf86
PS6, Line 13: Built dsdt.aml of lenovo/x230 and differs, but it remains the same when
Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax")'
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