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Change subject: cpu/amd/family15: Use parallel_mp init
......................................................................
Patch Set 30:
(1 comment)
File src/soc/amd/common/block/cpu/smm/smm_relocate.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159835):
https://review.coreboot.org/c/coreboot/+/64892/comment/cb6c766b_908caca6
PS30, Line 221: restore_aseg_mtrr();
code indent should use tabs where possible
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Change subject: mb/starlabs/starbook/tgl: Enable P2SB
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/starlabs/starbook/tgl: Disable XDCI
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/starlabs/starbook/tgl: Use chipset.cb aliases
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/67027/comment/13789065_ccbd2c9c
PS1, Line 88: device ref north_xhci on
nit: one tab too many
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Angel Pons, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64892
to look at the new patch set (#30).
Change subject: cpu/amd/family15: Use parallel_mp init
......................................................................
cpu/amd/family15: Use parallel_mp init
This now computes an MTRR solution based on coreboots allocation and
always uses that solution over the one set by AGESA.
Syncing MSR is now done in sipi_vector.S.
This also implements SMM in ASEG in the helper functions as some AGESA
targets have an SMI handler.
TESTED on ASUS F2A85-M PRO.
Change-Id: I33a5f93e3c2777fffb47400dfab9eedd774d3b2b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/amd/agesa/Kconfig
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/include/cpu/amd/msr.h
M src/northbridge/amd/agesa/family15tn/Kconfig
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/soc/amd/common/block/cpu/smm/smm_relocate.c
6 files changed, 149 insertions(+), 195 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/64892/30
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Change subject: mb/starlabs/starbook/tgl: Use chipset.cb aliases
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
File src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/67027/comment/e7eb52b8_50715a15
PS3, Line 88: device ref south_xhci on
nit: one tab too many
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Change subject: mainboard/starlabs/starbook: Update the EC binaries for StarLabs
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mainboard/starlabs/starbook: Update the EC binaries for StarLabs
......................................................................
Patch Set 4:
(1 comment)
File mainboard/starlabs/starbook/adl/README.md:
https://review.coreboot.org/c/blobs/+/68016/comment/5912e8fa_3f6a2171
PS2, Line 6: ITE128
> It's just a way to differentiate the ones that span 128k in different blocks.
Ack, thanks
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Change subject: cpu/amd/pi00730F01: Use common code for mp_init
......................................................................
Patch Set 25: Code-Review+1
(1 comment)
Patchset:
PS24:
> > Maybe 3mdeb can test this? […]
The coreboot 4.18 release is slated to happen ~now, so if this hasn't been tested it would be best to wait until the release is done. In the meantime, 3mdeb can test it if they want.
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