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Change subject: cpu/amd/family15: Use parallel_mp init
......................................................................
Patch Set 28: Code-Review+1
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Change subject: cpu/amd/family16: Use parallel mp init
......................................................................
Patch Set 27: Code-Review+1
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Change subject: cpu/amd/family14: Use parallel mp init
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Patch Set 27: Code-Review+1
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Change subject: cpu/amd/pi00730F01: Use common code for mp_init
......................................................................
Patch Set 24: Code-Review+1
(1 comment)
Patchset:
PS24:
Maybe 3mdeb can test this?
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Change subject: mb/google/dedede/var/beadrix: Update SoC gpio pin of USB camera
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/tigerlake/Kconfig: Change PCIEXBAR location
......................................................................
Patch Set 2: -Code-Review
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64892
to look at the new patch set (#28).
Change subject: cpu/amd/family15: Use parallel_mp init
......................................................................
cpu/amd/family15: Use parallel_mp init
This now computes an MTRR solution based on coreboots allocation and
always uses that solution over the one set by AGESA.
Syncing MSR is now done in sipi_vector.S.
This also implements SMM in ASEG in the helper functions as some AGESA
targets have an SMI handler.
TESTED on ASUS F2A85-M PRO.
Change-Id: I33a5f93e3c2777fffb47400dfab9eedd774d3b2b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/amd/agesa/Kconfig
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/include/cpu/amd/msr.h
M src/northbridge/amd/agesa/family15tn/Kconfig
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/soc/amd/common/block/cpu/smm/smm_relocate.c
6 files changed, 93 insertions(+), 194 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/64892/28
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: cpu/amd/family16: Use parallel mp init
......................................................................
cpu/amd/family16: Use parallel mp init
This now computes an MTRR solution based on coreboots allocation and
always uses that solution over the one set by AGESA.
Syncing MSR is now done in sipi_vector.S.
Change-Id: If3326c5fbd278f8f974d5408e16440e3b56b1b44
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/northbridge/amd/agesa/family16kb/Kconfig
M src/northbridge/amd/agesa/family16kb/northbridge.c
3 files changed, 44 insertions(+), 170 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/64496/27
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#27).
Change subject: cpu/amd/family14: Use parallel mp init
......................................................................
cpu/amd/family14: Use parallel mp init
This now computes an MTRR solution based on coreboots allocation and
always uses that solution over the one set by AGESA.
Syncing MSR is now done in sipi_vector.S.
TESTED: Works on pcengines/apu1 and fixes inconsistent MTRR warning by Linux.
Change-Id: I73a866462b0cb6fcaeb0a47eef7a1b16747240fb
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/amd/agesa/Makefile.inc
M src/cpu/amd/agesa/family14/model_14_init.c
M src/northbridge/amd/agesa/family14/Kconfig
M src/northbridge/amd/agesa/family14/northbridge.c
M src/soc/amd/common/block/cpu/smm/smm_relocate.c
5 files changed, 94 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/64495/27
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Change subject: mb/google/brya: Update devicetree setting for lisbon
......................................................................
mb/google/brya: Update devicetree setting for lisbon
update devicetree setting per the schematic
BUG=b:246657849
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
Change-Id: I4268a5b43690a22bb703337fed84b83c45da4ad2
---
M src/mainboard/google/brya/variants/lisbon/overridetree.cb
1 file changed, 322 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/68165/2
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