coreboot-gerrit October 2022

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[M] Change in coreboot[master]: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail
by Lean Sheng Tan (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66616 ) Change subject: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Gerrit-Change-Number: 66616 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Oct 2022 18:00:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: sb/intel/common/early_smbus.h: Add <device/pci_type.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68047 ) Change subject: sb/intel/common/early_smbus.h: Add <device/pci_type.h> ...................................................................... sb/intel/common/early_smbus.h: Add <device/pci_type.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68047 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/southbridge/intel/common/early_smbus.h 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h index d6a7cbb..0dc32c0 100644 --- a/src/southbridge/intel/common/early_smbus.h +++ b/src/southbridge/intel/common/early_smbus.h @@ -4,6 +4,7 @@ #define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H #include <device/pci_def.h> +#include <device/pci_type.h> #define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3) -- To view, visit https://review.coreboot.org/c/coreboot/+/68047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Gerrit-Change-Number: 68047 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: sb/intel/common/early_smbus.h: Add <device/pci_type.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68047 ) Change subject: sb/intel/common/early_smbus.h: Add <device/pci_type.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Gerrit-Change-Number: 68047 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 06 Oct 2022 17:02:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: security/memory/memory.h: Add <stdbool.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68046 ) Change subject: security/memory/memory.h: Add <stdbool.h> ...................................................................... security/memory/memory.h: Add <stdbool.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I908445b9f87b3db90527955116db22bbee674e1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68046 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/security/memory/memory.h 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/security/memory/memory.h b/src/security/memory/memory.h index c6ae4f8..90b4480 100644 --- a/src/security/memory/memory.h +++ b/src/security/memory/memory.h @@ -1,3 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stdbool.h> + bool security_clear_dram_request(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/68046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I908445b9f87b3db90527955116db22bbee674e1f Gerrit-Change-Number: 68046 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: security/memory/memory.h: Add <stdbool.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68046 ) Change subject: security/memory/memory.h: Add <stdbool.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I908445b9f87b3db90527955116db22bbee674e1f Gerrit-Change-Number: 68046 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 06 Oct 2022 17:01:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/rcven.c: Sort includes and add <types.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68045 ) Change subject: nb/intel/i945/rcven.c: Sort includes and add <types.h> ...................................................................... nb/intel/i945/rcven.c: Sort includes and add <types.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I360e4f8ed3b87225a09c7cbb761c570a579771cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68045 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/northbridge/intel/i945/rcven.c 1 file changed, 16 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index ca54bad..37b568a 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -2,8 +2,10 @@ #include <console/console.h> #include <device/mmio.h> -#include "raminit.h" +#include <types.h> + #include "i945.h" +#include "raminit.h" /** * sample the strobes signal -- To view, visit https://review.coreboot.org/c/coreboot/+/68045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I360e4f8ed3b87225a09c7cbb761c570a579771cf Gerrit-Change-Number: 68045 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i945/raminit.c: Clean up includes and add <types.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68044 ) Change subject: nb/intel/i945/raminit.c: Clean up includes and add <types.h> ...................................................................... nb/intel/i945/raminit.c: Clean up includes and add <types.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I94a81a30950cca6be5ba36a25f8bc6f87c2aad2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68044 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 22 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index ee5c541..0a4794a 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1,22 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cf9_reset.h> #include <console/console.h> #include <delay.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <device/smbus_host.h> -#include <cf9_reset.h> -#include <device/mmio.h> #include <device/device.h> +#include <device/dram/ddr2.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> +#include <device/smbus_host.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> +#include <timestamp.h> +#include <types.h> + #include "raminit.h" #include "i945.h" #include "chip.h" -#include <device/dram/ddr2.h> -#include <timestamp.h> /* Debugging macros. */ #if CONFIG(DEBUG_RAM_SETUP) -- To view, visit https://review.coreboot.org/c/coreboot/+/68044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94a81a30950cca6be5ba36a25f8bc6f87c2aad2f Gerrit-Change-Number: 68044 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: device/device_const.c: Clean up includes and add <types.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68043 ) Change subject: device/device_const.c: Clean up includes and add <types.h> ...................................................................... device/device_const.c: Clean up includes and add <types.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I7e84760566db5da7ff88dcbe9fb028ebcb390bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68043 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/device/device_const.c 1 file changed, 15 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/device/device_const.c b/src/device/device_const.c index c629f05..a40d0b0 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -4,10 +4,10 @@ #include <console/console.h> #include <device/device.h> #include <device/path.h> -#include <device/pci.h> #include <device/pci_def.h> -#include <device/resource.h> +#include <device/pci_type.h> #include <fw_config.h> +#include <types.h> /** Linked list of ALL devices */ DEVTREE_CONST struct device *DEVTREE_CONST all_devices = &dev_root; -- To view, visit https://review.coreboot.org/c/coreboot/+/68043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e84760566db5da7ff88dcbe9fb028ebcb390bdc Gerrit-Change-Number: 68043 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/x86/pae/pgtbl.c: Clean up includes and add <types.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68042 ) Change subject: cpu/x86/pae/pgtbl.c: Clean up includes and add <types.h> ...................................................................... cpu/x86/pae/pgtbl.c: Clean up includes and add <types.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I0ab39ff20b0fb59026063e064e20ce901c2985fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68042 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/cpu/x86/pae/pgtbl.c 1 file changed, 15 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index c8783d6..dceeb88 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cpu.h> #include <cbfs.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <arch/cpu.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <cpu/x86/pae.h> #include <string.h> #include <symbols.h> -#include <assert.h> +#include <types.h> #define PDPTE_PRES (1ULL << 0) #define PDPTE_ADDR_MASK (~((1ULL << 12) - 1)) -- To view, visit https://review.coreboot.org/c/coreboot/+/68042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab39ff20b0fb59026063e064e20ce901c2985fe Gerrit-Change-Number: 68042 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/intel/common/fsb.c: Sorte includes and add <stdint.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68041 ) Change subject: cpu/intel/common/fsb.c: Sorte includes and add <stdint.h> ...................................................................... cpu/intel/common/fsb.c: Sorte includes and add <stdint.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I9b85836ac21da5b885a97f05e3973fb23a052fd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68041 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/cpu/intel/common/fsb.c 1 file changed, 18 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 350e8c6..92f88cd 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <cpu/intel/fsb.h> +#include <cpu/intel/speedstep.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <cpu/intel/speedstep.h> -#include <cpu/intel/fsb.h> -#include <console/console.h> -#include <commonlib/helpers.h> #include <delay.h> +#include <stdint.h> static u32 timer_fsb; static u32 timer_tsc; -- To view, visit https://review.coreboot.org/c/coreboot/+/68041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85836ac21da5b885a97f05e3973fb23a052fd5 Gerrit-Change-Number: 68041 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2022