coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68031 ) Change subject: cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h> ...................................................................... cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h> Remove <stdint.h>, <stddef.h> and add <stdbool.h>. All of them are included through <types.h>. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: If5296988c68302896e3676d7b80d0f133d5d4264 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68031 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 24 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 41164bb..5f7535f 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -8,21 +8,21 @@ * Programming */ -#include <stddef.h> -#include <stdint.h> -#include <string.h> +#include <assert.h> #include <bootstate.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci_ids.h> +#include <cpu/amd/mtrr.h> #include <cpu/cpu.h> +#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> +#include <device/device.h> +#include <device/pci_ids.h> #include <memrange.h> -#include <cpu/amd/mtrr.h> -#include <assert.h> +#include <string.h> +#include <types.h> + #if CONFIG(X86_AMD_FIXED_MTRRS) #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) #else -- To view, visit https://review.coreboot.org/c/coreboot/+/68031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5296988c68302896e3676d7b80d0f133d5d4264 Gerrit-Change-Number: 68031 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: console/vsprintf.c: Add <stdarg.h>
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68038 ) Change subject: console/vsprintf.c: Add <stdarg.h> ...................................................................... console/vsprintf.c: Add <stdarg.h> Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I8c61f2a033f9630d3fa3eb5e364e6f38de5c7064 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68038 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/console/vsprintf.c 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 06b9e49..6892639 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/vtxprintf.h> +#include <stdarg.h> #include <string.h> struct vsnprintf_context { -- To view, visit https://review.coreboot.org/c/coreboot/+/68038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c61f2a033f9630d3fa3eb5e364e6f38de5c7064 Gerrit-Change-Number: 68038 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/qualcomm: Update the wait time for checking PCIe link up
by Shelley Chen (Code Review) 06 Oct '22

06 Oct '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67884 ) Change subject: soc/qualcomm: Update the wait time for checking PCIe link up ...................................................................... soc/qualcomm: Update the wait time for checking PCIe link up Currently, after the PCIe link is initialized, we wait 100ms every time the link is not up anymore. However, this causes significant delay. Assuming the first check is false, we'd like to increase the frequency of checks for the link to be up. Changing to check every 10ms instead. This seems to save about 90ms in the device configuration stage of bootup on herobrine. BUG=b:218406702 BRANCH=None TEST=reboot from AP console (on herobrine) prior to fix (from cbmem dump): 40:device configuration 919,391 (202,861) after fix (from cbmem dump): 40:device configuration 826,294 (112,729) Change-Id: Ic67e7207c1e9f589b34705dc24f5d1ea423e2d56 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67884 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: mturney mturney <quic_mturney(a)quicinc.com> Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- M src/soc/qualcomm/common/include/soc/pcie.h 1 file changed, 32 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Douglas Anderson: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve mturney mturney: Looks good to me, but someone else must approve diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h index 09ea671..5aa315c 100644 --- a/src/soc/qualcomm/common/include/soc/pcie.h +++ b/src/soc/qualcomm/common/include/soc/pcie.h @@ -48,8 +48,8 @@ #define LINK_SPEED_GEN_1 0x1 #define LINK_SPEED_GEN_2 0x2 #define LINK_SPEED_GEN_3 0x3 -#define PCIE_LINK_UP_MS 100 -#define LINK_WAIT_MAX_RETRIES 10 +#define PCIE_LINK_UP_MS 10 +#define LINK_WAIT_MAX_RETRIES 100 #define COMMAND_MASK 0xffff -- To view, visit https://review.coreboot.org/c/coreboot/+/67884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic67e7207c1e9f589b34705dc24f5d1ea423e2d56 Gerrit-Change-Number: 67884 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Veerabhadrarao Badiganti <vbadigan(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail
by build bot (Jenkins) (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Patrick Rudolph, Christian Walter. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66616 ) Change subject: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail ...................................................................... Patch Set 4: (7 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159867): https://review.coreboot.org/c/coreboot/+/66616/comment/39adbf00_070aa503 PS4, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159867): https://review.coreboot.org/c/coreboot/+/66616/comment/4c738d85_2da5b2ce PS4, Line 9: The PCH's SGPIO pads are connected to a buffer chip which is powered from Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159867): https://review.coreboot.org/c/coreboot/+/66616/comment/a3a8d734_3f36742d PS4, Line 10: the always-on +3V3_AUX rail. For some reason, if the SGPIO pads remain in Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159867): https://review.coreboot.org/c/coreboot/+/66616/comment/9f177cba_58deeb38 PS4, Line 11: their native function when a Poseidon system shuts down, a bit of voltage Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159867): https://review.coreboot.org/c/coreboot/+/66616/comment/6da7148b_aedbe6b4 PS4, Line 12: from the +3V3_AUX-powered buffer chip will leak into the +5V rail through Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159867): https://review.coreboot.org/c/coreboot/+/66616/comment/2f98d534_6b93ae1a PS4, Line 15: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159867): https://review.coreboot.org/c/coreboot/+/66616/comment/481bdc1d_1f84509e PS4, Line 16: This issue has only been observed in S5, but it is very likely other sleep Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/66616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Gerrit-Change-Number: 66616 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Thu, 06 Oct 2022 16:51:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm: Update the wait time for checking PCIe link up
by Douglas Anderson (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Shelley Chen, Tim Wawrzynczak, Julius Werner. Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67884 ) Change subject: soc/qualcomm: Update the wait time for checking PCIe link up ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic67e7207c1e9f589b34705dc24f5d1ea423e2d56 Gerrit-Change-Number: 67884 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Veerabhadrarao Badiganti <vbadigan(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 06 Oct 2022 16:51:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by build bot (Jenkins) (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... Patch Set 57: (47 comments) File payloads/cbui/NuklearUI/NuklearDatePicker.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/042cfb7e_efc1a42b PS57, Line 36: case 6: /* fallthrough */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/fcb1ef38_865eeb6b PS57, Line 37: case 9: /* fallthrough */ Prefer 'fallthrough;' over fallthrough comment File payloads/cbui/NuklearUI/NuklearRW.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/f0c03f7a_29e734bf PS57, Line 289: static const char *titles[] = { "Hex-View", "Header", "Index/Data" }; static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/1eea6090_98465f05 PS57, Line 323: static const char *entries[] = { "NVRAM" }; static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwAcpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/90008a5c_49bbabba PS57, Line 40: static const char *tools[] = { lang_translate(LANG_SAVE, 0), lang_translate( static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/3c906876_d763ca75 PS57, Line 43: static const char *tabs[] = { "RSDP", "XSDT", "RSDT", "FACP", "HPET", "APIC", "MCFG", static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/8cdeda6c_ec1c2139 PS57, Line 23: static const char *tools[] = { lang_translate(LANG_SAVE, 0), lang_translate( static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/431483cc_d8e8c753 PS57, Line 26: static const char *tabs[] = { "Hex-View", "Info", "Summary" }; static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwClock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/85d55301_6c6d09c2 PS57, Line 53: static const char *tools[] = { lang_translate(LANG_SAVE, 0), "Save bin", "Load", static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/ffc81afc_45739a7a PS57, Line 56: static const char *tabs[] = { "Hex-View", "Info", "Text" }; static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwCpuMsr.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/ed6f8fff_efa6e5c9 PS57, Line 20: static const char *tools[] = { lang_translate(LANG_SAVE, 0) }; static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/ad176587_cf70dcee PS57, Line 22: static const char *tabs[] = { "MTRR", "User", "Summary" }; static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwDimmSpd.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/e56856f6_11e0aad0 PS57, Line 61: static const char *tools[] = { lang_translate(LANG_SAVE, 0), "Save all", "Save bin", static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/d5458d76_8a6dd748 PS57, Line 65: static const char *tabs[] = { "Hex-View", "Info", "Text", "Summary" }; static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwE820.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/a75aee29_2f7d6711 PS57, Line 20: static const char *tools[] = { lang_translate(LANG_SAVE, 0) }; static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwEc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/4253c064_67fd4237 PS57, Line 49: static const char *tools[] = { lang_translate(LANG_SAVE, 0), "Save bin", "Load", static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/c64442cf_02041257 PS57, Line 52: static const char *tabs[] = { "Hex-View", "Info", "Text" }; static const char * array should probably be static const char * const File payloads/cbui/NuklearUI/NuklearRwIo.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/82d9646b_70bdc518 PS57, Line 49: static const char *tools[] = { lang_translate(LANG_SAVE, 0), "Save bin", "Load", static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/9d7036e3_d2ec0c40 PS57, Line 52: static const char *tabs[] = { "Hex-View", "Info", "Text" }; static const char * array should probably be static const char * const File payloads/cbui/arch/x86/int32.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/7741f837_ecf90b53 PS57, Line 20: typedef struct __attribute__ ((packed)) { Prefer __packed over __attribute__((packed)) File payloads/cbui/arch/x86/int32.nasm: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/738226e7_25c5767d PS57, Line 38: struc regs16_t 'struc' may be misspelled - perhaps 'struct'? File payloads/cbui/gfx/vbe.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/da6c11c8_35934dc6 PS57, Line 24: static u8 low_mem[0x1000] __attribute__ ((section(".lowmem"))); Prefer __section(".lowmem") over __attribute__((section(".lowmem"))) File payloads/cbui/lang/de.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/5b75d372_6206669d PS57, Line 39: "Kein Framebuffer gefunden. CBUI funktioniert nicht" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/8e858d90_11b5d7a3 PS57, Line 44: "Der coreboot framebuffer hat keine physikalische " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/8a73ed1f_5e0d8b11 PS57, Line 47: "Kein Platz auf dem Heap.\nBitte vergroBere den" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/ba40c8b3_a64dd650 PS57, Line 50: "Konnte die nuklear Bibliothek nicht intitialisieren.\nBitte" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/b0761acb_50344dd1 PS57, Line 52: "stelle sicher, das der Framebuffer entweder das RGBX8 oder " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/c01c38cc_02e9ecb2 PS57, Line 65: "Fehler: Keine CMOS Eintrage gefunden. Bitte schalte die " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/ef50f449_f985d157 PS57, Line 86: "Fehler: Keine Zeitstempel gefunden. Bitte schalte die " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/46ee8fc8_7dac58fd PS57, Line 89: "Fehler: Bootlog nicht gefunden. Bitte schalte die Kconfig " \ Avoid unnecessary line continuations File payloads/cbui/lang/en.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/5d3aa660_1fb7a63d PS57, Line 38: "No framebuffer found. CBUI doesn't work in text mode.\n" \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/d256f55e_828bb335 PS57, Line 46: "Failed to init nuklear library.\nMake sure you have enough " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/0e2b6263_269a4463 PS57, Line 60: "ERROR: No CMOS options found. Please make sure to enable " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/991e5b5a_50bc0bd3 PS57, Line 81: "ERROR: No timestamps found. Please make sure to enable " \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/f93fdca5_4d6ae20e PS57, Line 84: "ERROR: Bootlog not found. Please make sure to enable " \ Avoid unnecessary line continuations File payloads/cbui/modules/bootlog_module.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/d0118db3_2dad4746 PS57, Line 28: } __attribute__ ((__packed__)); Prefer __packed over __attribute__((__packed__)) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/f75905fe_04d37872 PS57, Line 82: } void function return statements are not generally useful File payloads/cbui/modules/cbfs_module.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/7207b647_106565e1 PS57, Line 50: } __attribute__ ((packed)); Prefer __packed over __attribute__((packed)) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/8c4b172e_fd28cabb PS57, Line 59: } __attribute__ ((packed)); Prefer __packed over __attribute__((packed)) File payloads/cbui/modules/cpuinfo_module.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/7c0843d8_3c25d146 PS57, Line 35: static const char *intel_cap_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/38700e78_ec1efa0c PS57, Line 43: static const char *amd_cap_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/8e140594_d464b7e5 PS57, Line 51: static const char *intel_cap_ecx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/965e4930_7ec66de2 PS57, Line 59: static const char *amd_cap_ecx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/a23646bc_da414b7d PS57, Line 67: static const char *intel_cap_extended_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/93b3bef6_9673edad PS57, Line 75: static const char *intel_cap_extended_ecx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/e04e6eea_4b24bbba PS57, Line 83: static const char *amd_cap_extended_edx_flags[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159866): https://review.coreboot.org/c/coreboot/+/23586/comment/02843871_83e5284f PS57, Line 92: static const char *amd_cap_extended_ecx_flags[] = { static const char * array should probably be static const char * const -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 57 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 06 Oct 2022 16:51:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#57) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearPciHeader.c A payloads/cbui/NuklearUI/NuklearPciHeader.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwClock.c A payloads/cbui/NuklearUI/NuklearRwClock.h A payloads/cbui/NuklearUI/NuklearRwCpuMsr.c A payloads/cbui/NuklearUI/NuklearRwCpuMsr.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwE820.c A payloads/cbui/NuklearUI/NuklearRwE820.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 104 files changed, 13,555 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/57 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 57 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI
by build bot (Jenkins) (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons, Lean Sheng Tan, David.Milosevic(a)9elements.com. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68137 ) Change subject: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI ...................................................................... Patch Set 6: (6 comments) File src/mainboard/prodrive/atlas/emi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159865): https://review.coreboot.org/c/coreboot/+/68137/comment/1f2d9ea0_7b767265 PS6, Line 51: switch (access) { switch and case should be at the same indent Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159865): https://review.coreboot.org/c/coreboot/+/68137/comment/5d93655a_06d00df9 PS6, Line 89: switch (access) { switch and case should be at the same indent File src/mainboard/prodrive/atlas/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159865): https://review.coreboot.org/c/coreboot/+/68137/comment/ac9d411b_9540d719 PS6, Line 14: static const char* get_smbios_part_number(void); "foo* bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159865): https://review.coreboot.org/c/coreboot/+/68137/comment/a0451ecc_9ed381b2 PS6, Line 41: static const char* get_smbios_part_number(void) "foo* bar" should be "foo *bar" File src/mainboard/prodrive/atlas/smbios.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159865): https://review.coreboot.org/c/coreboot/+/68137/comment/cf8805c4_14f05b4b PS6, Line 8: const char* smbios_mainboard_serial_number(void) "foo* bar" should be "foo *bar" File src/mainboard/prodrive/atlas/vpd.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159865): https://review.coreboot.org/c/coreboot/+/68137/comment/492a1b51_74ebc866 PS6, Line 34: switch (vpd) { switch and case should be at the same indent -- To view, visit https://review.coreboot.org/c/coreboot/+/68137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 Gerrit-Change-Number: 68137 Gerrit-PatchSet: 6 Gerrit-Owner: David.Milosevic(a)9elements.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David.Milosevic(a)9elements.com Gerrit-Comment-Date: Thu, 06 Oct 2022 16:49:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail
by Angel Pons (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Patrick Rudolph, Christian Walter. Hello build bot (Jenkins), Patrick Rudolph, Christian Walter, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66616 to look at the new patch set (#3). Change subject: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail ...................................................................... mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail The PCH's SGPIO pads are connected to a buffer chip which is powered from the always-on +3V3_AUX rail. For some reason, if the SGPIO pads remain in their native function when a Poseidon system shuts down, a bit of voltage from the +3V3_AUX-powered buffer chip will leak into the +5V rail through the SATA backplane. Simply pulling the SGPIO pads low before powering off the system stops the +5V rail from being cross-powered. This issue has only been observed in S5, but it is very likely other sleep states are affected as well. Thus, always pull the SGPIO pins low when the power supply will be switched off, i.e. ACPI S3 or deeper. TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered after going to S5. We measured 0.17V on our system, but voltages as high as 0.6V were measured on other systems. Verify that unplugging the SGPIO cable going to the SATA backplane results in the +5V rail voltage dropping to 0V, which indicates that the voltage leakage is exclusively coming from the SGPIO and SATA backplane. Finally, make sure that the +5V rail voltage drops to 0V after going into ACPI S5 with this patch applied and the SGPIO cable connected. Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/prodrive/hermes/smihandler.c 1 file changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/66616/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/66616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Gerrit-Change-Number: 66616 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI
by Name of user not set (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons, Lean Sheng Tan, David.Milosevic(a)9elements.com. Hello build bot (Jenkins), Christian Walter, Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68137 to look at the new patch set (#6). Change subject: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI ...................................................................... [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI The embedded controller stores serial-number and part-number within an EEPROM which is unreachable to the Host CPU. Therefore, on the EC side, we set up a shared memory region with the help of EMI and copy the VPDs to it. On the coreboot side, we can read those back and populate the SMBios table type 1 with the serial-number and type 11 with the part-number. emi.*: small interface to access the EMI regions vpd.*: uses the emi interface in order to read the VPDs smbios.c: populates smbios type 1 with the serial-number by using vpd.h mainboard.c: uses vpd.h to add a string to smbios type 11 ld_config.*: offers functionality to configure logical devices devicetree.cb: enables address range 0xc00-0xcff for the EMI runtime registers Makefile.inc: adds emi.c, vpd.c, smbios.c, ld_config.c to the ramstage compilation TODO: ld_config.* is redundant. We can replace this with pnp_device.h or pnp_ops.h Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 --- M src/mainboard/prodrive/atlas/Makefile.inc M src/mainboard/prodrive/atlas/devicetree.cb A src/mainboard/prodrive/atlas/emi.c A src/mainboard/prodrive/atlas/emi.h A src/mainboard/prodrive/atlas/ld_config.c A src/mainboard/prodrive/atlas/ld_config.h M src/mainboard/prodrive/atlas/mainboard.c A src/mainboard/prodrive/atlas/smbios.c A src/mainboard/prodrive/atlas/vpd.c A src/mainboard/prodrive/atlas/vpd.h 10 files changed, 528 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/68137/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 Gerrit-Change-Number: 68137 Gerrit-PatchSet: 6 Gerrit-Owner: David.Milosevic(a)9elements.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David.Milosevic(a)9elements.com Gerrit-MessageType: newpatchset

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