coreboot-gerrit October 2022

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[S] Change in coreboot[master]: treewide: use predicates to check for enabled pci devices
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68102 ) Change subject: treewide: use predicates to check for enabled pci devices ...................................................................... treewide: use predicates to check for enabled pci devices use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83(a)gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/mpspec.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 10 files changed, 29 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 2e65e25..739d185 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -575,7 +575,7 @@ for (dev = all_devices; dev; dev = dev->next) { - if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) + if (!is_enabled_pci(dev)) continue; have_fixed_entries = 0; diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 5c4103d..5a1623f 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -86,7 +86,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 99e3749..d499918 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -436,7 +436,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { uint8_t int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN); diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 1fc1ea3..5d1eda5 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -254,7 +254,7 @@ int8_t original_int_pin = 0, new_int_pin = 0, swiz_int_pin = 0; uint8_t int_line = 0xff; - if (irq_dev->path.type != DEVICE_PATH_PCI || !irq_dev->enabled) { + if (!is_enabled_pci(irq_dev)) { printk(BIOS_ERR, "%s for non pci device?\n", __func__); goto dnv_get_int_line_done; } @@ -380,7 +380,7 @@ int devfn = irq_dev->path.pci.devfn; u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b2e6344..4635189 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -104,7 +104,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a12e36b..4d82706 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -86,7 +86,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 9f70d1f..e39c95a 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -89,7 +89,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e3881ff..41bcccd 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -98,7 +98,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 1735020..d4e3098 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -96,7 +96,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7ae847b..20e40cb 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -120,7 +120,7 @@ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + if (!is_enabled_pci(irq_dev)) continue; int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); -- To view, visit https://review.coreboot.org/c/coreboot/+/68102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Gerrit-Change-Number: 68102 Gerrit-PatchSet: 4 Gerrit-Owner: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: include/device/device_util.c: add predicates for pci devices
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68101 ) Change subject: include/device/device_util.c: add predicates for pci devices ...................................................................... include/device/device_util.c: add predicates for pci devices add functions to check whether a device is enabled pci device or a pci device on a specific bus number. TEST: compile and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83(a)gmail.com> Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68101 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/device_util.c M src/include/device/device.h 2 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/device/device_util.c b/src/device/device_util.c index 0be6cfb..6919f4b 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -965,3 +965,18 @@ { return is_cpu(cpu) && cpu->enabled; } + +bool is_pci(const struct device *pci) +{ + return pci->path.type == DEVICE_PATH_PCI; +} + +bool is_enabled_pci(const struct device *pci) +{ + return is_pci(pci) && pci->enabled; +} + +bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus) +{ + return is_pci(pci) && pci->bus->secondary == bus; +} diff --git a/src/include/device/device.h b/src/include/device/device.h index a375639..0f9c39f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -209,6 +209,9 @@ bool is_devfn_enabled(unsigned int devfn); bool is_cpu(const struct device *cpu); bool is_enabled_cpu(const struct device *cpu); +bool is_pci(const struct device *pci); +bool is_enabled_pci(const struct device *pci); +bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus); /* Returns whether there is a hotplug port on the path to the given device. */ extern bool dev_path_hotplug(const struct device *); -- To view, visit https://review.coreboot.org/c/coreboot/+/68101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Gerrit-Change-Number: 68101 Gerrit-PatchSet: 3 Gerrit-Owner: Fabio Aiuto <fabioaiuto83(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/mithrax: adjust I2C5 times for TP
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67920 ) Change subject: mb/google/brya/var/mithrax: adjust I2C5 times for TP ...................................................................... mb/google/brya/var/mithrax: adjust I2C5 times for TP This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to follow I2C specification. I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us. I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us. BUG=b:249031186 BRANCH=brya TEST=EE check OK with test FW and TP function is normal. Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920 Reviewed-by: Ricky Chang <rickytlchang(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/mithrax/overridetree.cb 1 file changed, 31 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Ricky Chang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 5899535..2755c70 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -81,7 +81,12 @@ .speed = I2C_SPEED_FAST, .rise_time_ns = 550, .fall_time_ns = 400, - .data_hold_time_ns = 50, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 70, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/67920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940 Gerrit-Change-Number: 67920 Gerrit-PatchSet: 6 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization ...
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68095 ) Change subject: mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error ...................................................................... mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error Configure eMMC DLL tuning values for Pujjo board. BUG=b:241854926 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68095 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjo/overridetree.cb 1 file changed, 63 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 14164bc..a043b46 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -43,6 +43,51 @@ register "sagv" = "SaGv_Enabled" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10049" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. -- To view, visit https://review.coreboot.org/c/coreboot/+/68095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Gerrit-Change-Number: 68095 Gerrit-PatchSet: 5 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPU
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68099 ) Change subject: mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPU ...................................................................... mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPU An optional dGPU can be connected to the second PEG bridge: -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller +-01.0-[01]-- +-01.1-[02]----00.0 NVIDIA Corporation GK208M [GeForce GT 730M] It's possible that the 01.0 bridge is never populated, but we have to leave it on anyway so 01.1 can be enumerated. Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68099 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb 1 file changed, 24 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index b7588ea..c8772cc 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -23,8 +23,8 @@ subsystemid 0x17aa 0x220e inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 01.1 off end # Unused PCIe Bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics (optional) + device pci 01.1 on end # PCIe Bridge for discrete graphics (optional) device pci 02.0 on end # Internal graphics VGA controller device pci 03.0 on end # Mini-HD audio -- To view, visit https://review.coreboot.org/c/coreboot/+/68099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1 Gerrit-Change-Number: 68099 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/kontron/bsl6: Set board type to mobile for memory config
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67399 ) Change subject: mb/kontron/bsl6: Set board type to mobile for memory config ...................................................................... mb/kontron/bsl6: Set board type to mobile for memory config Given the embedded nature, the Halo SKU, SO-DIMMs and 1 DIMM per channel, `mobile` seems to come closest. Change-Id: Ia27f1e4dec0a0d06be3d8c08bfe82becd41a2149 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67399 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/kontron/bsl6/romstage.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index 3206f53..f0c1db0 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -39,5 +39,7 @@ memory_params->DqPinsInterleaved = true; memory_params->CaVrefConfig = 2; + memory_params->UserBd = BOARD_TYPE_MOBILE; + variant_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/67399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia27f1e4dec0a0d06be3d8c08bfe82becd41a2149 Gerrit-Change-Number: 67399 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_config
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68075 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_config ...................................................................... mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_config BUG=b:250470706 TEST=Boot to OS on pujjo and check that stylus GPIO are configured based on fw_config. Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: I4218748cb06426a918d89f688599c652062ac78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68075 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjo/fw_config.c 1 file changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjo/fw_config.c b/src/mainboard/google/brya/variants/pujjo/fw_config.c index ee86e74..dfc70c5 100644 --- a/src/mainboard/google/brya/variants/pujjo/fw_config.c +++ b/src/mainboard/google/brya/variants/pujjo/fw_config.c @@ -27,6 +27,13 @@ PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), }; +static const struct pad_config stylus_disable_pads[] = { + /* F13 : SOC_PEN_DETECT_R_ODL */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : SOC_PEN_DETECT_ODL */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (!fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT))) { @@ -41,4 +48,9 @@ ARRAY_SIZE(sd_disable_pads)); } + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { + printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); + gpio_padbased_override(padbased_table, stylus_disable_pads, + ARRAY_SIZE(stylus_disable_pads)); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4218748cb06426a918d89f688599c652062ac78c Gerrit-Change-Number: 68075 Gerrit-PatchSet: 3 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Fix unknown voltage in SMBIOS
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Zhixing Ma, Bora Guvendik, Tim Wawrzynczak, Nick Vaccaro. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68023 ) Change subject: soc/intel/alderlake: Fix unknown voltage in SMBIOS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68023/comment/1fa8e510_200736bd PS1, Line 13: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.… Please submit to archive.org and use the archive.org link here instead. That helps ensure that the link stays active even if dtmf.org decides to rearrange their site at some point in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/68023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86 Gerrit-Change-Number: 68023 Gerrit-PatchSet: 1 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 06 Oct 2022 18:24:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Fix unknown max speed in SMBIOS
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Zhixing Ma, Bora Guvendik, Selma Bensaid, Nick Vaccaro. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67913 ) Change subject: soc/intel/alderlake: Fix unknown max speed in SMBIOS ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67913/comment/fdd8c167_e815ba15 PS5, Line 13: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.… Please submit the link to archive.org and use the archive.org link instead -- To view, visit https://review.coreboot.org/c/coreboot/+/67913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09bcccc6f97238f7328224af8b852751114896fe Gerrit-Change-Number: 67913 Gerrit-PatchSet: 5 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 06 Oct 2022 18:22:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC
by Martin Roth (Code Review) 06 Oct '22

06 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66230 ) Change subject: soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC ...................................................................... soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/acpi/northbridge.asl 1 file changed, 23 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index f8023be..373d6b8 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -11,8 +11,12 @@ OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset(0x60), - MCNF, 32, /* PCI MMCONF base */ + Offset (0x60), /* PCIEXBAR (0:0:0:60) + PXEN, 1, /* Enable */ + PXSZ, 2, /* PCI Express Size */ + , 25, + PXBR, 11, /* PCI Express Base Address */ + Offset (0xA8), TUUD, 64, /* Top of Upper Used Memory */ Offset(0xB4), -- To view, visit https://review.coreboot.org/c/coreboot/+/66230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Gerrit-Change-Number: 66230 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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