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[L] Change in coreboot[master]: ec/starlabs/merlin: Add EC related files for Alder Lake boards
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67398 ) Change subject: ec/starlabs/merlin: Add EC related files for Alder Lake boards ...................................................................... ec/starlabs/merlin: Add EC related files for Alder Lake boards Add EC memory layout and Q events for Intel Alder Lake based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8cea386ba91d076084002738fe7041834deea311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/ec/starlabs/merlin/variants/adl/ecdefs.h A src/ec/starlabs/merlin/variants/adl/emem.asl A src/ec/starlabs/merlin/variants/adl/events.asl 3 files changed, 476 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/variants/adl/ecdefs.h b/src/ec/starlabs/merlin/variants/adl/ecdefs.h new file mode 100644 index 0000000..28f7e4b --- /dev/null +++ b/src/ec/starlabs/merlin/variants/adl/ecdefs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <stdint.h> + +/* + * EC communication interface for ITE Embedded Controller + */ + +#ifndef _EC_STARLABS_ADL_EC_DEFS_H +#define _EC_STARLABS_ADL_EC_DEFS_H + +/* IT5570 chip ID byte values */ +#define ITE_CHIPID_VAL 0x5570 + +/* EC RAM offsets */ +#define ECRAM_KBL_BRIGHTNESS 0x09 +#define ECRAM_KBL_TIMEOUT 0x10 +#define ECRAM_KBL_STATE 0x0a +#define ECRAM_TRACKPAD_STATE 0x0c +#define ECRAM_FN_LOCK_STATE 0x0f +#define ECRAM_FN_CTRL_REVERSE 0x17 +#define ECRAM_MAX_CHARGE 0x1a +#define ECRAM_FAN_MODE 0x1b +#define ECRAM_FAST_CHARGE dead_code_t(uint8_t) + +#endif diff --git a/src/ec/starlabs/merlin/variants/adl/emem.asl b/src/ec/starlabs/merlin/variants/adl/emem.asl new file mode 100644 index 0000000..7c9c0ed --- /dev/null +++ b/src/ec/starlabs/merlin/variants/adl/emem.asl @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + OSFG, 8, // OS Flag + FRMF, 8, // Force Mirror Flag + + Offset(0x07), + SKUI, 8, // SKU ID + CSFG, 8, // Modern Standby Flag + KLBE, 8, // Keyboard Backlight Brightness + KLSE, 8, // Keyboard Backlight State + BDID, 8, // Board ID + TPLE, 8, // Trackpad State + KBCD, 8, // Rotate Flag + WIFI, 8, // WiFi Enable + FLKE, 8, // Function Lock State + KLTE, 8, // Keyboard Backlight Timeout + + Offset(0x13), + AUDI, 8, // Control Audio + + Offset(0x15), + SURF, 8, // Chassis Surface Temperature + CHAR, 8, // Charger Temperature + FCLA, 8, // Fn Ctrl Reverse + + Offset(0x1a), + BFCP, 8, // Battery Full Charge Percentage + FANM, 8, // Fan Mode + + Offset(0x1d), + BSRC, 8, // BIOS Recover + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + ECT4, 8, // EC Build Time 4 + ECT5, 8, // EC Build Time 5 + ECT6, 8, // EC Build Time 6 + ECT7, 8, // EC Build Time 7 + ECT8, 8, // EC Build Time 8 + ECT9, 8, // EC Build Time 9 + + Offset(0x4B), + ECD0, 8, // EC Build Date 0 + ECD1, 8, // EC Build Date 1 + ECD2, 8, // EC Build Date 2 + ECD3, 8, // EC Build Date 3 + ECD4, 8, // EC Build Date 4 + ECD5, 8, // EC Build Date 5 + ECD6, 8, // EC Build Date 6 + ECD7, 8, // EC Build Date 7 + ECD8, 8, // EC Build Date 8 + ECD9, 8, // EC Build Date 9 + + Offset(0x62), + TSE2, 8, // Sensor 2 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x68), + BATT, 16, // Battery Temperature + BATC, 8, // Battery Temperature Ces + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + TSE1, 8, // Sensor 1 Temperature + TSE3, 8, // Sensor 3 Temperature + + Offset(0x7f), + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + + Offset(0xb0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xc0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xd0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xe6), + ECWD, 16, // EC Wakeup Delay + ECWE, 8, // EC Wakeup Enable + + Offset(0xf7), + TBTC, 8, // Thunderbolt Command + TBTP, 8, // Thunderbolt Data Port + TBTD, 8, // Thunderbolt Data + TBTA, 8, // Thunderbolt Acknowledge + TBTG, 16, // Thunderbolt DBG Data +} diff --git a/src/ec/starlabs/merlin/variants/adl/events.asl b/src/ec/starlabs/merlin/variants/adl/events.asl new file mode 100644 index 0000000..03de4d9 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/adl/events.asl @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q01, 0, NotSerialized) // Event: F1 Hot Key +{ + Printf ("EC: F1") +} + +Method (_Q02, 0, NotSerialized) // Event: F2 Hot Key +{ + Printf ("EC: F2") +} + +Method (_Q03, 0, NotSerialized) // Event: F3 Hot Key +{ + Printf ("EC: F3") +} + +Method (_Q04, 0, NotSerialized) // Event: F4 Hot Key +{ + Printf ("EC: F4") +} + +Method (_Q08, 0, NotSerialized) // Event: F5 Hot Key +{ + Printf ("EC: F5") +} + +Method (_Q09, 0, NotSerialized) // Event: F6 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q07, 0, NotSerialized) // Event: F7 Hot Key +{ + Printf ("EC: F7") +} + +Method (_Q05, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q10, 0, NotSerialized) // Event: F10 Hot Key +{ + Printf ("EC: F10") +} + +Method (_Q11, 0, NotSerialized) // Event: F11 Hot Key +{ + Printf ("EC: F11") +} + +Method (_Q12, 0, NotSerialized) // Event: F12 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0E, 0, NotSerialized) // Event: SLEEP +{ + Printf ("EC: SLEEP") +} + +Method (_Q13, 0, NotSerialized) // Event: BRIGHTNESS +{ + Printf ("EC: BRIGHTNESS") +} + +Method (_Q20, 0, NotSerialized) // Event: CPU_T +{ + Printf ("EC: CPU_T") +} + +Method (_Q21, 0, NotSerialized) // Event: SKIN_T +{ + Printf ("EC: SKIN_T") +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q30, 0, NotSerialized) // Event: THROT_OFF +{ + Printf ("EC: THROT_OFF") +} + +Method (_Q31, 0, NotSerialized) // Event: THROT_LV1 +{ + Printf ("EC: THROT_LV1") +} + +Method (_Q32, 0, NotSerialized) // Event: THROT_LV2 +{ + Printf ("EC: THROT_LV2") +} + +Method (_Q33, 0, NotSerialized) // Event: THROT_LV3 +{ + Printf ("EC: THROT_LV3") +} + +Method (_Q34, 0, NotSerialized) // Event: THROT_LV4 +{ + Printf ("EC: THROT_LV4") +} + +Method (_Q35, 0, NotSerialized) // Event: THROT_LV5 +{ + Printf ("EC: THROT_LV5") +} + +Method (_Q36, 0, NotSerialized) // Event: THROT_LV6 +{ + Printf ("EC: THROT_LV6") +} + +Method (_Q37, 0, NotSerialized) // Event: THROT_LV7 +{ + Printf ("EC: THROT_LV7") +} + +Method (_Q3B, 0, NotSerialized) // Event: CPU_DN_SPEED +{ + Printf ("EC: CPU_DN_SPEED") +} + +Method (_Q3C, 0, NotSerialized) // Event: CPU_UP_SPEED +{ + Printf ("EC: CPU_UP_SPEED") +} + +Method (_Q3D, 0, NotSerialized) // Event: CPU_TURBO_OFF +{ + Printf ("EC: CPU_TURBO_OFF") +} + +Method (_Q3E, 0, NotSerialized) // Event: CPU_TURBO_ON +{ + Printf ("EC: CPU_TURBO_ON") +} + +Method (_Q3F, 0, NotSerialized) // Event: SHUTDOWN +{ + Printf ("EC: SHUTDOWN") +} + +Method (_Q40, 0, NotSerialized) // Event: AC and DC Power +{ + SMB2 = 0xC6 +} + +Method (_Q41, 0, NotSerialized) // Event: Battery Charge between 0% and 20% +{ + SMB2 = 0xC7 +} + +Method (_Q42, 0, NotSerialized) // Event: Battery Charge between 20% and 60% +{ + SMB2 = 0xC8 +} + +Method (_Q43, 0, NotSerialized) // Event: Battery Charge between 60% and 100% +{ + SMB2 = 0xC9 +} + +Method (_Q44, 0, NotSerialized) // Event: AC Power Only +{ + SMB2 = 0xCA +} + +Method (_Q45, 0, NotSerialized) // Event: SENSOR_T76 +{ + SMB2 = 0xCB +} + +Method (_Q48, 0, NotSerialized) // Event: Fan Turbo On +{ + Printf ("EC: Fan Turbo On") +} + +Method (_Q49, 0, NotSerialized) // Event: Fan Turbo Off +{ + Printf ("EC: Fan Turbo Off") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +} + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC: VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q85, 0, NotSerialized) // Event: HOME +{ + Printf ("EC: HOME") +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +Method (_QF0, 0, NotSerialized) // Event: Temperature Report +{ + Printf ("EC: Temperature Report") +} + +Method (_QF1, 0, NotSerialized) // Event: Temperature Trigger +{ + Printf ("EC: Temperature Trigger") +} + +Method (_Q99, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/67398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cea386ba91d076084002738fe7041834deea311 Gerrit-Change-Number: 67398 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/prodrive/hermes: Factor out serial reading logic
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67275 ) Change subject: mb/prodrive/hermes: Factor out serial reading logic ...................................................................... mb/prodrive/hermes: Factor out serial reading logic Add the `eeprom_read_serial()` function to read serials from the EEPROM. Note that there's only one buffer now: this means only one serial can be accessed at the same time, and the buffer needs to be cleared so that it does not contain old data from other serials. Given that the serials are copied one at a time into SMBIOS tables, having one shared buffer is not a problem. Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67275 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/eeprom.h M src/mainboard/prodrive/hermes/smbios.c 3 files changed, 35 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index 7a92fe3..54e0e11 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -7,6 +7,7 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <soc/intel/common/block/smbus/smbuslib.h> +#include <string.h> #include <types.h> #include "eeprom.h" @@ -88,6 +89,17 @@ return &bmc_cfg; } +const char *eeprom_read_serial(const size_t offset, const char *const fallback) +{ + static char serial_no[HERMES_SERIAL_NUMBER_LENGTH] = { 0 }; + memset(serial_no, 0, sizeof(serial_no)); + + if (eeprom_read_buffer(serial_no, offset, sizeof(serial_no)) == 0) + return serial_no; + else + return fallback; +} + uint8_t get_bmc_hsi(void) { uint8_t hsi = 0; diff --git a/src/mainboard/prodrive/hermes/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h index 2f7eac7..63e84af 100644 --- a/src/mainboard/prodrive/hermes/eeprom.h +++ b/src/mainboard/prodrive/hermes/eeprom.h @@ -105,6 +105,7 @@ int check_signature(const size_t offset, const uint64_t signature); struct eeprom_board_settings *get_board_settings(void); struct eeprom_bmc_settings *get_bmc_settings(void); +const char *eeprom_read_serial(size_t offset, const char *fallback); uint8_t get_bmc_hsi(void); void report_eeprom_error(const size_t off); bool write_board_settings(const struct eeprom_board_layout *new_layout); diff --git a/src/mainboard/prodrive/hermes/smbios.c b/src/mainboard/prodrive/hermes/smbios.c index c1325d4..923ce81 100644 --- a/src/mainboard/prodrive/hermes/smbios.c +++ b/src/mainboard/prodrive/hermes/smbios.c @@ -9,23 +9,13 @@ const char *smbios_system_serial_number(void) { const size_t offset = offsetof(struct eeprom_layout, system_serial_number); - static char serial_no[HERMES_SERIAL_NUMBER_LENGTH] = { 0 }; - - if (eeprom_read_buffer(serial_no, offset, sizeof(serial_no)) == 0) - return serial_no; - else - return CONFIG_MAINBOARD_SERIAL_NUMBER; + return eeprom_read_serial(offset, CONFIG_MAINBOARD_SERIAL_NUMBER); } const char *smbios_mainboard_serial_number(void) { const size_t offset = offsetof(struct eeprom_layout, board_serial_number); - static char serial_no[HERMES_SERIAL_NUMBER_LENGTH] = { 0 }; - - if (eeprom_read_buffer(serial_no, offset, sizeof(serial_no)) == 0) - return serial_no; - else - return CONFIG_MAINBOARD_SERIAL_NUMBER; + return eeprom_read_serial(offset, CONFIG_MAINBOARD_SERIAL_NUMBER); } const char *smbios_mainboard_version(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/67275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c Gerrit-Change-Number: 67275 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66616 ) Change subject: mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail ...................................................................... mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail The PCH's SGPIO pads are connected to a buffer chip that is powered from the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads stay configured as SGPIO when a Poseidon system shuts down, voltage from the +3V3_AUX-powered buffer chip will leak into the +5V rail through the SATA backplane. Just pulling the SGPIO pads low before the system powers off stops the +5V rail from being cross-powered. This issue has only been observed in S5, but it's very likely other sleep states are affected as well. Thus, always pull the SGPIO pins low before entering ACPI S3 or deeper because the power supply will turn off in these states as well. TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered after going to S5. We measured 0.17V on our system, but voltages as high as 0.6V were measured on other systems. Verify that unplugging the SGPIO cable going to the SATA backplane results in the +5V rail voltage dropping to 0V, which indicates that the voltage leakage is exclusively coming from the SGPIO and SATA backplane. Finally, make sure that the +5V rail voltage drops to 0V after going into ACPI S5 with this patch applied and the SGPIO cable connected. Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- A src/mainboard/prodrive/hermes/smihandler.c 1 file changed, 58 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/smihandler.c b/src/mainboard/prodrive/hermes/smihandler.c new file mode 100644 index 0000000..50b8e8b --- /dev/null +++ b/src/mainboard/prodrive/hermes/smihandler.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <cpu/x86/smm.h> +#include <intelblocks/gpio.h> +#include <intelblocks/smihandler.h> +#include <soc/gpio.h> + +static const struct pad_config sgpio_table[] = { + PAD_CFG_GPO(GPP_F10, 0, DEEP), + PAD_CFG_GPO(GPP_F11, 0, DEEP), + PAD_CFG_GPO(GPP_F12, 0, DEEP), + PAD_CFG_GPO(GPP_F13, 0, DEEP), +}; + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* + * Pull SGPIO pins low to prevent cross-powering the +5V rail + * through the SATA backplane when the power supply is off. + */ + if (slp_typ >= ACPI_S3) + gpio_configure_pads(sgpio_table, ARRAY_SIZE(sgpio_table)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/66616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Gerrit-Change-Number: 66616 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: payloads/edk2: Guard the build target
by Sean Rhodes (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Martin L Roth, Stefan Reinauer, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68182 ) Change subject: payloads/edk2: Guard the build target ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68182/comment/92fca1af_605f9b9c PS2, Line 9: against > a tiny fix needed Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4597b5ed76616e39cec45f8a69be9f1ccd72d4c Gerrit-Change-Number: 68182 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 22:06:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/coreboot-configurator: Update the README
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65350 ) Change subject: util/coreboot-configurator: Update the README ...................................................................... util/coreboot-configurator: Update the README Update the README with new instructions for Debian 11 and MX Linux. Also add the build dependencies. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/coreboot-configurator/README.md 1 file changed, 23 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/util/coreboot-configurator/README.md b/util/coreboot-configurator/README.md index baf0490..cbfe8b7 100644 --- a/util/coreboot-configurator/README.md +++ b/util/coreboot-configurator/README.md @@ -16,13 +16,14 @@ sudo apt purge coreboot-configurator ``` -## Debian 11 +## Debian 11 / MX Linux 19 ##### Install ``` -echo "deb http://ppa.launchpad.net/starlabs/ppa/ubuntu focal main" | sudo tee -a /etc/apt/sources.list.d/starlabs-ubuntu-ppa-focal.list -sudo apt-key adv --keyserver keyserver.ubuntu.com --recv-keys 17A20BAF70BEC3904545ACFF8F21C26C794386E3 -sudo apt update -sudo apt install coreboot-configurator +cd /tmp +wget https://github.com/StarLabsLtd/packages/raw/main/Debian/11/coreboot-configu… \ + https://github.com/StarLabsLtd/packages/raw/main/Debian/11/nvramtool_1_all.… +sudo dpkg -i *.deb +sudo apt -f install ``` ##### Uninstall -- To view, visit https://review.coreboot.org/c/coreboot/+/65350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e Gerrit-Change-Number: 65350 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/apollolake: Add UFS Interrupt
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67680 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Add UFS Interrupt ...................................................................... soc/intel/apollolake: Add UFS Interrupt According to Intel document number 336561, GLK has UFS (0x1d), so add the PCI interrupt. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/acpi/pci_irqs.asl 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index 585d9db..b47ac24 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -54,6 +54,9 @@ Package(){0x001BFFFF, 0, 0, SDCARD_INT}, #endif Package(){0x001CFFFF, 0, 0, EMMC_INT}, +#if CONFIG(SOC_INTEL_GEMINILAKE) + Package(){0x001DFFFF, 0, 0, UFS_INT}, +#endif Package(){0x001EFFFF, 0, 0, SDIO_INT}, Package(){0x001FFFFF, 0, 0, SMBUS_INT}, }) -- To view, visit https://review.coreboot.org/c/coreboot/+/67680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Gerrit-Change-Number: 67680 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/apollolake: Remove SD Card interrupt for GLK
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67679 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Remove SD Card interrupt for GLK ...................................................................... soc/intel/apollolake: Remove SD Card interrupt for GLK According to Intel document number 336561, G, SD Card (0x1b) does not exist on GLK, so remove it. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/acpi/pci_irqs.asl 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index 7a963ff..585d9db 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -50,7 +50,9 @@ Package(){0x0019FFFF, 0, 0, SPI0_INT}, Package(){0x0019FFFF, 1, 0, SPI1_INT}, Package(){0x0019FFFF, 2, 0, SPI2_INT}, +#if !CONFIG(SOC_INTEL_GEMINILAKE) Package(){0x001BFFFF, 0, 0, SDCARD_INT}, +#endif Package(){0x001CFFFF, 0, 0, EMMC_INT}, Package(){0x001EFFFF, 0, 0, SDIO_INT}, Package(){0x001FFFFF, 0, 0, SMBUS_INT}, -- To view, visit https://review.coreboot.org/c/coreboot/+/67679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Gerrit-Change-Number: 67679 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Use preset driver strength for SD-Card
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68166 ) Change subject: mb/siemens/mc_ehl2: Use preset driver strength for SD-Card ...................................................................... mb/siemens/mc_ehl2: Use preset driver strength for SD-Card The intention of predefining driver strength is to avoid that the OS SD-Card driver changes this setting. Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index a798398..3395160 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -9,6 +9,8 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> +#define HOSTCTRL2 0x3E +#define HOSTCTRL2_PRESET (1 << 15) #define SD_CAP_BYP 0x810 #define SD_CAP_BYP_EN 0x5A #define SD_CAP_BYP_REG1 0x814 @@ -34,6 +36,7 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { uint32_t reg; + uint16_t reg16; struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -43,6 +46,11 @@ reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50); reg |= SD_CAP_BYP_DDR50; write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + + /* Use preset driver strength from preset value registers. */ + reg16 = read16(res2mmio(res, HOSTCTRL2, 0)); + reg16 |= HOSTCTRL2_PRESET; + write16(res2mmio(res, HOSTCTRL2, 0), reg16); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946 Gerrit-Change-Number: 68166 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/ehl: Set Ethernet controller to D0 power state
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67976 ) Change subject: soc/intel/ehl: Set Ethernet controller to D0 power state ...................................................................... soc/intel/ehl: Set Ethernet controller to D0 power state To be able to change the MAC addresses, it is necessary that the controllers are in D0 power state. As of FSP MR3, Intel has set the controllers to D3 power state at the end of FSP-S TSN GbE initialization. This patch sets the state back to D0 before the programming of the MAC addresses. Test: - Build coreboot with FSP MR4 for mc_ehl2 mainboard - Boot into Linux and check MAC addr via 'ip a' Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/elkhartlake/tsn_gbe.c 1 file changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index ea2ef0e..49ce4da 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/lpss.h> #include <soc/soc_chip.h> #include <soc/tsn_gbe.h> #include <timer.h> @@ -99,6 +100,13 @@ } } +static void gbe_tsn_enable(struct device *dev) +{ + /* Ensure controller is in D0 state. */ + lpss_set_power_state(PCI_DEV(0, PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)), STATE_D0); +} + static void gbe_tsn_init(struct device *dev) { /* Get the base address of the I/O registers in memory space */ @@ -127,6 +135,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .enable = gbe_tsn_enable, .init = gbe_tsn_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/67976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21 Gerrit-Change-Number: 67976 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/amdfwtool: Add preliminary code for morgana & glinda SOCs
by Marshall Dawson (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Martin L Roth, Martin Roth, Fred Reitberger. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68193 ) Change subject: util/amdfwtool: Add preliminary code for morgana & glinda SOCs ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/68193/comment/840fb5bf_cbc9df26 PS2, Line 1940: return PLATFORM_GLENDA; > Done I'll likely make the same error many times. -- To view, visit https://review.coreboot.org/c/coreboot/+/68193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f Gerrit-Change-Number: 68193 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 21:49:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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