coreboot-gerrit October 2022

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[S] Change in coreboot[master]: util/lint: Fix typo in lint-stable-003-whitespace
by Martin L Roth (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Martin Roth. Hello Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68243 to review the following change. Change subject: util/lint: Fix typo in lint-stable-003-whitespace ...................................................................... util/lint: Fix typo in lint-stable-003-whitespace Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: I0101da5943a35e688d50ec5750e96e48956aa820 --- M util/lint/lint-stable-003-whitespace 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/68243/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index e46d93e..0611f25 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -4,7 +4,7 @@ # DESCR: Check for superfluous whitespace in the tree -INTDIR="$( +LINTDIR="$( cd -- "$(dirname "$0")" > /dev/null 2>&1 || return pwd -P )" -- To view, visit https://review.coreboot.org/c/coreboot/+/68243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0101da5943a35e688d50ec5750e96e48956aa820 Gerrit-Change-Number: 68243 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: Documentation/security: Update list of boards supporting vboot
by Martin L Roth (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Martin Roth. Hello Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68242 to review the following change. Change subject: Documentation/security: Update list of boards supporting vboot ...................................................................... Documentation/security: Update list of boards supporting vboot Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: Ie6ecb3ed97ed0581300411962c3b1bba416e0224 --- M Documentation/security/vboot/list_vboot.md 1 file changed, 77 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/68242/1 diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 8908c6a..24149c0 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -35,7 +35,6 @@ - Anahera4ES - Brask - Brya 0 -- Brya4ES - Felwinter - Gimble - Gimble4ES @@ -46,6 +45,8 @@ - Primus4ES - Redrix - Redrix4ES +- Skolas +- Skolas4ES - Taeko - Taeko4ES - Taniks @@ -55,12 +56,24 @@ - Crota - Moli - Kinox +- Craask +- Osiris +- Mithrax +- Kuldax +- Joxer +- Pujjo +- Xivu +- Gaelin4ADL +- Yaviks - Butterfly (HP Pavilion Chromebook 14) - Cherry - Dojo - Tomato - Kingler +- Steelix - Krabby +- Tentacruel +- Magikarp - Banon (Acer Chromebook 15 (CB3-532)) - Celes (Samsung Chromebook 3) - Cyan (Acer Chromebook R11 (C738T)) @@ -72,7 +85,6 @@ - Terra (ASUS Chromebook C202SA/C300SA/C301SA) - Ultima (Lenovo Yoga 11e G3) - Wizpig -- Daisy (Samsung Chromebook (2012)) - Drallion - Eve (Google Pixelbook) - Fizz @@ -80,6 +92,7 @@ - Endeavour - Foster - Gale (Google WiFi) +- Geralt - Asuka (Dell Chromebook 13 3380) - Caroline (Samsung Chromebook Pro) - Cave (Asus Chromebook Flip C302SA) @@ -97,34 +110,24 @@ - Nipperkin - Dewatt - Akemi (IdeaPad Flex 5/5i Chromebook) -- Ambassador -- Dooly - Dratini (HP Pro c640 Chromebook) -- Duffy Legacy (32MB) -- Duffy (ASUS Chromebox 4) -- Faffy (ASUS Fanless Chromebox) -- Genesis - Hatch - Helios (ASUS Chromebook Flip C436FA) - Helios_Diskswap - Jinlon (HP Elite c1030 Chromebook) -- Kaisa Legacy (32MB) -- Kaisa (Acer Chromebox CXI4) - Kindred (Acer Chromebook 712) - Kohaku (Samsung Galaxy Chromebook) -- Moonbuggy - Mushu - Nightfury (Samsung Galaxy Chromebook 2) -- Noibat (HP Chromebox G3) - Palkia -- Puff -- Scout -- Wyvern (CTL Chromebox CBx2) - Herobrine - Herobrine_Rev0 - Senor - Piglin - Hoglin +- Villager +- Evoker +- Zoglin - Guado (ASUS Chromebox CN62) - Jecht - Rikku (Acer Chromebox CXI2) @@ -164,14 +167,26 @@ - Elm (Acer Chromebook R13) - Hana (Lenovo N23 Yoga Chromebook) - Parrot (Acer C7/C710 Chromebook) -- Peach Pit (Samsung Chromebook 2 11\") - Atlas (Google Pixelbook Go) - Poppy - Nami - Nautilus (Samsung Chromebook Plus V2, V2 LTE) - Nocturne (Google Pixel Slate) -- Rammus (Asus Chromebook C425, Flip C433, Flip C434) +- Rammus - Soraka (HP Chromebook x2) +- Ambassador +- Dooly +- Duffy Legacy (32MB) +- Duffy (ASUS Chromebox 4) +- Faffy (ASUS Fanless Chromebox) +- Genesis +- Kaisa Legacy (32MB) +- Kaisa (Acer Chromebox CXI4) +- Moonbuggy +- Noibat (HP Chromebox G3) +- Puff +- Scout +- Wyvern (CTL Chromebox CBx2) - Banjo (Acer Chromebook 15 (CB3-531)) - Candy (Dell Chromebook 11 3120) - Clapper (Lenovo N20 Chromebook) @@ -193,8 +208,12 @@ - Sand (Acer Chromebook 15 CB515-1HT/1H) - Snappy (HP Chromebook x360 11 G1 EE) - Coral +- Rex 0 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise) - Sarien (Dell Latitude 5400 Chromebook Enterprise) +- Skyrim +- Winterhold +- Morthal - Falco (HP Chromebook 14) - Leon (Toshiba Chromebook) - Peppy (Acer C720/C720P Chromebook) @@ -222,6 +241,25 @@ - Veyron_Speedy (ASUS C201 Chromebook) - Veyron_Mickey (Asus Chromebit CS10) - Veyron_Rialto +- Delbin (ASUS Chromebook Flip CX5) +- Eldrid +- Halvor +- Lindar +- Malefor +- Terrador +- Todor +- Trondo +- Volteer +- Volteer2 +- Volteer2_Ti50 +- Voxel (Acer Chromebook Spin 713 (CP713-3W)) +- Elemi (HP Pro c640 G2 Chromebook) +- Voema +- Drobit (ASUS Chromebook CX9400) +- Copano (ASUS Chromebook Flip CX5400) +- Collis +- Volet +- Chronicler - Dalboz - Vilboz (Lenovo 100e/300e Gen3 AMD) - Ezkinil (Acer Chromebook Spin 514) @@ -234,6 +272,7 @@ - Gumboz (HP Chromebook x360 14a) ## HP +- Z220 CMT Workstation - Z220 SFF Workstation ## Intel @@ -244,6 +283,7 @@ - Alderlake-M RVP with Chrome EC - Alderlake-N RVP - Alderlake-N RVP with Chrome EC +- Raptorlake silicon with Alderlake-P RVP and Chrome EC - Basking Ridge CRB - Coffeelake U SO-DIMM DDR4 RVP - Coffeelake H SO-DIMM DDR4 RVP11 @@ -270,6 +310,8 @@ - Whitetip Mountain 2 CRB ## Lenovo +- ThinkPad T440p +- ThinkPad W541 - ThinkPad T400 - ThinkPad T500 - ThinkPad R400 @@ -281,7 +323,6 @@ - ThinkPad T430 - ThinkPad T430s - ThinkPad T431s -- ThinkPad T440p - ThinkPad T520 - ThinkPad W520 - ThinkPad T530 @@ -299,6 +340,9 @@ - ThinkPad X230s - ThinkPad X60 / X60s / X60t +## MSI +- PRO Z690-A WIFI DDR4 + ## OpenCellular - Elgon (GBCv2) @@ -313,6 +357,11 @@ - MC APL4 - MC APL5 - MC APL6 +- MC APL7 + +## Star Labs +- Star Labs Lite Mk III (N5000) +- Star Labs Lite Mk IV (N5030) ## Supermicro - X11SSH-TF -- To view, visit https://review.coreboot.org/c/coreboot/+/68242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6ecb3ed97ed0581300411962c3b1bba416e0224 Gerrit-Change-Number: 68242 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs
by Angel Pons (Code Review) 08 Oct '22

08 Oct '22

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68187 ) Change subject: sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs ...................................................................... Patch Set 1: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/68187/comment/e440ba7a_ec738c57 PS1, Line 2840: #define PCI_DID_INTEL_LPT_H97 0x8cc6 Might need to add them to report_platform somewhere. -- To view, visit https://review.coreboot.org/c/coreboot/+/68187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235 Gerrit-Change-Number: 68187 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 08 Oct 2022 19:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/common/mcu.c: Use 'enum cb_err' instead of 'int'
by Elyes Haouas (Code Review) 08 Oct '22

08 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68241 ) Change subject: soc/mediatek/common/mcu.c: Use 'enum cb_err' instead of 'int' ...................................................................... soc/mediatek/common/mcu.c: Use 'enum cb_err' instead of 'int' Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I562bfbdc5c917a17ce1aa656046b69eb56dce48c --- M src/soc/mediatek/common/include/soc/mcu_common.h M src/soc/mediatek/common/mcu.c 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68241/1 diff --git a/src/soc/mediatek/common/include/soc/mcu_common.h b/src/soc/mediatek/common/include/soc/mcu_common.h index 974da52..7689c1b 100644 --- a/src/soc/mediatek/common/include/soc/mcu_common.h +++ b/src/soc/mediatek/common/include/soc/mcu_common.h @@ -13,6 +13,6 @@ void (*reset)(struct mtk_mcu *mcu); /* The reset callback */ }; -int mtk_init_mcu(struct mtk_mcu *mcu); +enum cb_err mtk_init_mcu(struct mtk_mcu *mcu); #endif /* SOC_MEDIATEK_MTLIB_COMMON_H */ diff --git a/src/soc/mediatek/common/mcu.c b/src/soc/mediatek/common/mcu.c index 42b3124..ca2bdbb 100644 --- a/src/soc/mediatek/common/mcu.c +++ b/src/soc/mediatek/common/mcu.c @@ -7,7 +7,7 @@ #include <soc/symbols.h> #include <timer.h> -int mtk_init_mcu(struct mtk_mcu *mcu) +enum cb_err mtk_init_mcu(struct mtk_mcu *mcu) { struct stopwatch sw; -- To view, visit https://review.coreboot.org/c/coreboot/+/68241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I562bfbdc5c917a17ce1aa656046b69eb56dce48c Gerrit-Change-Number: 68241 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: device/dram/ddr2: Use 'enum cb_err' instead of 'int'
by Elyes Haouas (Code Review) 08 Oct '22

08 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68240 ) Change subject: device/dram/ddr2: Use 'enum cb_err' instead of 'int' ...................................................................... device/dram/ddr2: Use 'enum cb_err' instead of 'int' Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I8ea6e773d858b30d75ff93d4fe07301f3825c1cb --- M src/device/dram/ddr2.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/68240/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 2cacc85..ce7a3bf 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -122,7 +122,7 @@ * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th ns. */ -static int spd_decode_tck_time(u32 *tck, u8 c) +static enum cb_err spd_decode_tck_time(u32 *tck, u8 c) { u8 high, low; @@ -159,7 +159,7 @@ * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th ns. */ -static int spd_decode_bcd_time(u32 *bcd, u8 c) +static enum cb_err spd_decode_bcd_time(u32 *bcd, u8 c) { u8 high, low; @@ -194,7 +194,7 @@ * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th us. */ -static int spd_decode_tRR_time(u32 *tRR, u8 c) +static enum cb_err spd_decode_tRR_time(u32 *tRR, u8 c) { switch (c & ~0x80) { default: -- To view, visit https://review.coreboot.org/c/coreboot/+/68240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ea6e773d858b30d75ff93d4fe07301f3825c1cb Gerrit-Change-Number: 68240 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/lint/lint-stable-003-whitespace: Fix shell variable name
by Elyes Haouas (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Martin L Roth, Fred Reitberger. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68225 ) Change subject: util/lint/lint-stable-003-whitespace: Fix shell variable name ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3 Gerrit-Change-Number: 68225 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Sat, 08 Oct 2022 13:32:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#82) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearPciHeader.c A payloads/cbui/NuklearUI/NuklearPciHeader.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwClock.c A payloads/cbui/NuklearUI/NuklearRwClock.h A payloads/cbui/NuklearUI/NuklearRwCpuMsr.c A payloads/cbui/NuklearUI/NuklearRwCpuMsr.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwE820.c A payloads/cbui/NuklearUI/NuklearRwE820.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.c A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.h A payloads/cbui/NuklearUI/NuklearRwSmbios.c A payloads/cbui/NuklearUI/NuklearRwSmbios.h A payloads/cbui/NuklearUI/NuklearRwSmbus.c A payloads/cbui/NuklearUI/NuklearRwSmbus.h A payloads/cbui/NuklearUI/NuklearRwSmram.c A payloads/cbui/NuklearUI/NuklearRwSmram.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearRwUsb.c A payloads/cbui/NuklearUI/NuklearRwUsb.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 128 files changed, 15,443 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/82 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 82 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/picasso: Clean up includes
by Elyes Haouas (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68237 ) Change subject: soc/amd/picasso: Clean up includes ...................................................................... soc/amd/picasso: Clean up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I4ed869627af11b607f910644b6f21898f7c7bba5 --- M src/soc/amd/picasso/bootblock.c M src/soc/amd/picasso/graphics.c M src/soc/amd/picasso/pcie_gpp.c M src/soc/amd/picasso/smu.c 4 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/68237/1 diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c index dd4ef3c..9e88cea 100644 --- a/src/soc/amd/picasso/bootblock.c +++ b/src/soc/amd/picasso/bootblock.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/cpu.h> #include <bootblock_common.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/tsc.h> #include <soc/psp_transfer.h> #include <soc/southbridge.h> -#include <amdblocks/amd_pci_mmconf.h> +#include <stdint.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/amd/picasso/graphics.c b/src/soc/amd/picasso/graphics.c index 047559c..298e177 100644 --- a/src/soc/amd/picasso/graphics.c +++ b/src/soc/amd/picasso/graphics.c @@ -4,6 +4,7 @@ #include <device/pci_rom.h> #include <soc/cpu.h> #include <soc/soc_util.h> +#include <stdint.h> void map_oprom_vendev_rev(u32 *vendev, u8 *rev) { diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index c46135f..aab37f4 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <amdblocks/amd_pci_util.h> +#include <commonlib/bsd/helpers.h> #include <soc/pci_devs.h> +#include <stddef.h> /* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ const struct pci_routing_info pci_routing_table[] = { diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/picasso/smu.c index 1496957..076baaa 100644 --- a/src/soc/amd/picasso/smu.c +++ b/src/soc/amd/picasso/smu.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <amdblocks/smu.h> +#include <console/console.h> #include <soc/smu.h> /* -- To view, visit https://review.coreboot.org/c/coreboot/+/68237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ed869627af11b607f910644b6f21898f7c7bba5 Gerrit-Change-Number: 68237 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/amd/common: Clean up inludes
by Elyes Haouas (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68236 ) Change subject: soc/amd/common: Clean up inludes ...................................................................... soc/amd/common: Clean up inludes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I7e11c14ba2653f2a2e6472ed58cb4923b0e1840d --- M src/soc/amd/common/block/acp/acp_gen1.c M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/acpi/elog.c M src/soc/amd/common/block/acpimmio/print_reset_status.c M src/soc/amd/common/block/aoac/aoac.c M src/soc/amd/common/block/cpu/smm/smi_handler.c M src/soc/amd/common/block/cpu/tsc/monotonic_timer.c M src/soc/amd/common/block/cpu/tsc/tsc_freq.c M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/pci/amd_pci_util.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smm_gen2.c M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/common/block/spi/fch_spi_util.c M src/soc/amd/common/block/uart/uart_acpi.c M src/soc/amd/common/block/uart/uart_console.c M src/soc/amd/common/fsp/dmi.c 19 files changed, 63 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/68236/1 diff --git a/src/soc/amd/common/block/acp/acp_gen1.c b/src/soc/amd/common/block/acp/acp_gen1.c index 0fe37f3..192f7cb 100644 --- a/src/soc/amd/common/block/acp/acp_gen1.c +++ b/src/soc/amd/common/block/acp/acp_gen1.c @@ -2,10 +2,10 @@ #include <amdblocks/acp.h> #include <amdblocks/chip.h> +#include <console/console.h> #include <device/device.h> #include <device/mmio.h> -#include <console/console.h> -#include "acp_def.h" +#include <stdint.h> /* ACP registers and associated fields */ #define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 75d4adf..2aafabf 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -2,8 +2,8 @@ #include <acpi/acpi.h> #include <acpi/acpi_pm.h> -#include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> +#include <amdblocks/acpimmio.h> #include <bootmode.h> #include <console/console.h> #include <halt.h> diff --git a/src/soc/amd/common/block/acpi/elog.c b/src/soc/amd/common/block/acpi/elog.c index b9268aa..fd0337a 100644 --- a/src/soc/amd/common/block/acpi/elog.c +++ b/src/soc/amd/common/block/acpi/elog.c @@ -3,6 +3,7 @@ #include <amdblocks/acpi.h> #include <elog.h> #include <soc/southbridge.h> +#include <stdint.h> static void elog_pm1_status(const struct acpi_pm_gpe_state *state) { diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c index 5ff0412..0c5cbd6 100644 --- a/src/soc/amd/common/block/acpimmio/print_reset_status.c +++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <amdblocks/acpimmio.h> +#include <commonlib/bsd/helpers.h> +#include <console/console.h> +#include <stdint.h> static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) diff --git a/src/soc/amd/common/block/aoac/aoac.c b/src/soc/amd/common/block/aoac/aoac.c index 0afd2a1..4beb9ed 100644 --- a/src/soc/amd/common/block/aoac/aoac.c +++ b/src/soc/amd/common/block/aoac/aoac.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <amdblocks/acpimmio.h> #include <amdblocks/aoac.h> +#include <types.h> /* This initiates the power on sequence, but doesn't wait for the device to be powered on. */ void power_on_aoac_device(unsigned int dev) diff --git a/src/soc/amd/common/block/cpu/smm/smi_handler.c b/src/soc/amd/common/block/cpu/smm/smi_handler.c index ee8423a..2b41368 100644 --- a/src/soc/amd/common/block/cpu/smm/smi_handler.c +++ b/src/soc/amd/common/block/cpu/smm/smi_handler.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <amdblocks/acpimmio.h> -#include <console/console.h> #include <amdblocks/smi.h> #include <amdblocks/smm.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/smi.h> +#include <stdint.h> __weak void mainboard_handle_smi(int event) { diff --git a/src/soc/amd/common/block/cpu/tsc/monotonic_timer.c b/src/soc/amd/common/block/cpu/tsc/monotonic_timer.c index 4cedc3d..a26dfe0 100644 --- a/src/soc/amd/common/block/cpu/tsc/monotonic_timer.c +++ b/src/soc/amd/common/block/cpu/tsc/monotonic_timer.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <cpu/x86/tsc.h> +#include <stdint.h> #include <timer.h> #include <timestamp.h> diff --git a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c index 55c8665..d4e2c2a 100644 --- a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c +++ b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/tsc.h> #include <console/console.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <stdint.h> static unsigned long mhz; diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 4f20dd4..ca9d5cc 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c index d665a81..2d73029 100644 --- a/src/soc/amd/common/block/pci/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <device/pci.h> -#include <arch/io.h> -#include <device/pci_ops.h> #include <amdblocks/amd_pci_util.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> #include <pc80/i8259.h> #include <soc/amd_pci_int_defs.h> +#include <types.h> const struct pirq_struct *pirq_data_ptr; u32 pirq_data_size; diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 65043e5..74e5d01 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/psp.h> +#include <amdblocks/smn.h> #include <bootstate.h> #include <console/console.h> #include <timer.h> -#include <amdblocks/psp.h> -#include <amdblocks/smn.h> +#include <types.h> + #include "psp_def.h" #define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ diff --git a/src/soc/amd/common/block/psp/psp_smm_gen2.c b/src/soc/amd/common/block/psp/psp_smm_gen2.c index f02723a..e23324f 100644 --- a/src/soc/amd/common/block/psp/psp_smm_gen2.c +++ b/src/soc/amd/common/block/psp/psp_smm_gen2.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/smi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/psp.h> #include <amdblocks/smi.h> +#include <soc/smi.h> +#include <stdint.h> void soc_fill_smm_trig_info(struct smm_trigger_info *trig) { diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 801a154..285d4e2 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/smbus.h> #include <device/smbus_host.h> +#include <stdint.h> static u32 get_sm_mmio(struct device *dev) { diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index ac2f4b4..36eb8b8 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -2,12 +2,13 @@ /* SMI utilities used in both SMM and normal mode */ -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/southbridge.h> -#include <soc/smi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/smi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/smi.h> +#include <soc/southbridge.h> +#include <types.h> void configure_smi(uint8_t smi_num, uint8_t mode) { diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index b3d7c69..ed160e5 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <spi_flash.h> -#include <soc/pci_devs.h> #include <amdblocks/lpc.h> #include <amdblocks/spi.h> +#include <commonlib/bsd/helpers.h> +#include <console/console.h> #include <device/pci_ops.h> #include <lib.h> +#include <soc/pci_devs.h> +#include <spi_flash.h> #include <timer.h> #include <types.h> diff --git a/src/soc/amd/common/block/spi/fch_spi_util.c b/src/soc/amd/common/block/spi/fch_spi_util.c index c5d7123..84e7ca6 100644 --- a/src/soc/amd/common/block/spi/fch_spi_util.c +++ b/src/soc/amd/common/block/spi/fch_spi_util.c @@ -2,9 +2,10 @@ #include <amdblocks/lpc.h> #include <amdblocks/spi.h> -#include <device/mmio.h> #include <assert.h> +#include <device/mmio.h> #include <stdint.h> +#include <thread.h> /* Global SPI controller mutex */ struct thread_mutex spi_hw_mutex; diff --git a/src/soc/amd/common/block/uart/uart_acpi.c b/src/soc/amd/common/block/uart/uart_acpi.c index eb17322..17c36d7 100644 --- a/src/soc/amd/common/block/uart/uart_acpi.c +++ b/src/soc/amd/common/block/uart/uart_acpi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> #include <acpi/acpigen.h> #include <amdblocks/uart.h> #include <device/device.h> diff --git a/src/soc/amd/common/block/uart/uart_console.c b/src/soc/amd/common/block/uart/uart_console.c index 9f37190..99f80ba 100644 --- a/src/soc/amd/common/block/uart/uart_console.c +++ b/src/soc/amd/common/block/uart/uart_console.c @@ -2,6 +2,7 @@ #include <amdblocks/uart.h> #include <console/uart.h> +#include <stdint.h> /* * uart_platform_base and uart_platform_refclk are used by the console UART driver and need to diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index b443fe2..9018dda 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -4,19 +4,20 @@ * This code was adapted from src/soc/amd/common/block/pi/amd_late_init.c */ -#include <fsp/util.h> -#include <memory_info.h> -#include <console/console.h> -#include <cbmem.h> -#include <string.h> -#include <ec/google/chromeec/ec.h> #include <bootstate.h> -#include <lib.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/dram/ddr4.h> +#include <device/dram/ddr5.h> +#include <device/dram/lpddr4.h> #include <dimm_info_util.h> #include <dmi_info.h> -#include <device/dram/ddr4.h> -#include <device/dram/lpddr4.h> -#include <device/dram/ddr5.h> +#include <ec/google/chromeec/ec.h> +#include <fsp/util.h> +#include <lib.h> +#include <memory_info.h> +#include <string.h> +#include <types.h> /** * Convert DDR clock speed (based on memory type) in MHz to the standard reported speed in MT/s -- To view, visit https://review.coreboot.org/c/coreboot/+/68236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e11c14ba2653f2a2e6472ed58cb4923b0e1840d Gerrit-Change-Number: 68236 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/amd/bilby: Clean up includes
by Elyes Haouas (Code Review) 08 Oct '22

08 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68235 ) Change subject: mb/amd/bilby: Clean up includes ...................................................................... mb/amd/bilby: Clean up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ieb4bf3e759605de92a9bcedbd595a9ce3f5fb17e --- M src/mainboard/amd/bilby/bootblock.c M src/mainboard/amd/bilby/early_gpio.c M src/mainboard/amd/bilby/emmc_gpio.c M src/mainboard/amd/bilby/gpio.c M src/mainboard/amd/bilby/hda_verb.c M src/mainboard/amd/bilby/mainboard.h 6 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/68235/1 diff --git a/src/mainboard/amd/bilby/bootblock.c b/src/mainboard/amd/bilby/bootblock.c index 94a1329..1847d86 100644 --- a/src/mainboard/amd/bilby/bootblock.c +++ b/src/mainboard/amd/bilby/bootblock.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootblock_common.h> #include <amdblocks/lpc.h> +#include <bootblock_common.h> +#include <device/pnp_type.h> #include <superio/smsc/sio1036/sio1036.h> + #include "gpio.h" #define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_ADDR_BASE, SIO1036_SP1) diff --git a/src/mainboard/amd/bilby/early_gpio.c b/src/mainboard/amd/bilby/early_gpio.c index 466b4fc..746b5c4 100644 --- a/src/mainboard/amd/bilby/early_gpio.c +++ b/src/mainboard/amd/bilby/early_gpio.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/bsd/helpers.h> #include <soc/gpio.h> + #include "gpio.h" /* GPIO pins used by coreboot should be initialized in bootblock */ diff --git a/src/mainboard/amd/bilby/emmc_gpio.c b/src/mainboard/amd/bilby/emmc_gpio.c index f72437b..a92b98d 100644 --- a/src/mainboard/amd/bilby/emmc_gpio.c +++ b/src/mainboard/amd/bilby/emmc_gpio.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <soc/gpio.h> + #include "gpio.h" /* eMMC controller driving either an SD card or eMMC device. */ diff --git a/src/mainboard/amd/bilby/gpio.c b/src/mainboard/amd/bilby/gpio.c index 18ee482..481a387 100644 --- a/src/mainboard/amd/bilby/gpio.c +++ b/src/mainboard/amd/bilby/gpio.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <soc/gpio.h> + #include "gpio.h" /* diff --git a/src/mainboard/amd/bilby/hda_verb.c b/src/mainboard/amd/bilby/hda_verb.c index 0f61f31..60d75fd 100644 --- a/src/mainboard/amd/bilby/hda_verb.c +++ b/src/mainboard/amd/bilby/hda_verb.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/azalia_device.h> +#include <stdint.h> const u32 cim_verb_data[] = { /* Realtek ALC701 on mainboard */ diff --git a/src/mainboard/amd/bilby/mainboard.h b/src/mainboard/amd/bilby/mainboard.h index b58c350..d4f25c1 100644 --- a/src/mainboard/amd/bilby/mainboard.h +++ b/src/mainboard/amd/bilby/mainboard.h @@ -1,3 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stdint.h> + int get_ddi_port_conn_type(uint8_t port_num); -- To view, visit https://review.coreboot.org/c/coreboot/+/68235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb4bf3e759605de92a9bcedbd595a9ce3f5fb17e Gerrit-Change-Number: 68235 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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