coreboot-gerrit October 2022

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#84) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearPciHeader.c A payloads/cbui/NuklearUI/NuklearPciHeader.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwClock.c A payloads/cbui/NuklearUI/NuklearRwClock.h A payloads/cbui/NuklearUI/NuklearRwCpuMsr.c A payloads/cbui/NuklearUI/NuklearRwCpuMsr.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwE820.c A payloads/cbui/NuklearUI/NuklearRwE820.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.c A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.h A payloads/cbui/NuklearUI/NuklearRwSmbios.c A payloads/cbui/NuklearUI/NuklearRwSmbios.h A payloads/cbui/NuklearUI/NuklearRwSmbus.c A payloads/cbui/NuklearUI/NuklearRwSmbus.h A payloads/cbui/NuklearUI/NuklearRwSmram.c A payloads/cbui/NuklearUI/NuklearRwSmram.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearRwUsb.c A payloads/cbui/NuklearUI/NuklearRwUsb.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 128 files changed, 15,309 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/84 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 84 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: payloads/edk2: Guard the build target
by Lean Sheng Tan (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Sean Rhodes, Martin L Roth, Stefan Reinauer. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68182 ) Change subject: payloads/edk2: Guard the build target ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4597b5ed76616e39cec45f8a69be9f1ccd72d4c Gerrit-Change-Number: 68182 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 08 Oct 2022 21:20:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Guard the silent switch
by Lean Sheng Tan (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Sean Rhodes, Martin L Roth, Matt DeVillier, Stefan Reinauer. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68181 ) Change subject: payloads/edk2: Guard the silent switch ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5df636e6484a435c849c6d19c7cb61e8e62ee6 Gerrit-Change-Number: 68181 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 08 Oct 2022 21:19:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/64bit: Fix building with -jx
by Arthur Heymans (Code Review) 08 Oct '22

08 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68244 ) Change subject: cpu/x86/64bit: Fix building with -jx ...................................................................... cpu/x86/64bit: Fix building with -jx config.h is a dependency so add it. Change-Id: Iac87039dd43aa75d49766b9a239fbd841ca6850c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/64bit/Makefile.inc 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/68244/1 diff --git a/src/cpu/x86/64bit/Makefile.inc b/src/cpu/x86/64bit/Makefile.inc index 1895498..48f56fc 100644 --- a/src/cpu/x86/64bit/Makefile.inc +++ b/src/cpu/x86/64bit/Makefile.inc @@ -7,7 +7,7 @@ ramstage-y += mode_switch.S # Add --defsym=_start=0 to suppress a linker warning. -$(objcbfs)/pt: $(dir)/pt.S +$(objcbfs)/pt: $(dir)/pt.S $(obj)/config.h $(CC_bootblock) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -o $@.tmp $< -Wl,--section-start=.rodata=$(CONFIG_ARCH_X86_64_PGTBL_LOC),--defsym=_start=0 $(OBJCOPY_ramstage) -Obinary -j .rodata $@.tmp $@ rm $@.tmp -- To view, visit https://review.coreboot.org/c/coreboot/+/68244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac87039dd43aa75d49766b9a239fbd841ca6850c Gerrit-Change-Number: 68244 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino/psp_verstage: Remove TODO comment
by Martin Roth (Code Review) 08 Oct '22

08 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68227 ) Change subject: soc/amd/mendocino/psp_verstage: Remove TODO comment ...................................................................... soc/amd/mendocino/psp_verstage: Remove TODO comment PSP verstage has been successfully enabled and this makefile looks good. Hence removing a TODO comment. BUG=b:239090306 TEST=Build Skyrim BIOS image. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ic3cd55171fd1e4d74fac72f0b0b92dc80e533b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68227 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/mendocino/psp_verstage/Makefile.inc 1 file changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/mendocino/psp_verstage/Makefile.inc b/src/soc/amd/mendocino/psp_verstage/Makefile.inc index b6819a1..b185ffd 100644 --- a/src/soc/amd/mendocino/psp_verstage/Makefile.inc +++ b/src/soc/amd/mendocino/psp_verstage/Makefile.inc @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -# TODO(b/239090306): Check if this is still correct - verstage-generic-ccopts += -I$(src)/soc/amd/mendocino/psp_verstage/include verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/mendocino/include -- To view, visit https://review.coreboot.org/c/coreboot/+/68227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3cd55171fd1e4d74fac72f0b0b92dc80e533b5c Gerrit-Change-Number: 68227 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Create frostflow variant
by Martin Roth (Code Review) 08 Oct '22

08 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68189 ) Change subject: mb/google/skyrim: Create frostflow variant ...................................................................... mb/google/skyrim: Create frostflow variant Create the frostflow variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_FROSTFLOW Signed-off-by: Chao Gui <chaogui(a)google.com> Change-Id: I937e6562094968824e73bfa20390b3ec8b24dfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68189 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/Kconfig.name A src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h A src/mainboard/google/skyrim/variants/frostflow/overridetree.cb 4 files changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 0bc9ea9..cb1932f 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -78,6 +78,7 @@ default "Skyrim" if BOARD_GOOGLE_SKYRIM default "Winterhold" if BOARD_GOOGLE_WINTERHOLD default "Morthal" if BOARD_GOOGLE_MORTHAL + default "Frostflow" if BOARD_GOOGLE_FROSTFLOW config OVERRIDE_DEVICETREE string @@ -88,6 +89,7 @@ default "skyrim" if BOARD_GOOGLE_SKYRIM default "winterhold" if BOARD_GOOGLE_WINTERHOLD default "morthal" if BOARD_GOOGLE_MORTHAL + default "frostflow" if BOARD_GOOGLE_FROSTFLOW config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name index 2091776..498f09b 100644 --- a/src/mainboard/google/skyrim/Kconfig.name +++ b/src/mainboard/google/skyrim/Kconfig.name @@ -11,3 +11,7 @@ config BOARD_GOOGLE_MORTHAL bool "-> Morthal" select BOARD_GOOGLE_BASEBOARD_SKYRIM + +config BOARD_GOOGLE_FROSTFLOW + bool "-> Frostflow" + select BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h b/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/frostflow/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb new file mode 100644 index 0000000..7a56f93 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/mendocino + device domain 0 on end +end # chip soc/amd/mendocino -- To view, visit https://review.coreboot.org/c/coreboot/+/68189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I937e6562094968824e73bfa20390b3ec8b24dfa0 Gerrit-Change-Number: 68189 Gerrit-PatchSet: 2 Gerrit-Owner: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/prodrive/hermes: Write reset cause regs to EEPROM
by Martin Roth (Code Review) 08 Oct '22

08 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67483 ) Change subject: mb/prodrive/hermes: Write reset cause regs to EEPROM ...................................................................... mb/prodrive/hermes: Write reset cause regs to EEPROM Write the value for reset cause registers to the EEPROM for debugging. Change-Id: I827f38731fd868aac72103957e01aac8263f1cd3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67483 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/eeprom.h M src/mainboard/prodrive/hermes/mainboard.c 3 files changed, 56 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index 4d67133..5defff6 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -153,7 +153,7 @@ * Write a single byte into the EEPROM at specified offset. * Returns true on error, false on success. */ -static bool eeprom_write_byte(const uint8_t data, const uint16_t write_offset) +bool eeprom_write_byte(const uint8_t data, const uint16_t write_offset) { int ret = 0; diff --git a/src/mainboard/prodrive/hermes/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h index 97a1f48..6befd8e 100644 --- a/src/mainboard/prodrive/hermes/eeprom.h +++ b/src/mainboard/prodrive/hermes/eeprom.h @@ -38,6 +38,12 @@ _Static_assert(sizeof(struct eeprom_board_layout) == (617 + sizeof(uint32_t)), "struct eeprom_board_layout has invalid size!"); +struct __packed eeprom_reset_cause_regs { + uint32_t gblrst_cause0; + uint32_t gblrst_cause1; + uint32_t hpr_cause0; +}; + struct __packed eeprom_board_settings { uint32_t signature; union { @@ -89,7 +95,11 @@ uint8_t boot_order[0x200]; char board_part_number[HERMES_SN_PN_LENGTH]; char product_part_number[HERMES_SN_PN_LENGTH]; - uint8_t unused[0x680]; + union { + struct eeprom_reset_cause_regs reset_cause_regs; + uint8_t raw_reset_cause_registers[0x80]; + }; + uint8_t unused[0x600]; union { uint8_t raw_board_settings[0xf8]; struct eeprom_board_settings board_settings; @@ -111,6 +121,7 @@ const char *eeprom_read_serial(size_t offset, const char *fallback); uint8_t get_bmc_hsi(void); void report_eeprom_error(const size_t off); +bool eeprom_write_byte(const uint8_t data, const uint16_t write_offset); bool write_board_settings(const struct eeprom_board_layout *new_layout); #define READ_EEPROM(section_type, section_name, dest, opt_name) \ diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index c2f8b63..e94a8bc 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -14,6 +14,7 @@ #include <intelblocks/pmclib.h> #include <smbios.h> #include <soc/gpio.h> +#include <soc/pm.h> #include <string.h> #include <types.h> @@ -249,6 +250,31 @@ .enable_dev = mainboard_enable, }; +static void log_reset_causes(void) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + union { + struct eeprom_reset_cause_regs regs; + uint8_t raw[sizeof(struct eeprom_reset_cause_regs)]; + } reset_cause = { + .regs = { + .gblrst_cause0 = ps->gblrst_cause[0], + .gblrst_cause1 = ps->gblrst_cause[1], + .hpr_cause0 = ps->hpr_cause0, + }, + }; + + const size_t base = offsetof(struct eeprom_layout, reset_cause_regs); + for (size_t i = 0; i < ARRAY_SIZE(reset_cause.raw); i++) + eeprom_write_byte(reset_cause.raw[i], base + i); +} + /* Must happen before MPinit */ static void mainboard_early(void *unused) { @@ -273,6 +299,8 @@ READ_EEPROM_FSP_S((&supd), FspsConfig.TurboMode); config->cpu_turbo_disable = !supd.FspsConfig.TurboMode; } + + log_reset_causes(); } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/67483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827f38731fd868aac72103957e01aac8263f1cd3 Gerrit-Change-Number: 67483 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: payloads/edk2: Guard the silent switch
by Sean Rhodes (Code Review) 08 Oct '22

08 Oct '22

Attention is currently required from: Martin L Roth, Stefan Reinauer. Hello build bot (Jenkins), Martin L Roth, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68181 to look at the new patch set (#4). Change subject: payloads/edk2: Guard the silent switch ...................................................................... payloads/edk2: Guard the silent switch The silent switch, `-s`, only works for building UefiPayloadPkg. Guard it against the relevant Kconfig option so that it doesn't cause problems with other targets. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I5a5df636e6484a435c849c6d19c7cb61e8e62ee6 --- M payloads/external/edk2/Makefile 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/68181/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5df636e6484a435c849c6d19c7cb61e8e62ee6 Gerrit-Change-Number: 68181 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/prodrive/hermes: Add part numbers to SMBIOS
by Martin Roth (Code Review) 08 Oct '22

08 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67759 ) Change subject: mb/prodrive/hermes: Add part numbers to SMBIOS ...................................................................... mb/prodrive/hermes: Add part numbers to SMBIOS Adjust the EEPROM layout to account for two new fields: board part number and product part number. In addition, put them in a Type 11 SMBIOS table (OEM Strings). Also, rename a macro to better reflect its purpose. Change-Id: I26c17ab37859c3306fe72c3f0cdc1d3787b48157 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67759 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/eeprom.h M src/mainboard/prodrive/hermes/mainboard.c 3 files changed, 49 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index 54e0e11..4d67133 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -91,7 +91,7 @@ const char *eeprom_read_serial(const size_t offset, const char *const fallback) { - static char serial_no[HERMES_SERIAL_NUMBER_LENGTH] = { 0 }; + static char serial_no[HERMES_SN_PN_LENGTH] = { 0 }; memset(serial_no, 0, sizeof(serial_no)); if (eeprom_read_buffer(serial_no, offset, sizeof(serial_no)) == 0) diff --git a/src/mainboard/prodrive/hermes/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h index 63e84af..97a1f48 100644 --- a/src/mainboard/prodrive/hermes/eeprom.h +++ b/src/mainboard/prodrive/hermes/eeprom.h @@ -68,7 +68,7 @@ uint8_t efp3_displayport; }; -#define HERMES_SERIAL_NUMBER_LENGTH 32 +#define HERMES_SN_PN_LENGTH 32 /* The EEPROM on address 0x57 has the following vendor defined layout: */ struct __packed eeprom_layout { @@ -84,9 +84,12 @@ uint8_t raw_board_layout[0x400]; struct eeprom_board_layout board_layout; }; - char system_serial_number[HERMES_SERIAL_NUMBER_LENGTH]; - char board_serial_number[HERMES_SERIAL_NUMBER_LENGTH]; - uint8_t boot_order[0x8c0]; + char system_serial_number[HERMES_SN_PN_LENGTH]; + char board_serial_number[HERMES_SN_PN_LENGTH]; + uint8_t boot_order[0x200]; + char board_part_number[HERMES_SN_PN_LENGTH]; + char product_part_number[HERMES_SN_PN_LENGTH]; + uint8_t unused[0x680]; union { uint8_t raw_board_settings[0xf8]; struct eeprom_board_settings board_settings; diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index a713342..c2f8b63 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -14,6 +14,7 @@ #include <intelblocks/pmclib.h> #include <smbios.h> #include <soc/gpio.h> +#include <string.h> #include <types.h> #include "eeprom.h" @@ -170,6 +171,27 @@ pmc_soc_set_afterg3_en(on); } +static const char *format_pn(const char *prefix, size_t offset) +{ + static char buffer[32 + HERMES_SN_PN_LENGTH] = { 0 }; + + const char *part_num = eeprom_read_serial(offset, "N/A"); + + memset(buffer, 0, sizeof(buffer)); + strcpy(buffer, prefix); + strcpy(buffer + strlen(prefix), part_num); + + return buffer; +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + const size_t board_offset = offsetof(struct eeprom_layout, board_part_number); + const size_t product_offset = offsetof(struct eeprom_layout, product_part_number); + t->count = smbios_add_string(t->eos, format_pn("Board P/N: ", board_offset)); + t->count = smbios_add_string(t->eos, format_pn("Product P/N: ", product_offset)); +} + #if CONFIG(HAVE_ACPI_TABLES) static void mainboard_acpi_fill_ssdt(const struct device *dev) { @@ -215,6 +237,7 @@ mb_usb2_fp2_pwr_enable(1); dev->ops->final = mainboard_final; + dev->ops->get_smbios_strings = mainboard_smbios_strings; #if CONFIG(HAVE_ACPI_TABLES) dev->ops->acpi_fill_ssdt = mainboard_acpi_fill_ssdt; -- To view, visit https://review.coreboot.org/c/coreboot/+/67759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c17ab37859c3306fe72c3f0cdc1d3787b48157 Gerrit-Change-Number: 67759 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/inteltool: Add support for (non-ULT) Broadwell
by Martin Roth (Code Review) 08 Oct '22

08 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68186 ) Change subject: util/inteltool: Add support for (non-ULT) Broadwell ...................................................................... util/inteltool: Add support for (non-ULT) Broadwell Add support for traditional (non-ULT) Broadwell. Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 743cd1a..8f66237 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -107,6 +107,10 @@ "4th generation (Haswell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D, + "5th generation (Broadwell family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M, + "5th generation (Broadwell family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M, "6th generation (Skylake-H family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 44201b1..091e592 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -333,6 +333,8 @@ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D 0x1610 /* Broadwell (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M 0x1614 /* Broadwell (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 36d1197..a536d39 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -206,6 +206,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index d392c28..fb29d32 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -250,6 +250,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: @@ -369,6 +371,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ @@ -496,6 +500,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: -- To view, visit https://review.coreboot.org/c/coreboot/+/68186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Gerrit-Change-Number: 68186 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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