Attention is currently required from: Tim Crawford, Raul Rangel, Karthik Ramasubramanian.
Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60174 )
Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Is this ready to land?
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Gerrit-Change-Number: 60174
Gerrit-PatchSet: 2
Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
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Change subject: Documentation: Add wake source info to device tree documentation
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Is this ready to land now?
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Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph.
Iman Bingi has uploaded a new patch set (#78) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 )
Change subject: payloads/cbui: Add new payload CBUI
......................................................................
payloads/cbui: Add new payload CBUI
Depends on libpayload and nuklear.
Features:
* Graphical menus with scrolling.
* Text rendering engine (atm only bitmap font)
* Support for keyboard and mouse
* Support for USB and PS/2 devices
* Ported coreinfo and nvramcui
* Allows to modify NVRAM and RTC
* Works as ELF payload
* Works as Seabios secondary payload
* Basic support for multiple languages
* Hacky support for BIOS calls (depends on NASM)
* Runs in qemu and on real hardware
* Use linker script to allocate low memory
Shortcomings:
* Doesn't work in VGA text mode
* Untested on UEFI
* int32 relocates itself to low memory
Licenses:
* GPLv2 (CBUI + libpayload)
* BSD (libpayload)
* MIT (nuklear)
TODO:
* Test on as much platforms as possible
* Link int32 into low memory
This is Patrick Rudolph's original patch, updated by
Ben Adu-Boahen to:
* Add Read/Write module
* This module allows read/write to any hardware
component that is readable/writeable
Note:
This is work in progress
Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com>
---
M payloads/Kconfig
M payloads/Makefile.inc
A payloads/cbui/.gitignore
A payloads/cbui/Kconfig
A payloads/cbui/Makefile
A payloads/cbui/NuklearUI/NuklearCombo.c
A payloads/cbui/NuklearUI/NuklearCombo.h
A payloads/cbui/NuklearUI/NuklearCommon.h
A payloads/cbui/NuklearUI/NuklearDataGrid.c
A payloads/cbui/NuklearUI/NuklearDataGrid.h
A payloads/cbui/NuklearUI/NuklearDatePicker.c
A payloads/cbui/NuklearUI/NuklearDatePicker.h
A payloads/cbui/NuklearUI/NuklearFieldFile.c
A payloads/cbui/NuklearUI/NuklearFieldFile.h
A payloads/cbui/NuklearUI/NuklearFieldHex.c
A payloads/cbui/NuklearUI/NuklearFieldHex.h
A payloads/cbui/NuklearUI/NuklearFileChooser.c
A payloads/cbui/NuklearUI/NuklearFileChooser.h
A payloads/cbui/NuklearUI/NuklearGroup.c
A payloads/cbui/NuklearUI/NuklearGroup.h
A payloads/cbui/NuklearUI/NuklearHex.c
A payloads/cbui/NuklearUI/NuklearHex.h
A payloads/cbui/NuklearUI/NuklearIntegerRange.c
A payloads/cbui/NuklearUI/NuklearIntegerRange.h
A payloads/cbui/NuklearUI/NuklearLabel.c
A payloads/cbui/NuklearUI/NuklearLabel.h
A payloads/cbui/NuklearUI/NuklearObject.c
A payloads/cbui/NuklearUI/NuklearObject.h
A payloads/cbui/NuklearUI/NuklearPciHeader.c
A payloads/cbui/NuklearUI/NuklearPciHeader.h
A payloads/cbui/NuklearUI/NuklearRW.c
A payloads/cbui/NuklearUI/NuklearRW.h
A payloads/cbui/NuklearUI/NuklearRoot.c
A payloads/cbui/NuklearUI/NuklearRwAcpi.c
A payloads/cbui/NuklearUI/NuklearRwAcpi.h
A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c
A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h
A payloads/cbui/NuklearUI/NuklearRwClock.c
A payloads/cbui/NuklearUI/NuklearRwClock.h
A payloads/cbui/NuklearUI/NuklearRwCpuMsr.c
A payloads/cbui/NuklearUI/NuklearRwCpuMsr.h
A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c
A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h
A payloads/cbui/NuklearUI/NuklearRwE820.c
A payloads/cbui/NuklearUI/NuklearRwE820.h
A payloads/cbui/NuklearUI/NuklearRwEc.c
A payloads/cbui/NuklearUI/NuklearRwEc.h
A payloads/cbui/NuklearUI/NuklearRwIo.c
A payloads/cbui/NuklearUI/NuklearRwIo.h
A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c
A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h
A payloads/cbui/NuklearUI/NuklearRwMemory.c
A payloads/cbui/NuklearUI/NuklearRwMemory.h
A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c
A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h
A payloads/cbui/NuklearUI/NuklearRwNvram.c
A payloads/cbui/NuklearUI/NuklearRwNvram.h
A payloads/cbui/NuklearUI/NuklearRwPci.c
A payloads/cbui/NuklearUI/NuklearRwPci.h
A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c
A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h
A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.c
A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.h
A payloads/cbui/NuklearUI/NuklearRwSmbios.c
A payloads/cbui/NuklearUI/NuklearRwSmbios.h
A payloads/cbui/NuklearUI/NuklearRwSmbus.c
A payloads/cbui/NuklearUI/NuklearRwSmbus.h
A payloads/cbui/NuklearUI/NuklearRwSmram.c
A payloads/cbui/NuklearUI/NuklearRwSmram.h
A payloads/cbui/NuklearUI/NuklearRwSuperIo.c
A payloads/cbui/NuklearUI/NuklearRwSuperIo.h
A payloads/cbui/NuklearUI/NuklearRwUsb.c
A payloads/cbui/NuklearUI/NuklearRwUsb.h
A payloads/cbui/NuklearUI/NuklearStyle.c
A payloads/cbui/NuklearUI/NuklearStyle.h
A payloads/cbui/NuklearUI/NuklearTabView.c
A payloads/cbui/NuklearUI/NuklearTextView.c
A payloads/cbui/NuklearUI/NuklearTextView.h
A payloads/cbui/NuklearUI/NuklearTextfield.c
A payloads/cbui/NuklearUI/NuklearTextfield.h
A payloads/cbui/NuklearUI/NuklearTimePicker.c
A payloads/cbui/NuklearUI/NuklearTimePicker.h
A payloads/cbui/NuklearUI/NuklearUI.h
A payloads/cbui/NuklearUI/NuklearVector.c
A payloads/cbui/NuklearUI/NuklearVector.h
A payloads/cbui/arch/x86/cpuid.c
A payloads/cbui/arch/x86/cpuid.h
A payloads/cbui/arch/x86/int32.h
A payloads/cbui/arch/x86/int32.ld
A payloads/cbui/arch/x86/int32.nasm
A payloads/cbui/arch/x86/memcpy.c
A payloads/cbui/arch/x86/memcpy.h
A payloads/cbui/arch/x86/vga.c
A payloads/cbui/arch/x86/vga.h
A payloads/cbui/cbui.c
A payloads/cbui/cbui.h
A payloads/cbui/fsys/usbstorage.c
A payloads/cbui/fsys/usbstorage.h
A payloads/cbui/gfx/coreboot.c
A payloads/cbui/gfx/coreboot.h
A payloads/cbui/gfx/gfx.c
A payloads/cbui/gfx/gfx.h
A payloads/cbui/gfx/splash.c
A payloads/cbui/gfx/splash.h
A payloads/cbui/gfx/vbe.c
A payloads/cbui/gfx/vbe.h
A payloads/cbui/lang/de.c
A payloads/cbui/lang/en.c
A payloads/cbui/lang/lang.c
A payloads/cbui/lang/lang.h
A payloads/cbui/logo/cbui.png
A payloads/cbui/lp.config
A payloads/cbui/modules/bootlog_module.c
A payloads/cbui/modules/cbfs_module.c
A payloads/cbui/modules/cmos_module.c
A payloads/cbui/modules/coreboot_module.c
A payloads/cbui/modules/cpuinfo_module.c
A payloads/cbui/modules/license_module.c
A payloads/cbui/modules/modules.c
A payloads/cbui/modules/modules.h
A payloads/cbui/modules/nvram_module.c
A payloads/cbui/modules/pci_module.c
A payloads/cbui/modules/reboot_module.c
A payloads/cbui/modules/rtc_module.c
A payloads/cbui/modules/rw_module.c
A payloads/cbui/modules/timestamps_module.c
A payloads/cbui/modules/usb_module.c
A payloads/libpayload/configs/defconfig-cbui
128 files changed, 15,587 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/78
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1
Gerrit-Change-Number: 23586
Gerrit-PatchSet: 78
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Attention is currently required from: Martin L Roth.
Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68196 )
Change subject: mb/amd/birman: Add framework for morgana crb birman
......................................................................
Patch Set 2: Code-Review+1
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Gerrit-Change-Id: I4b16854c954949217a76c3d4f04ddc4001f64337
Gerrit-Change-Number: 68196
Gerrit-PatchSet: 2
Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
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Gerrit-Comment-Date: Fri, 07 Oct 2022 19:50:40 +0000
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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68195 )
Change subject: soc/amd/morgana: Add initial commit for new SoC
......................................................................
Patch Set 2: Code-Review+1
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Gerrit-Change-Number: 68195
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Gerrit-Comment-Date: Fri, 07 Oct 2022 19:44:15 +0000
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Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph.
Iman Bingi has uploaded a new patch set (#77) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 )
Change subject: payloads/cbui: Add new payload CBUI
......................................................................
payloads/cbui: Add new payload CBUI
Depends on libpayload and nuklear.
Features:
* Graphical menus with scrolling.
* Text rendering engine (atm only bitmap font)
* Support for keyboard and mouse
* Support for USB and PS/2 devices
* Ported coreinfo and nvramcui
* Allows to modify NVRAM and RTC
* Works as ELF payload
* Works as Seabios secondary payload
* Basic support for multiple languages
* Hacky support for BIOS calls (depends on NASM)
* Runs in qemu and on real hardware
* Use linker script to allocate low memory
Shortcomings:
* Doesn't work in VGA text mode
* Untested on UEFI
* int32 relocates itself to low memory
Licenses:
* GPLv2 (CBUI + libpayload)
* BSD (libpayload)
* MIT (nuklear)
TODO:
* Test on as much platforms as possible
* Link int32 into low memory
This is Patrick Rudolph's original patch, updated by
Ben Adu-Boahen to:
* Add Read/Write module
* This module allows read/write to any hardware
component that is readable/writeable
Note:
This is work in progress
Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com>
---
M payloads/Kconfig
M payloads/Makefile.inc
A payloads/cbui/.gitignore
A payloads/cbui/Kconfig
A payloads/cbui/Makefile
A payloads/cbui/NuklearUI/NuklearCombo.c
A payloads/cbui/NuklearUI/NuklearCombo.h
A payloads/cbui/NuklearUI/NuklearCommon.h
A payloads/cbui/NuklearUI/NuklearDataGrid.c
A payloads/cbui/NuklearUI/NuklearDataGrid.h
A payloads/cbui/NuklearUI/NuklearDatePicker.c
A payloads/cbui/NuklearUI/NuklearDatePicker.h
A payloads/cbui/NuklearUI/NuklearFieldFile.c
A payloads/cbui/NuklearUI/NuklearFieldFile.h
A payloads/cbui/NuklearUI/NuklearFieldHex.c
A payloads/cbui/NuklearUI/NuklearFieldHex.h
A payloads/cbui/NuklearUI/NuklearFileChooser.c
A payloads/cbui/NuklearUI/NuklearFileChooser.h
A payloads/cbui/NuklearUI/NuklearGroup.c
A payloads/cbui/NuklearUI/NuklearGroup.h
A payloads/cbui/NuklearUI/NuklearHex.c
A payloads/cbui/NuklearUI/NuklearHex.h
A payloads/cbui/NuklearUI/NuklearIntegerRange.c
A payloads/cbui/NuklearUI/NuklearIntegerRange.h
A payloads/cbui/NuklearUI/NuklearLabel.c
A payloads/cbui/NuklearUI/NuklearLabel.h
A payloads/cbui/NuklearUI/NuklearObject.c
A payloads/cbui/NuklearUI/NuklearObject.h
A payloads/cbui/NuklearUI/NuklearPciHeader.c
A payloads/cbui/NuklearUI/NuklearPciHeader.h
A payloads/cbui/NuklearUI/NuklearRW.c
A payloads/cbui/NuklearUI/NuklearRW.h
A payloads/cbui/NuklearUI/NuklearRoot.c
A payloads/cbui/NuklearUI/NuklearRwAcpi.c
A payloads/cbui/NuklearUI/NuklearRwAcpi.h
A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c
A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h
A payloads/cbui/NuklearUI/NuklearRwClock.c
A payloads/cbui/NuklearUI/NuklearRwClock.h
A payloads/cbui/NuklearUI/NuklearRwCpuMsr.c
A payloads/cbui/NuklearUI/NuklearRwCpuMsr.h
A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c
A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h
A payloads/cbui/NuklearUI/NuklearRwE820.c
A payloads/cbui/NuklearUI/NuklearRwE820.h
A payloads/cbui/NuklearUI/NuklearRwEc.c
A payloads/cbui/NuklearUI/NuklearRwEc.h
A payloads/cbui/NuklearUI/NuklearRwIo.c
A payloads/cbui/NuklearUI/NuklearRwIo.h
A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c
A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h
A payloads/cbui/NuklearUI/NuklearRwMemory.c
A payloads/cbui/NuklearUI/NuklearRwMemory.h
A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c
A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h
A payloads/cbui/NuklearUI/NuklearRwNvram.c
A payloads/cbui/NuklearUI/NuklearRwNvram.h
A payloads/cbui/NuklearUI/NuklearRwPci.c
A payloads/cbui/NuklearUI/NuklearRwPci.h
A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c
A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h
A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.c
A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.h
A payloads/cbui/NuklearUI/NuklearRwSmbios.c
A payloads/cbui/NuklearUI/NuklearRwSmbios.h
A payloads/cbui/NuklearUI/NuklearRwSmbus.c
A payloads/cbui/NuklearUI/NuklearRwSmbus.h
A payloads/cbui/NuklearUI/NuklearRwSmram.c
A payloads/cbui/NuklearUI/NuklearRwSmram.h
A payloads/cbui/NuklearUI/NuklearRwSuperIo.c
A payloads/cbui/NuklearUI/NuklearRwSuperIo.h
A payloads/cbui/NuklearUI/NuklearRwUsb.c
A payloads/cbui/NuklearUI/NuklearRwUsb.h
A payloads/cbui/NuklearUI/NuklearStyle.c
A payloads/cbui/NuklearUI/NuklearStyle.h
A payloads/cbui/NuklearUI/NuklearTabView.c
A payloads/cbui/NuklearUI/NuklearTextView.c
A payloads/cbui/NuklearUI/NuklearTextView.h
A payloads/cbui/NuklearUI/NuklearTextfield.c
A payloads/cbui/NuklearUI/NuklearTextfield.h
A payloads/cbui/NuklearUI/NuklearTimePicker.c
A payloads/cbui/NuklearUI/NuklearTimePicker.h
A payloads/cbui/NuklearUI/NuklearUI.h
A payloads/cbui/NuklearUI/NuklearVector.c
A payloads/cbui/NuklearUI/NuklearVector.h
A payloads/cbui/arch/x86/cpuid.c
A payloads/cbui/arch/x86/cpuid.h
A payloads/cbui/arch/x86/int32.h
A payloads/cbui/arch/x86/int32.ld
A payloads/cbui/arch/x86/int32.nasm
A payloads/cbui/arch/x86/memcpy.c
A payloads/cbui/arch/x86/memcpy.h
A payloads/cbui/arch/x86/vga.c
A payloads/cbui/arch/x86/vga.h
A payloads/cbui/cbui.c
A payloads/cbui/cbui.h
A payloads/cbui/fsys/usbstorage.c
A payloads/cbui/fsys/usbstorage.h
A payloads/cbui/gfx/coreboot.c
A payloads/cbui/gfx/coreboot.h
A payloads/cbui/gfx/gfx.c
A payloads/cbui/gfx/gfx.h
A payloads/cbui/gfx/splash.c
A payloads/cbui/gfx/splash.h
A payloads/cbui/gfx/vbe.c
A payloads/cbui/gfx/vbe.h
A payloads/cbui/lang/de.c
A payloads/cbui/lang/en.c
A payloads/cbui/lang/lang.c
A payloads/cbui/lang/lang.h
A payloads/cbui/logo/cbui.png
A payloads/cbui/lp.config
A payloads/cbui/modules/bootlog_module.c
A payloads/cbui/modules/cbfs_module.c
A payloads/cbui/modules/cmos_module.c
A payloads/cbui/modules/coreboot_module.c
A payloads/cbui/modules/cpuinfo_module.c
A payloads/cbui/modules/license_module.c
A payloads/cbui/modules/modules.c
A payloads/cbui/modules/modules.h
A payloads/cbui/modules/nvram_module.c
A payloads/cbui/modules/pci_module.c
A payloads/cbui/modules/reboot_module.c
A payloads/cbui/modules/rtc_module.c
A payloads/cbui/modules/rw_module.c
A payloads/cbui/modules/timestamps_module.c
A payloads/cbui/modules/usb_module.c
A payloads/libpayload/configs/defconfig-cbui
128 files changed, 15,587 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/77
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68224 )
Change subject: mb/prodrive/atlas: Print HSID
......................................................................
Patch Set 1: Code-Review+1
(5 comments)
File src/mainboard/prodrive/atlas/gpio.c:
https://review.coreboot.org/c/coreboot/+/68224/comment/65d21445_e9f783b8
PS1, Line 10: PAD_CFG_GPI(GPP_A8, NONE, RSMRST), /* HSID_0 */
We should probably configure the GPIOs early in bootblock, as in the future we might need to read the HSID in pre-RAM.
File src/mainboard/prodrive/atlas/mainboard.c:
https://review.coreboot.org/c/coreboot/+/68224/comment/1ae93db6_dedae1bd
PS1, Line 7: #include <arch/io.h>
nit: alphabetical order?
https://review.coreboot.org/c/coreboot/+/68224/comment/25786754_b0bafd74
PS1, Line 11: static void print_hsid(void)
We probably want to have a `uint8_t get_hsid()` function instead, in case we need to deal with revision-specific differences.
```
uint8_t get_hsid(void)
{
const gpio_t hsid_gpios[] = {
GPP_A8,
GPP_F19,
GPP_H23,
GPP_H19,
};
return gpio_base2_value(hsid_gpios, ARRAY_SIZE(hsid_gpios));
}
static void mainboard_init(void *chip_info)
{
configure_gpio_pads();
printk(BIOS_INFO, "HSID: 0x%x\n", get_hsid());
}
```
https://review.coreboot.org/c/coreboot/+/68224/comment/6816a11f_966d0d6e
PS1, Line 14: <
This is not a shift! 😄
Also, there's `gpio_base2_value()`
https://review.coreboot.org/c/coreboot/+/68224/comment/5f0f9e1c_d695f24e
PS1, Line 17: 1
No need to restrict the print width, it may actually make bugs harder to diagnose.
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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68227 )
Change subject: soc/amd/mendocino/psp_verstage: Remove TODO comment
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/prodrive/atlas: Disable C-States & cTDP
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68222/comment/78a6b3ea_37ed8b40
PS1, Line 9: required
"required" sounds wrong here. How about:
As Atlas is targeted towards industrial use cases:
https://review.coreboot.org/c/coreboot/+/68222/comment/f8cebabe_06453423
PS1, Line 11: - Disable all C-states other than C0/C1 for CPU and package
Maybe add Kconfig options, so that it's easy to re-enable them for testing?
The main source of "annoyance" is that enabling SaGv (a power saving feature) and disabling C-states (another power saving feature) at the same time makes no sense outside of testing environments. In any case, this will probably end up being runtime configurable.
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