coreboot-gerrit October 2022

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[L] Change in coreboot[master]: util/inteltool: Add support for Alderlake P in inteltool
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66825 ) ( 15 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/inteltool: Add support for Alderlake P in inteltool ...................................................................... util/inteltool: Add support for Alderlake P in inteltool TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P Document number: 626817, 630094, 655258 Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Signed-off-by: Kacper Stojek <kacper.stojek(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825 Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/alderlake_p.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 661 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index dc2ed77..aa52592 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1106,6 +1106,9 @@ case PCI_DEVICE_ID_INTEL_HM670: case PCI_DEVICE_ID_INTEL_WM790: case PCI_DEVICE_ID_INTEL_HM770: + case PCI_DEVICE_ID_INTEL_ADL_P: + case PCI_DEVICE_ID_INTEL_ADL_M: + case PCI_DEVICE_ID_INTEL_RPL_P: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 28a5f65..b50cc80 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -20,6 +20,7 @@ #include "gpio_names/sunrise.h" #include "gpio_names/tigerlake.h" #include "gpio_names/alderlake_h.h" +#include "gpio_names/alderlake_p.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) @@ -217,6 +218,13 @@ *community_count = ARRAY_SIZE(alderlake_pch_h_communities); *pad_stepping = 16; return alderlake_pch_h_communities; + case PCI_DEVICE_ID_INTEL_ADL_P: + case PCI_DEVICE_ID_INTEL_ADL_M: + case PCI_DEVICE_ID_INTEL_RPL_P: + *community_count = ARRAY_SIZE(alderlake_pch_p_communities); + *pad_stepping = 16; + return alderlake_pch_p_communities; + default: return NULL; } diff --git a/util/inteltool/gpio_names/alderlake_p.h b/util/inteltool/gpio_names/alderlake_p.h new file mode 100644 index 0000000..79d5ce7 --- /dev/null +++ b/util/inteltool/gpio_names/alderlake_p.h @@ -0,0 +1,616 @@ +#ifndef GPIO_NAMES_ALDERLAKE_P +#define GPIO_NAMES_ALDERLAKE_P + +#include "gpio_groups.h" + +/* ----------------------------- Alder Lake P ----------------------------- */ + +const char *const alderlake_pch_p_group_a_names[] = { + "GPP_A0", "ESPI_IO0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A0", + "GPP_A1", "ESPI_IO1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A1", + "GPP_A2", "ESPI_IO2", "SUSWARN# / SUSPWRDNACK", "n/a", "n/a", "n/a", "USB_C_GPP_A2", + "GPP_A3", "ESPI_IO3", "SUSACK#", "n/a", "n/a", "n/a", "USB_C_GPP_A3", + "GPP_A4", "ESPI_CS0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A4", + "GPP_A5", "ESPI_ALERT0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A5", + "GPP_A6", "ESPI_ALERT1#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A6", + "GPP_A7", "SRCCLK_OE7#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A7", + "GPP_A8", "SRCCLKREQ7#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A8", + "GPP_A9", "ESPI_CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A9", + "GPP_A10", "ESPI_RESET#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A10", + "GPP_A11", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A11", + "GPP_A12", "SATAXPCIE1", "SATAGP1", "n/a", "SRCCLKREQ9B#", "n/a", "USB_C_GPP_A12", + "GPP_A13", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A13", + "GPP_A14", "USB_OC1#", "DDSP_HPD3", "n/a", "DISP_MISC3", "n/a", "USB_C_GPP_A14", + "GPP_A15", "USB_OC2#", "DDSP_HPD4", "n/a", "DISP_MISC4", "n/a", "USB_C_GPP_A15", + "GPP_A16", "USB_OC3#", "n/a", "n/a", "ISH_GP5", "n/a", "USB_C_GPP_A16", + "GPP_A17", "n/a", "n/a", "n/a", "DISP_MISCC", "n/a", "USB_C_GPP_A17", + "GPP_A18", "DDSP_HPDB", "n/a", "n/a", "DISP_MISCB", "n/a", "USB_C_GPP_A18", + "GPP_A19", "DDSP_HPD1", "n/a", "n/a", "DISP_MISC1", "n/a", "USB_C_GPP_A19", + "GPP_A20", "DDSP_HPD2", "n/a", "n/a", "DISP_MISC2", "n/a", "USB_C_GPP_A20", + "GPP_A21", "DDPC_CTRLCLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A21", + "GPP_A22", "DDPC_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A22", + "GPP_A23", "ESPI_CS1#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A23", + "GPP_ESPI_CLK_LOOPBK", "GPP_ESPI_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_a_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_p_group_a_names, +}; + +const char *const alderlake_pch_p_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B0", + "GPP_B1", "CORE_VID1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B1", + "GPP_B2", "VRALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B2", + "GPP_B3", "PROC_GP2", "n/a", "n/a", "ISH_GP4B", "n/a", "USB_C_GPP_B3", + "GPP_B4", "PROC_GP3", "n/a", "n/a", "ISH_GP5B", "n/a", "USB_C_GPP_B4", + "GPP_B5", "ISH_I2C0_SDA", "I2C2_SDA", "n/a", "n/a", "n/a", "USB_C_GPP_B5", + "GPP_B6", "ISH_I2C0_SCL", "I2C2_SCL", "n/a", "n/a", "n/a", "USB_C_GPP_B6", + "GPP_B7", "ISH_I2C1_SDA", "I2C3_SDA", "n/a", "n/a", "n/a", "USB_C_GPP_B7", + "GPP_B8", "ISH_I2C1_SCL", "I2C3_SCL", "n/a", "n/a", "n/a", "USB_C_GPP_B8", + "GPP_B9", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B10", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B11", "PMCALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B11", + "GPP_B12", "SLP_S0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B12", + "GPP_B13", "PLTRST#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B13", + "GPP_B14", "SPKR", "TIME_SYNC1", "n/a", "SATA_LED#", "ISH_GP6", "USB_C_GPP_B14", + "GPP_B15", "n/a", "TIME_SYNC0", "n/a", "n/a", "ISH_GP7", "USB_C_GPP_B15", + "GPP_B16", "n/a", "I2C5_SDA", "n/a", "ISH_I2C2_SDA", "n/a", "USB_C_GPP_B16", + "GPP_B17", "n/a", "I2C5_SCL", "n/a", "ISH_I2C2_SCL", "n/a", "USB_C_GPP_B17", + "GPP_B18", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B18", + "GPP_B19", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B20", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B21", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B22", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", "n/a", "n/a", "USB_C_GPP_B23", + "GPP_B24", "GSPI0_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B25", "GSPI1_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_b_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_p_group_b_names, +}; + +const char *const alderlake_pch_p_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C0", + "GPP_C1", "SMBDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C1", + "GPP_C2", "SMBALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C2", + "GPP_C3", "SML0CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C3", + "GPP_C4", "SML0DATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C4", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C5", + "GPP_C6", "SML1CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C6", + "GPP_C7", "SML1DATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C7", + "GPP_C8", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C9", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C10", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C11", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C12", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C13", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C14", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C15", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C16", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C17", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C18", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C19", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C20", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C21", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C22", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C23", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_c_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_p_group_c_names, +}; + +const char *const alderlake_pch_p_group_d_names[] = { + "GPP_D0", "ISH_GP0", "BK0", "n/a", "n/a", "SBK0", "USB_C_GPP_D0", "n/a", + "GPP_D1", "ISH_GP1", "BK1", "n/a", "n/a", "SBK1", "USB_C_GPP_D1", "n/a", + "GPP_D2", "ISH_GP2", "BK2", "n/a", "n/a", "SBK2", "USB_C_GPP_D2", "n/a", + "GPP_D3", "ISH_GP3", "BK3", "n/a", "n/a", "SBK3", "USB_C_GPP_D3", "n/a", + "GPP_D4", "IMGCLKOUT0", "BK4", "n/a", "n/a", "SBK4", "USB_C_GPP_D4", "n/a", + "GPP_D5", "SRCCLKREQ0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D5", "n/a", + "GPP_D6", "SRCCLKREQ1#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D6", "n/a", + "GPP_D7", "SRCCLKREQ2#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D7", "n/a", + "GPP_D8", "SRCCLKREQ3#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D8", "n/a", + "GPP_D9", "ISH_SPI_CS#", "DDP3_CTRLCLK", "n/a", "TBT_LSX2_TXD", "BSSB_LS2_RX", "USB_C_GPP_D9", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "DDP3_CTRLDATA", "n/a", "TBT_LSX2_RXD", "BSSB_LS2_TX", "USB_C_GPP_D10", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "DDP4_CTRLCLK", "n/a", "TBT_LSX3_TXD", "BSSB_LS3_RX", "USB_C_GPP_D11", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "DDP4_CTRLDATA", "n/a", "TBT_LSX3_RXD", "BSSB_LS3_TX", "USB_C_GPP_D12", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C6_SDA", "n/a", "n/a", "USB_C_GPP_D13", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C6_SCL", "n/a", "n/a", "USB_C_GPP_D14", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", "I2C7B_SDA", "n/a", "USB_C_GPP_D15", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "I2C7B_SCL", "n/a", "USB_C_GPP_D16", "n/a", + "GPP_D17", "UART1_RXD", "ISH_UART1_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_D17", "n/a", + "GPP_D18", "UART1_TXD", "ISH_UART1_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_D18", "n/a", + "GPP_D19", "I2S_MCLK1_OUT", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D19", "n/a", + "GPP_GSPI2_CLK_LOOPBK", "GPP_GSPI2_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_d_names) / 8, + .func_count = 8, + .pad_names = alderlake_pch_p_group_d_names, +}; + +const char *const alderlake_pch_p_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", "n/a", "n/a", "USB_C_GPP_E0", "SRCCLKREQ9#", + "GPP_E1", "n/a", "THC0_SPI1_IO2", "n/a", "n/a", "n/a", "USB_C_GPP_E1", "n/a", + "GPP_E2", "n/a", "THC0_SPI1_IO3", "n/a", "n/a", "n/a", "USB_C_GPP_E2", "n/a", + "GPP_E3", "PROC_GP0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E3", "n/a", + "GPP_E4", "DEVSLP0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E4", "SRCCLK_OE9#", + "GPP_E5", "DEVSLP1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E5", "SRCCLK_OE6#", + "GPP_E6", "n/a", "THC0_SPI1_RST#", "n/a", "n/a", "n/a", "USB_C_GPP_E6", "n/a", + "GPP_E7", "PROC_GP1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E7", "n/a", + "GPP_E8", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E8", "n/a", + "GPP_E9", "USB_OC0#", "ISH_GP4", "n/a", "n/a", "n/a", "USB_C_GPP_E9", "n/a", + "GPP_E10", "n/a", "THC0_SPI1_CS#", "n/a", "n/a", "n/a", "USB_C_GPP_E10", "GSPI0_CS0#", + "GPP_E11", "n/a", "THC0_SPI1_CLK", "n/a", "n/a", "n/a", "USB_C_GPP_E11", "GSPI0_CLK", + "GPP_E12", "n/a", "THC0_SPI1_IO1", "n/a", "n/a", "I2C0A_SDA", "USB_C_GPP_E12", "GSPI0_MISO", + "GPP_E13", "n/a", "THC0_SPI1_IO0", "n/a", "n/a", "I2C0A_SCL", "USB_C_GPP_E13", "GSPI0_MOSI", + "GPP_E14", "DDSP_HPDA", "DISP_MISC_A", "n/a", "n/a", "n/a", "USB_C_GPP_E14", "n/a", + "GPP_E15", "n/a", "Reserved", "n/a", "n/a", "n/a", "USB_C_GPP_E15", "SRCCLK_OE8#", + "GPP_E16", "n/a", "Reserved", "n/a", "n/a", "n/a", "USB_C_GPP_E16", "SRCCLKREQ8#", + "GPP_E17", "n/a", "THC0_SPI1_INT#", "n/a", "n/a", "n/a", "USB_C_GPP_E17", "n/a", + "GPP_E18", "DDP1_CTRLCLK", "n/a", "n/a", "TBT_LSX0_TXD", "BSSB_LS0_RX", "USB_C_GPP_E18", "n/a", + "GPP_E19", "DDP1_CTRLDATA", "n/a", "n/a", "TBT_LSX0_RXD", "BSSB_LS0_TX", "USB_C_GPP_E19", "n/a", + "GPP_E20", "DDP2_CTRLCLK", "n/a", "n/a", "TBT_LSX1_TXD", "BSSB_LS1_RX", "USB_C_GPP_E20", "n/a", + "GPP_E21", "DDP2_CTRLDATA", "n/a", "n/a", "TBT_LSX1_RXD", "BSSB_LS1_TX", "USB_C_GPP_E21", "n/a", + "GPP_E22", "DDPA_CTRLCLK", "DNX_FORCE_RELOAD", "n/a", "n/a", "n/a", "USB_C_GPP_E22", "n/a", + "GPP_E23", "DDPA_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E23", "n/a", + "GPP_E_CLK_LOOPBK", "GPP_E_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_e_names) / 8, + .func_count = 8, + .pad_names = alderlake_pch_p_group_e_names, +}; + +const char *const alderlake_pch_p_group_f_names[] = { + "GPP_F0", "CNV_BRI_DT", "UART2_RTS#", "n/a", "n/a", "n/a", "USB_C_GPP_F0", + "GPP_F1", "CNV_BRI_RSP", "UART2_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_F1", + "GPP_F2", "CNV_RGI_DT", "UART2_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_F2", + "GPP_F3", "CNV_RGI_RSP", "UART2_CTS#", "n/a", "n/a", "n/a", "USB_C_GPP_F3", + "GPP_F4", "CNV_RF_RESET#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F4", + "GPP_F5", "n/a", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", "n/a", "n/a", "USB_C_GPP_F5", + "GPP_F6", "CNV_PA_BLANKING", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F6", + "GPP_F7", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F7", + "GPP_F8", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F9", "BOOTMPC", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F9", + "GPP_F10", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F10", + "GPP_F11", "n/a", "n/a", "THC1_SPI2_CLK", "GSPI1_CLK", "n/a", "USB_C_GPP_F11", + "GPP_F12", "GSXDOUT", "n/a", "THC1_SPI2_IO0", "GSPI1_MOSI", "I2C1A_SCL", "USB_C_GPP_F12", + "GPP_F13", "GSXSLOAD" , "n/a", "THC1_SPI2_IO1", "GSPI1_MISO", "I2C1A_SDA", "USB_C_GPP_F13", + "GPP_F14", "GSXDIN", "n/a", "THC1_SPI2_IO2", "n/a", "n/a", "USB_C_GPP_F14", + "GPP_F15", "GSXSRESET#", "n/a", "THC1_SPI2_IO3", "n/a", "n/a", "USB_C_GPP_F15", + "GPP_F16", "GSXCLK", "n/a", "THC1_SPI2_CS#", "GSPI_CS0#", "n/a", "USB_C_GPP_F16", + "GPP_F17", "n/a", "n/a", "THC1_SPI2_RST#", "n/a", "n/a", "USB_C_GPP_F17", + "GPP_F18", "n/a", "n/a", "THC1_SPI2_INT#", "n/a", "n/a", "USB_C_GPP_F18", + "GPP_F19", "SRCCLKREQ6#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F19", + "GPP_F20", "Reserved", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F20", + "GPP_F21", "Reserved", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F21", + "GPP_F22", "VNN_CTRL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F22", + "GPP_F23", "V1P05_CTRL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F23", + "GPP_F_CLK_LOOPBK", "GPP_F_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_f_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_p_group_f_names, +}; + +const char *const alderlake_pch_p_group_h_names[] = { + "GPP_H0", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H0", + "GPP_H1", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H1", + "GPP_H2", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H2", + "GPP_H3", "SX_EXIT_HOLDOFF#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H3", + "GPP_H4", "I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H4", + "GPP_H5", "I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H5", + "GPP_H6", "I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H6", + "GPP_H7", "I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H7", + "GPP_H8", "I2C4_SDA", "CNV_MFUART2_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_H8", + "GPP_H9", "I2C4_SCL", "CNV_MFUART2_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_H9", + "GPP_H10", "n/a", "UART0_RXD", "M2_SKT2_CFG0", "n/a", "n/a", "USB_C_GPP_H10", + "GPP_H11", "n/a", "UART0_TXD", "M2_SKT2_CFG1", "n/a", "n/a", "USB_C_GPP_H11", + "GPP_H12", "I2C7_SDA", "UART0_RTS#", "M2_SKT2_CFG2", "ISH_GP6B", "DEVSLP0B", "USB_C_GPP_H12", + "GPP_H13", "I2C7_SCL", "UART0_CTS#", "M2_SKT2_CFG3", "ISH_GP7B", "DEVSLP1B", "USB_C_GPP_H13", + "GPP_H14", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H15", "DDPB_CTRLCLK", "n/a", "PCIE_LINK_DOWN", "n/a", "n/a", "USB_C_GPP_H15", + "GPP_H16", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H17", "DDPB_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H17", + "GPP_H18", "PROC_C10_GATE#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H18", + "GPP_H19", "SRCCLKREQ4#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H19", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H20", + "GPP_H21", "IMGCLKOUT2", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H21", + "GPP_H22", "IMGCLKOUT3", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H22", + "GPP_H23", "n/a", "SRCCLKREQ5#", "n/a", "n/a", "n/a", "USB_C_GPP_H23", +}; + +const struct gpio_group alderlake_pch_p_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_h_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_p_group_h_names, +}; + +const char *const alderlake_pch_p_group_r_names[] = { + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", "DMIC_CLK_B0", "HDAPROC_BCLK", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", "DMIC_CLK_B1", "n/a", + "GPP_R2", "HDA_SDO", "I2S0_TXD", "n/a", "HDAPROC_SDO", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", "n/a", "HDAPROC_SDI", + "GPP_R4", "HDA_RST#", "I2S2_SCLK", "DMIC_CLK_A0", "n/a", + "GPP_R5", "HDA_SDI1", "I2S2_SFRM", "DMIC_DATA0", "n/a", + "GPP_R6", "n/a", "I2S2_TXD", "DMIC_CLK_A1", "n/a", + "GPP_R7", "n/a", "I2S2_RXD", "DMIC_DATA1", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_r = { + .display = "------- GPIO Group GPP_R -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_r_names) / 5, + .func_count = 5, + .pad_names = alderlake_pch_p_group_r_names, +}; + +const char *const alderlake_pch_p_group_s_names[] = { + "GPP_S0", "SNDW0_CLK", "n/a", "n/a", "I2S1_SCLK", + "GPP_S1", "SNDW0_DATA", "n/a", "n/a", "I2S1_SFRM", + "GPP_S2", "SNDW1_CLK", "DMIC_CKL_A0", "n/a", "I2S1_TXD", + "GPP_S3", "SNDW1_DATA", "DMIC_DATA0", "n/a", "I2S1_RXD", + "GPP_S4", "SNDW2_CLK", "DMIC_CLK_B0", "n/a", "n/a", + "GPP_S5", "SNDW2_DATA", "DMIC_CLK_B1", "n/a", "n/a", + "GPP_S6", "SNDW3_CLK", "DMIC_CLK_A1", "n/a", "n/a", + "GPP_S7", "SNDW3_DATA", "DMIC_DATA1", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_s = { + .display = "------- GPIO Group GPP_S -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_s_names) / 5, + .func_count = 5, + .pad_names = alderlake_pch_p_group_s_names, +}; + +const char *const alderlake_pch_p_group_t_names[] = { + "GPP_T0", "n/a", "n/a", + "GPP_T1", "n/a", "n/a", + "GPP_T2", "n/a", "Reserved", + "GPP_T3", "n/a", "Reserved", + "GPP_T4", "n/a", "n/a", + "GPP_T5", "n/a", "n/a", + "GPP_T6", "n/a", "n/a", + "GPP_T7", "n/a", "n/a", + "GPP_T8", "n/a", "n/a", + "GPP_T9", "n/a", "n/a", + "GPP_T10", "n/a", "n/a", + "GPP_T11", "n/a", "n/a", + "GPP_T12", "n/a", "n/a", + "GPP_T13", "n/a", "n/a", + "GPP_T14", "n/a", "n/a", + "GPP_T15", "n/a", "n/a", + }; + + +const struct gpio_group alderlake_pch_p_group_t = { + .display = "------- GPIO Group GPP_T -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_t_names) / 3, + .func_count = 3, + .pad_names = alderlake_pch_p_group_t_names, +}; + +const char *const alderlake_pch_p_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PWRBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", + "GPD_INPUT3VSEL", "GPD_INPUT3VSEL", + "GPD_SLP_LANB", "GPD_SLP_LANB", + "GPD_SLP_SUSB", "GPD_SLP_SUSB", + "GPD_WAKEB", "GPD_WAKEB", + "GPD_DRAM_RESETB", "GPD_DRAM_RESETB", +}; + +const struct gpio_group alderlake_pch_p_group_gpd = { + .display = "------- GPIO Group GPP_GPD -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_gpd_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_p_group_gpd_names, +}; + +const char *const alderlake_pch_p_group_hvcmos_names[] = { + "GPP_L_BKLTEN", "n/a", + "GPP_L_BKLTCTL", "n/a", + "GPP_L_VDDEN", "n/a", + "GPP_SYS_PWROK", "n/a", + "GPP_SYS_RESETB", "n/a", + "GPP_MLK_RSTB", "n/a", +}; + +const struct gpio_group alderlake_pch_p_group_hvcmos = { + .display = "------- GPIO Group GPP_HVCMOS -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_hvcmos_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_p_group_hvcmos_names, +}; + +const char *const alderlake_pch_p_group_reserved_names[] = { + "GPP_CPU_RSVD_1", "GPP_CPU_RSVD_1", + "GPP_CPU_RSVD_2", "GPP_CPU_RSVD_2", + "GPP_CPU_RSVD_3", "GPP_CPU_RSVD_3", + "GPP_CPU_RSVD_4", "GPP_CPU_RSVD_4", + "GPP_CPU_RSVD_5", "GPP_CPU_RSVD_5", + "GPP_CPU_RSVD_6", "GPP_CPU_RSVD_6", + "GPP_CPU_RSVD_7", "GPP_CPU_RSVD_7", + "GPP_CPU_RSVD_8", "GPP_CPU_RSVD_8", + "GPP_CPU_RSVD_9", "GPP_CPU_RSVD_9", + "GPP_CPU_RSVD_10", "GPP_CPU_RSVD_10", + "GPP_CPU_RSVD_11", "GPP_CPU_RSVD_11", + "GPP_CPU_RSVD_12", "GPP_CPU_RSVD_12", + "GPP_CPU_RSVD_13", "GPP_CPU_RSVD_13", + "GPP_CPU_RSVD_14", "GPP_CPU_RSVD_14", + "GPP_CPU_RSVD_15", "GPP_CPU_RSVD_15", + "GPP_CPU_RSVD_16", "GPP_CPU_RSVD_16", + "GPP_CPU_RSVD_17", "GPP_CPU_RSVD_17", + "GPP_CPU_RSVD_18", "GPP_CPU_RSVD_18", + "GPP_CPU_RSVD_19", "GPP_CPU_RSVD_19", + "GPP_CPU_RSVD_20", "GPP_CPU_RSVD_20", + "GPP_CPU_RSVD_21", "GPP_CPU_RSVD_21", + "GPP_CPU_RSVD_22", "GPP_CPU_RSVD_22", + "GPP_CPU_RSVD_23", "GPP_CPU_RSVD_23", + "GPP_CPU_RSVD_24", "GPP_CPU_RSVD_24", +}; + +const struct gpio_group alderlake_pch_p_group_reserved = { + .display = "------- GPIO Group RESERVED -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_reserved_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_p_group_reserved_names, +}; + +const char *const alderlake_pch_p_group_vgpio_names[] = { + "GPP_VGPIO_0", "GPP_VGPIO_0", + "GPP_VGPIO_4", "GPP_VGPIO_4", + "GPP_VGPIO_5", "GPP_VGPIO_5", + "GPP_VGPIO_6", "GPP_VGPIO_6", + "GPP_VGPIO_7", "GPP_VGPIO_7", + "GPP_VGPIO_8", "GPP_VGPIO_8", + "GPP_VGPIO_9", "GPP_VGPIO_9", + "GPP_VGPIO_10", "GPP_VGPIO_10", + "GPP_VGPIO_11", "GPP_VGPIO_11", + "GPP_VGPIO_12", "GPP_VGPIO_12", + "GPP_VGPIO_13", "GPP_VGPIO_13", + "GPP_VGPIO_18", "GPP_VGPIO_18", + "GPP_VGPIO_19", "GPP_VGPIO_19", + "GPP_VGPIO_20", "GPP_VGPIO_20", + "GPP_VGPIO_21", "GPP_VGPIO_21", + "GPP_VGPIO_22", "GPP_VGPIO_22", + "GPP_VGPIO_23", "GPP_VGPIO_23", + "GPP_VGPIO_24", "GPP_VGPIO_24", + "GPP_VGPIO_25", "GPP_VGPIO_25", + "GPP_VGPIO_30", "GPP_VGPIO_30", + "GPP_VGPIO_31", "GPP_VGPIO_31", + "GPP_VGPIO_32", "GPP_VGPIO_32", + "GPP_VGPIO_33", "GPP_VGPIO_33", + "GPP_VGPIO_34", "GPP_VGPIO_34", + "GPP_VGPIO_35", "GPP_VGPIO_35", + "GPP_VGPIO_36", "GPP_VGPIO_36", + "GPP_VGPIO_37", "GPP_VGPIO_37", +}; + +const struct gpio_group alderlake_pch_p_group_vgpio = { + .display = "------- GPIO Group vGPIO -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_p_group_vgpio_names, +}; + + +const char *const alderlake_pch_p_group_pcie_vgpio_names[] = { + "GPP_CPU_RSVD_25", "GPP_CPU_RSVD_25", + "GPP_CPU_RSVD_26", "GPP_CPU_RSVD_26", + "GPP_CPU_RSVD_27", "GPP_CPU_RSVD_27", + "GPP_CPU_RSVD_28", "GPP_CPU_RSVD_28", + "GPP_CPU_RSVD_29", "GPP_CPU_RSVD_29", + "GPP_CPU_RSVD_30", "GPP_CPU_RSVD_30", + "GPP_CPU_RSVD_31", "GPP_CPU_RSVD_31", + "GPP_CPU_RSVD_32", "GPP_CPU_RSVD_32", + "GPP_CPU_RSVD_33", "GPP_CPU_RSVD_33", + "GPP_CPU_RSVD_34", "GPP_CPU_RSVD_34", + "GPP_CPU_RSVD_35", "GPP_CPU_RSVD_35", + "GPP_CPU_RSVD_36", "GPP_CPU_RSVD_36", + "GPP_CPU_RSVD_37", "GPP_CPU_RSVD_37", + "GPP_CPU_RSVD_38", "GPP_CPU_RSVD_38", + "GPP_CPU_RSVD_39", "GPP_CPU_RSVD_39", + "GPP_vGPIO_PCIE_0", "GPP_vGPIO_PCIE_0", + "GPP_vGPIO_PCIE_1", "GPP_vGPIO_PCIE_1", + "GPP_vGPIO_PCIE_2", "GPP_vGPIO_PCIE_2", + "GPP_vGPIO_PCIE_3", "GPP_vGPIO_PCIE_3", + "GPP_vGPIO_PCIE_4", "GPP_vGPIO_PCIE_4", + "GPP_vGPIO_PCIE_5", "GPP_vGPIO_PCIE_5", + "GPP_vGPIO_PCIE_6", "GPP_vGPIO_PCIE_6", + "GPP_vGPIO_PCIE_7", "GPP_vGPIO_PCIE_7", + "GPP_vGPIO_PCIE_8", "GPP_vGPIO_PCIE_8", + "GPP_vGPIO_PCIE_9", "GPP_vGPIO_PCIE_9", + "GPP_vGPIO_PCIE_10", "GPP_vGPIO_PCIE_10", + "GPP_vGPIO_PCIE_11", "GPP_vGPIO_PCIE_11", + "GPP_vGPIO_PCIE_12", "GPP_vGPIO_PCIE_12", + "GPP_vGPIO_PCIE_13", "GPP_vGPIO_PCIE_13", + "GPP_vGPIO_PCIE_14", "GPP_vGPIO_PCIE_14", + "GPP_vGPIO_PCIE_15", "GPP_vGPIO_PCIE_15", + "GPP_vGPIO_PCIE_16", "GPP_vGPIO_PCIE_16", + "GPP_vGPIO_PCIE_17", "GPP_vGPIO_PCIE_17", + "GPP_vGPIO_PCIE_18", "GPP_vGPIO_PCIE_18", + "GPP_vGPIO_PCIE_19", "GPP_vGPIO_PCIE_19", + "GPP_vGPIO_PCIE_20", "GPP_vGPIO_PCIE_20", + "GPP_vGPIO_PCIE_21", "GPP_vGPIO_PCIE_21", + "GPP_vGPIO_PCIE_22", "GPP_vGPIO_PCIE_22", + "GPP_vGPIO_PCIE_23", "GPP_vGPIO_PCIE_23", + "GPP_vGPIO_PCIE_24", "GPP_vGPIO_PCIE_24", + "GPP_vGPIO_PCIE_25", "GPP_vGPIO_PCIE_25", + "GPP_vGPIO_PCIE_26", "GPP_vGPIO_PCIE_26", + "GPP_vGPIO_PCIE_27", "GPP_vGPIO_PCIE_27", + "GPP_vGPIO_PCIE_28", "GPP_vGPIO_PCIE_28", + "GPP_vGPIO_PCIE_29", "GPP_vGPIO_PCIE_29", + "GPP_vGPIO_PCIE_30", "GPP_vGPIO_PCIE_30", + "GPP_vGPIO_PCIE_31", "GPP_vGPIO_PCIE_31", + "GPP_vGPIO_PCIE_32", "GPP_vGPIO_PCIE_32", + "GPP_vGPIO_PCIE_33", "GPP_vGPIO_PCIE_33", + "GPP_vGPIO_PCIE_34", "GPP_vGPIO_PCIE_34", + "GPP_vGPIO_PCIE_35", "GPP_vGPIO_PCIE_35", + "GPP_vGPIO_PCIE_36", "GPP_vGPIO_PCIE_36", + "GPP_vGPIO_PCIE_37", "GPP_vGPIO_PCIE_37", + "GPP_vGPIO_PCIE_38", "GPP_vGPIO_PCIE_38", + "GPP_vGPIO_PCIE_39", "GPP_vGPIO_PCIE_39", + "GPP_vGPIO_PCIE_40", "GPP_vGPIO_PCIE_40", + "GPP_vGPIO_PCIE_41", "GPP_vGPIO_PCIE_41", + "GPP_vGPIO_PCIE_42", "GPP_vGPIO_PCIE_42", + "GPP_vGPIO_PCIE_43", "GPP_vGPIO_PCIE_43", + "GPP_vGPIO_PCIE_44", "GPP_vGPIO_PCIE_44", + "GPP_vGPIO_PCIE_45", "GPP_vGPIO_PCIE_45", + "GPP_vGPIO_PCIE_46", "GPP_vGPIO_PCIE_46", + "GPP_vGPIO_PCIE_47", "GPP_vGPIO_PCIE_47", + "GPP_vGPIO_PCIE_48", "GPP_vGPIO_PCIE_48", + "GPP_vGPIO_PCIE_49", "GPP_vGPIO_PCIE_49", + "GPP_vGPIO_PCIE_50", "GPP_vGPIO_PCIE_50", + "GPP_vGPIO_PCIE_51", "GPP_vGPIO_PCIE_51", + "GPP_vGPIO_PCIE_52", "GPP_vGPIO_PCIE_52", + "GPP_vGPIO_PCIE_53", "GPP_vGPIO_PCIE_53", + "GPP_vGPIO_PCIE_54", "GPP_vGPIO_PCIE_54", + "GPP_vGPIO_PCIE_55", "GPP_vGPIO_PCIE_55", + "GPP_vGPIO_PCIE_56", "GPP_vGPIO_PCIE_56", + "GPP_vGPIO_PCIE_57", "GPP_vGPIO_PCIE_57", + "GPP_vGPIO_PCIE_58", "GPP_vGPIO_PCIE_58", + "GPP_vGPIO_PCIE_59", "GPP_vGPIO_PCIE_59", + "GPP_vGPIO_PCIE_60", "GPP_vGPIO_PCIE_60", + "GPP_vGPIO_PCIE_61", "GPP_vGPIO_PCIE_61", + "GPP_vGPIO_PCIE_62", "GPP_vGPIO_PCIE_62", + "GPP_vGPIO_PCIE_63", "GPP_vGPIO_PCIE_63", + "GPP_vGPIO_PCIE_64", "GPP_vGPIO_PCIE_64", + "GPP_vGPIO_PCIE_65", "GPP_vGPIO_PCIE_65", + "GPP_vGPIO_PCIE_66", "GPP_vGPIO_PCIE_66", + "GPP_vGPIO_PCIE_67", "GPP_vGPIO_PCIE_67", + "GPP_vGPIO_PCIE_68", "GPP_vGPIO_PCIE_68", + "GPP_vGPIO_PCIE_69", "GPP_vGPIO_PCIE_69", + "GPP_vGPIO_PCIE_70", "GPP_vGPIO_PCIE_70", + "GPP_vGPIO_PCIE_71", "GPP_vGPIO_PCIE_71", + "GPP_vGPIO_PCIE_72", "GPP_vGPIO_PCIE_72", + "GPP_vGPIO_PCIE_73", "GPP_vGPIO_PCIE_73", + "GPP_vGPIO_PCIE_74", "GPP_vGPIO_PCIE_74", + "GPP_vGPIO_PCIE_75", "GPP_vGPIO_PCIE_75", + "GPP_vGPIO_PCIE_76", "GPP_vGPIO_PCIE_76", + "GPP_vGPIO_PCIE_77", "GPP_vGPIO_PCIE_77", + "GPP_vGPIO_PCIE_78", "GPP_vGPIO_PCIE_78", + "GPP_vGPIO_PCIE_79", "GPP_vGPIO_PCIE_79", + "GPP_CPU_RSVD_40", "GPP_CPU_RSVD_40", + "GPP_CPU_RSVD_41", "GPP_CPU_RSVD_41", + "GPP_CPU_RSVD_42", "GPP_CPU_RSVD_42", + "GPP_CPU_RSVD_43", "GPP_CPU_RSVD_43", + "GPP_CPU_RSVD_44", "GPP_CPU_RSVD_44", + "GPP_CPU_RSVD_45", "GPP_CPU_RSVD_45", + "GPP_CPU_RSVD_46", "GPP_CPU_RSVD_46", + "GPP_CPU_RSVD_47", "GPP_CPU_RSVD_47", + "GPP_vGPIO_PCIE_80", "GPP_vGPIO_PCIE_80", + "GPP_vGPIO_PCIE_81", "GPP_vGPIO_PCIE_81", + "GPP_vGPIO_PCIE_82", "GPP_vGPIO_PCIE_82", + "GPP_vGPIO_PCIE_83", "GPP_vGPIO_PCIE_83", +}; + +const struct gpio_group alderlake_pch_p_group_pcie_vgpio = { + .display = "------- GPIO Group PCIe vGPIO -------", + .pad_count = ARRAY_SIZE(alderlake_pch_p_group_pcie_vgpio_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_p_group_pcie_vgpio_names, +}; + +const struct gpio_group *const alderlake_pch_p_community_0_groups[] = { + &alderlake_pch_p_group_b, + &alderlake_pch_p_group_t, + &alderlake_pch_p_group_a, +}; + +const struct gpio_community alderlake_pch_p_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(alderlake_pch_p_community_0_groups), + .groups = alderlake_pch_p_community_0_groups, +}; + +const struct gpio_group *const alderlake_pch_p_community_1_groups[] = { + &alderlake_pch_p_group_s, + &alderlake_pch_p_group_h, + &alderlake_pch_p_group_d, + &alderlake_pch_p_group_reserved, + &alderlake_pch_p_group_vgpio, +}; + +const struct gpio_community alderlake_pch_p_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(alderlake_pch_p_community_1_groups), + .groups = alderlake_pch_p_community_1_groups, +}; + +const struct gpio_group *const alderlake_pch_p_community_2_groups[] = { + &alderlake_pch_p_group_gpd, + &alderlake_pch_p_group_pcie_vgpio, +}; + +const struct gpio_community alderlake_pch_p_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(alderlake_pch_p_community_2_groups), + .groups = alderlake_pch_p_community_2_groups, +}; + +const struct gpio_group *const alderlake_pch_p_community_4_groups[] = { + &alderlake_pch_p_group_c, + &alderlake_pch_p_group_f, + &alderlake_pch_p_group_hvcmos, + &alderlake_pch_p_group_e, +}; + +const struct gpio_community alderlake_pch_p_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(alderlake_pch_p_community_4_groups), + .groups = alderlake_pch_p_community_4_groups, +}; + +const struct gpio_group *const alderlake_pch_p_community_5_groups[] = { + &alderlake_pch_p_group_r, +}; + +const struct gpio_community alderlake_pch_p_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(alderlake_pch_p_community_5_groups), + .groups = alderlake_pch_p_community_5_groups, +}; + +const struct gpio_community *const alderlake_pch_p_communities[] = { + &alderlake_pch_p_community_0, + &alderlake_pch_p_community_1, + &alderlake_pch_p_community_2, + &alderlake_pch_p_community_4, + &alderlake_pch_p_community_5, +}; + +#endif diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 25149a5..2c2b950 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -170,6 +170,13 @@ "12th generation (Alder Lake S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_0, "12th generation (Alder Lake S family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8, + "12th generation (Alder Lake P family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8, + "12th generation (Alder Lake P family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8, + "12th generation (Alder Lake P family) Core Processor"}, + /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 8759c6c..3b43b398 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -287,6 +287,10 @@ #define PCI_DEVICE_ID_INTEL_I5000V 0x25d4 #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 +#define PCI_DEVICE_ID_INTEL_ADL_P 0x5182 +#define PCI_DEVICE_ID_INTEL_ADL_M 0x5187 +#define PCI_DEVICE_ID_INTEL_RPL_P 0x519d + /* untested, but almost identical to D-series */ #define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 @@ -357,7 +361,9 @@ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_8_8 0x4637 /* Alderlake HX 8+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_6_8 0x463B /* Alderlake HX 6+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_4_8 0x4623 /* Alderlake HX 4+8 */ - +#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8 0x4641 /* Alderlake P 6+8 */ +#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8 0x4621 /* Alderlake P 4+8 */ +#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8 0x4601 /* Alderlake P 2+8 */ /* Intel GPUs */ #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 672eb98..4e3f41c 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -150,6 +150,9 @@ case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: + case PCI_DEVICE_ID_INTEL_ADL_P: + case PCI_DEVICE_ID_INTEL_ADL_M: + case PCI_DEVICE_ID_INTEL_RPL_P: sbbar_phys = 0xfd000000; use_p2sb = false; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/66825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Gerrit-Change-Number: 66825 Gerrit-PatchSet: 17 Gerrit-Owner: Kacper Stojek Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68098 ) Change subject: mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz ...................................................................... mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHz Change the TPM I2C freqeuncy to 1 MHz for pujjo. BUG=b:249953707 TEST=On pujjo, all timing requirements in the spec are met. Frequencies: pujjo - 987.80 kHz Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/brya/variants/pujjo/overridetree.cb 1 file changed, 24 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index a043b46..d7d36e1 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -126,11 +126,11 @@ register "common_soc_config" = "{ .i2c[0] = { .early_init = 1, - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST_PLUS, .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 160, - .scl_hcnt = 79, + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, .sda_hold = 7, } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/68098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Gerrit-Change-Number: 68098 Gerrit-PatchSet: 4 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Leanne1 Chen <leanne1.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/nissa/var/yaviks: Config I2C frequency
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68082 ) Change subject: mb/google/nissa/var/yaviks: Config I2C frequency ...................................................................... mb/google/nissa/var/yaviks: Config I2C frequency Update parameters for all I2C devices. After applied this patch, the measured the I2C frequency meets spec BUG=b:249953708 TEST=FW_NAME=yaviks emerge-nissa coreboot flash and measure the all I2C devices 1. I2C0 (TPM): 980.6 Khz 2. I2C1 (TouchScreen); 392.6 Khz 3. I2C3 （Audio): 394.9 Khz 4. I2C5 (Touchpad): 391.6 Khz Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68082 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/brya/variants/yaviks/overridetree.cb 1 file changed, 49 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb index e30cc06..bfee360 100644 --- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb @@ -40,16 +40,40 @@ register "common_soc_config" = "{ .i2c[0] = { .early_init = 1, - .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 56, + .scl_hcnt = 30, + .sda_hold = 7, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/68082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7 Gerrit-Change-Number: 68082 Gerrit-PatchSet: 7 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68126 ) Change subject: soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region ...................................................................... soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was selected, but needs to be added in the RW_A only case as well (VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A, we can guard amdfw_a and _b separately and both will be added in the RW_AB case. TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions as appropriate. Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68126 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 6 files changed, 50 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 43c83bf..35b9215 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -484,7 +484,7 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY string @@ -493,6 +493,10 @@ Add a space-delimited list of filenames that should only be in the RW-A section. +endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + config RWB_REGION_ONLY string default "apu/amdfw_b" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 205b349..dc97c1f 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -280,13 +280,15 @@ apu/amdfw-position := $(CEZANNE_FWM_POSITION) apu/amdfw-type := raw -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom # Ensure this ends up at the beginning of the FW_MAIN_A fmap region apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw +endif +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom # Ensure this ends up at the beginning of the FW_MAIN_B fmap region diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d7c5372..9608e41 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -506,7 +506,7 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY string @@ -515,6 +515,10 @@ Add a space-delimited list of filenames that should only be in the RW-A section. +endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + config RWB_REGION_ONLY string default "apu/amdfw_b" diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index f8aa96f..9549426 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -302,18 +302,21 @@ apu/amdfw-position := $(MENDOCINO_FWM_POSITION) apu/amdfw-type := raw -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw +endif +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw +endif -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom @printf " Adding Signed ROM and HASH\n" $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed @@ -322,7 +325,6 @@ -n apu/amdfw_a_hash -t raw $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ -n apu/amdfw_b_hash -t raw -endif # CONFIG_SEPARATE_SIGNED_PSPFW endif endif # ($(CONFIG_SOC_AMD_MENDOCINO),y) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6b8b910..f3b982d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -500,7 +500,7 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) -if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK +if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY string @@ -509,6 +509,10 @@ Add a space-delimited list of filenames that should only be in the RW-A section. +endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + config RWB_REGION_ONLY string default "apu/amdfw_b" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d909b2c..3e43a3d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -292,12 +292,14 @@ apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw +endif +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -- To view, visit https://review.coreboot.org/c/coreboot/+/68126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Gerrit-Change-Number: 68126 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68125 ) Change subject: soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw ...................................................................... soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw apu/amdfw should be restricted to the RO region only when building with VBOOT + any RW region (RW_A or RW_A + RW_B); it is not tied to ChromeOS in any way. Fix guarding to match newer AMD platforms (eg, CZN/MDN). TEST=build google/zork without CHROMEOS, with VBOOT_SLOTS_RW_A Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68125 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig 2 files changed, 22 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 30ca132..6b8b910 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -330,7 +330,7 @@ config RO_REGION_ONLY string - depends on CHROMEOS + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2517e44..26dca89 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -357,7 +357,7 @@ config RO_REGION_ONLY string - depends on CHROMEOS + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ -- To view, visit https://review.coreboot.org/c/coreboot/+/68125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Gerrit-Change-Number: 68125 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: MAINTAINERS: Update maintainers for several Google projects
by Martin Roth (Code Review) 07 Oct '22

07 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67289 ) Change subject: MAINTAINERS: Update maintainers for several Google projects ...................................................................... MAINTAINERS: Update maintainers for several Google projects Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: I973b0abf8a82189df1495e3bcd9bae452a5be827 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67289 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> --- M MAINTAINERS 1 file changed, 21 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 0433602..d753c3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -271,10 +271,12 @@ F: src/mainboard/google/rex/ GOOGLE BRYA MAINBOARDS +M: Tarun Tuli <taruntuli(a)google.com> S: Maintained F: src/mainboard/google/brya/ GOOGLE HATCH MAINBOARDS +M: Tarun Tuli <taruntuli(a)google.com> S: Maintained F: src/mainboard/google/hatch/ @@ -562,6 +564,8 @@ ################################################################################ CHROME EC +M: Boris Mittelberg <bmbm(a)google.com> +M: Caveh Jalali <caveh(a)chromium.org> S: Maintained F: src/ec/google/chromeec/ @@ -702,6 +706,8 @@ F: src/soc/intel/meteorlake/ INTEL ALDERLAKE SOC +M: Subrata Banik <subratabanik(a)google.com> +M: Tarun Tuli <taruntuli(a)google.com> S: Maintained F: src/soc/intel/alderlake/ @@ -733,6 +739,8 @@ F: src/soc/intel/elkhartlake/ INTEL TIGERLAKE SOC +M: Subrata Banik <subratabanik(a)google.com> +M: Tarun Tuli <taruntuli(a)google.com> S: Maintained F: src/soc/intel/tigerlake/ -- To view, visit https://review.coreboot.org/c/coreboot/+/67289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973b0abf8a82189df1495e3bcd9bae452a5be827 Gerrit-Change-Number: 67289 Gerrit-PatchSet: 6 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Noga Smith <nogasmith(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/alderlake: Support Raptor Lake VR Fast VMODE
by 9elements QA (Code Review) 07 Oct '22

07 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66917 ) Change subject: soc/intel/alderlake: Support Raptor Lake VR Fast VMODE ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/126559 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/126558 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/126557 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/126556 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/126555 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/126554 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/126553 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/126552 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/126551 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/126550 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/126549 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/126548 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/126547 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/126546 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/126545 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/126544 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/66917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Gerrit-Change-Number: 66917 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 07 Oct 2022 21:01:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Support Raptor Lake VR Fast VMODE
by Angel Pons (Code Review) 07 Oct '22

07 Oct '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66917 ) Change subject: soc/intel/alderlake: Support Raptor Lake VR Fast VMODE ...................................................................... soc/intel/alderlake: Support Raptor Lake VR Fast VMODE RaptorLake introduces the support of the Voltage Regulator Fast Vmode feature. When enabled, it makes the SoC throttle when the current exceeds the I_TRIP threshold. This threshold should be between Iccmax.app and Iccmax and take into account the specification of the Voltage Regulator of the system. This change provides a mean to: 1. Enable the feature via the `vr_config->enable_fast_vmode'. If no I_TRIP value is supplied FSPs picks an adapted I_TRIP value for the current SoC assuming a Voltage Regulator error accuracy of 6.5%. 2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip' field. These new fields are considered independent from the other `vr_config' fields so that the board configuration does not have to unnecessarily supply other VR settings to enable Fast VMode. Information about the Fast VMode Feature can be found in the following Intel documents: - 627270 ADL and RPL Processor Family Core and Uncore BIOS Specification - 724220 RaptorLake Platform Fast V-Mode - 686872 RaptorLake Lake U P H Platform BUG=b:243120082 BRANCH=firmware-brya-14505.B TEST=Read I_TRIP from the Pcode and verify consistency with a few `enable_fast_vmode' and `fast_vmode_i_trip' settings. Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/include/soc/vr_config.h M src/soc/intel/alderlake/vr_config.c 2 files changed, 75 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/include/soc/vr_config.h b/src/soc/intel/alderlake/include/soc/vr_config.h index 316abc0..41c2f6b 100644 --- a/src/soc/intel/alderlake/include/soc/vr_config.h +++ b/src/soc/intel/alderlake/include/soc/vr_config.h @@ -8,6 +8,25 @@ #include <fsp/api.h> struct vr_config { +#if CONFIG(SOC_INTEL_RAPTORLAKE) + /* + * When enabled, this feature makes the SoC throttle when the power + * consumption exceeds the I_TRIP threshold. + * + * FSPs sets a by default I_TRIP threshold adapted to the current SoC + * and assuming a Voltage Regulator error accuracy of 6.5%. + */ + bool enable_fast_vmode; + + /* + * VR Fast Vmode I_TRIP threshold. + * 0-255A in 1/4 A units. Example: 400 = 100A + + * This setting overrides the default value set by FSPs when Fast VMode + * is enabled. + */ + uint16_t fast_vmode_i_trip; +#endif /* The below settings will take effect when this is set to 1 for that domain. */ bool vr_config_enable; diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 159f451..4d649fb 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -254,6 +254,16 @@ { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 30) }, }; +static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, + int domain, const struct vr_config *chip_cfg) +{ +#if CONFIG(SOC_INTEL_RAPTORLAKE) + s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode; + if (s_cfg->EnableFastVmode[domain]) + s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip; +#endif +} + void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, int domain, const struct vr_config *chip_cfg) { @@ -299,6 +309,8 @@ domain, mch_id, tdp); } + fill_vr_fast_vmode(s_cfg, domain, chip_cfg); + /* Check TdcTimeWindow and TdcCurrentLimit, Set TdcEnable and Set VR TDC Input current to root mean square */ if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/66917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Gerrit-Change-Number: 66917 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/alderlake: Support Raptor Lake VR Fast VMODE
by Angel Pons (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Anil Kumar K, Tarun Tuli, Cliff Huang, Subrata Banik, Jérémy Compostella, Selma Bensaid, Paul Menzel, Tim Wawrzynczak, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66917 ) Change subject: soc/intel/alderlake: Support Raptor Lake VR Fast VMODE ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > Is there anything holding this patch back that I missed ? Oh, let's submit it -- To view, visit https://review.coreboot.org/c/coreboot/+/66917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Gerrit-Change-Number: 66917 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 Oct 2022 20:30:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Raul Rangel (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Dmitry Torokhov, Tim Wawrzynczak, Paul Menzel, Tim Van Patten, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Is this ready to land now? There's a merge conflict and I haven't had a chance to fix it :/ -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 20:25:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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