coreboot-gerrit January 2022

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 9: (2 comments) File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/8beb66ba_663b711c PS8, Line 221: printk(BIOS_NOTICE, "PSB is not Enabled.\n"); > would "Enabling PSB failed. […] Ack File src/soc/amd/common/block/psp/psp_def.h: https://review.coreboot.org/c/coreboot/+/60968/comment/dc3e0c89_b74fec59 PS8, Line 25: #define MBOX_BIOS_CMD_PSB_AUTO_FUSING 0x21 > this needs to be moved up above line 20, since this isn't a v1 psp mailbox command Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 9 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Jan 2022 14:42:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Aamir Bohra, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60968 to look at the new patch set (#9). Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... soc/amd/common/block/psp: Add platform secure boot support Add Platform Secure Boot (PSB) enablement via the PSP if it is not already enabled. Upon receiving psb command, PSP will program PSB fuses as long as BIOS signing key token is valid. Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.inc A src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 5 files changed, 241 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60968/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 9 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/3a6d6281_b88c76ea PS2, Line 666: is_cse_fw_update_enabled > > >is there any restriction that on after FSI, we can't read the softstrap ? […] >So, if I read it correctly there is no restriction while reading OEM sections prior or post FSI. hence, why we would like to introduce a Kconfig to guard the read operation which would eventually get drop during FSI. Any owner for ensuring the same across program ? I don't see any benefit running this code since it is not useful once RO is locked. Hence, I want to guard the code and remove it before FSI. >I could sense there are some underlying assumption which is not documented anything, either please raise a bug or write a .md file to clear out those assumptions. There are no assumptions or hidden things in this regard, I will update commit message with more information. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 14:26:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Remove `mb_gpio_lock_config()` override function
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61503 ) Change subject: mb/google/brya: Remove `mb_gpio_lock_config()` override function ...................................................................... mb/google/brya: Remove `mb_gpio_lock_config()` override function This patch removes `lockable_brya_gpios` lists and `mb_gpio_lock_config` override function from brya baseboard directory as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to built and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/61503/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 14a12e2..8f3d0f0 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -456,12 +456,3 @@ *num = 0; return NULL; } - -static struct gpio_lock_config lockable_brya_gpios[] = { -}; - -const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) -{ - *num = ARRAY_SIZE(lockable_brya_gpios); - return lockable_brya_gpios; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/61503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Gerrit-Change-Number: 61503 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock `FPMCU_*` GPIO PADs
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61502 ) Change subject: mb/google/brya: Allow mainboard to lock `FPMCU_*` GPIO PADs ...................................................................... mb/google/brya: Allow mainboard to lock `FPMCU_*` GPIO PADs BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests `FPMCU_*` (F11-F13 and F15-F16) are locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5 --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 2 files changed, 10 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/61502/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 203f6d9..5383aa7 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -230,17 +230,17 @@ /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), /* F14 : GSXDIN ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index e72d0af..14a12e2 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -234,17 +234,17 @@ /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ @@ -458,11 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ - { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ - { GPP_F12, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D0_FPMCU_D1_R */ - { GPP_F15, GPIO_LOCK_CONFIG }, /* FPMCU_INT_L */ - { GPP_F16, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CS_FPMCU_R_L */ }; const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/61502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5 Gerrit-Change-Number: 61502 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61501 ) Change subject: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs ...................................................................... mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests PCH_WP_OD is locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e --- M src/mainboard/google/brya/variants/agah/gpio.c M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/anahera4es/gpio.c M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya4es/gpio.c M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/gimble/gpio.c M src/mainboard/google/brya/variants/gimble4es/gpio.c M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix4es/gpio.c M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/brya/variants/taeko4es/gpio.c M src/mainboard/google/brya/variants/taniks/gpio.c M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/volmar/gpio.c 21 files changed, 39 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/61501/1 diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 9b8574d..ade9ca9 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -91,6 +91,8 @@ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */ PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */ diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 2d89712..1e7813b 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -59,6 +59,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c index 6c2990c..c08b863 100644 --- a/src/mainboard/google/brya/variants/anahera4es/gpio.c +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -63,6 +63,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index bdf3815..1306cf7 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -143,6 +143,7 @@ PAD_NC(GPP_E13, NONE), /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 22b2c70..203f6d9 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -189,7 +189,7 @@ /* E14 : DDSP_HPDA ==> SOC_DP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> CLKREQ_8 */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> TP102 */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 269e8b9..e72d0af 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -188,7 +188,7 @@ /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ @@ -458,7 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ { GPP_F12, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D0_FPMCU_D1_R */ diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index 78cc853..9e495cb 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -23,6 +23,8 @@ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ PAD_CFG_GPI(GPP_F19, UP_20K, DEEP), /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ diff --git a/src/mainboard/google/brya/variants/brya4es/gpio.c b/src/mainboard/google/brya/variants/brya4es/gpio.c index 78cc853..9e495cb 100644 --- a/src/mainboard/google/brya/variants/brya4es/gpio.c +++ b/src/mainboard/google/brya/variants/brya4es/gpio.c @@ -23,6 +23,8 @@ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ PAD_CFG_GPI(GPP_F19, UP_20K, DEEP), /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 5a57941..ae12d29 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -49,6 +49,8 @@ PAD_NC(GPP_E9, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index db3f7a0..b65053d 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -63,6 +63,8 @@ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c index 14bc922..4b7bdd4 100644 --- a/src/mainboard/google/brya/variants/gimble4es/gpio.c +++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c @@ -67,6 +67,8 @@ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index cd5aa26..9feb99a 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -53,6 +53,8 @@ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E17 : THC0_SPI1_INT# ==> NC */ PAD_NC(GPP_E17, NONE), /* E22 : DDPA_CTRLCLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index 4d8f520..1565665 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -51,6 +51,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE), diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index b49c3fe..c873a7f 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -55,6 +55,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE), diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index 918f9cf..4d76488 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -39,6 +39,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : DDP2_CTRLCLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/redrix4es/gpio.c b/src/mainboard/google/brya/variants/redrix4es/gpio.c index b360672..2523dc2 100644 --- a/src/mainboard/google/brya/variants/redrix4es/gpio.c +++ b/src/mainboard/google/brya/variants/redrix4es/gpio.c @@ -43,6 +43,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : DDP2_CTRLCLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index 0e15b5e..caff7d9 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -73,6 +73,8 @@ PAD_NC(GPP_E5, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c index acd0698..3ac396d 100644 --- a/src/mainboard/google/brya/variants/taeko4es/gpio.c +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -77,6 +77,8 @@ PAD_NC(GPP_E5, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ diff --git a/src/mainboard/google/brya/variants/taniks/gpio.c b/src/mainboard/google/brya/variants/taniks/gpio.c index 00f8049..b0d5bfe 100644 --- a/src/mainboard/google/brya/variants/taniks/gpio.c +++ b/src/mainboard/google/brya/variants/taniks/gpio.c @@ -81,6 +81,8 @@ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index d26310b..16532d5 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -41,6 +41,8 @@ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */ PAD_CFG_GPI(GPP_E22, NONE, DEEP), /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */ diff --git a/src/mainboard/google/brya/variants/volmar/gpio.c b/src/mainboard/google/brya/variants/volmar/gpio.c index a3cfc90..658aaec 100644 --- a/src/mainboard/google/brya/variants/volmar/gpio.c +++ b/src/mainboard/google/brya/variants/volmar/gpio.c @@ -60,6 +60,8 @@ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E17 : THC0_SPI1_INT# ==> NC */ PAD_NC(GPP_E17, NONE), /* E18 : DDP1_CTRLCLK ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e Gerrit-Change-Number: 61501 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61500 ) Change subject: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs ...................................................................... mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests GSC_PCH_INT_ODL is locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62 --- M src/mainboard/google/brya/variants/agah/gpio.c M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/anahera4es/gpio.c M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya4es/gpio.c M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/gimble/gpio.c M src/mainboard/google/brya/variants/gimble4es/gpio.c M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix4es/gpio.c M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/brya/variants/taeko4es/gpio.c M src/mainboard/google/brya/variants/taniks/gpio.c M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/volmar/gpio.c 21 files changed, 39 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/61500/1 diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 25c20f3..9b8574d 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -13,6 +13,8 @@ PAD_CFG_GPO(GPP_A8, 1, DEEP), /* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */ PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index ab3ea66..2d89712 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -9,6 +9,8 @@ static const struct pad_config override_gpio_table[] = { /* A7 : SRCCLK_OE7# ==> NC */ PAD_NC(GPP_A7, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A17 : DISP_MISCC ==> NC */ PAD_NC(GPP_A17, NONE), /* A19 : DDSP_HPD1 ==> NC */ diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c index e7ded60..6c2990c 100644 --- a/src/mainboard/google/brya/variants/anahera4es/gpio.c +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -9,6 +9,8 @@ static const struct pad_config override_gpio_table[] = { /* A7 : SRCCLK_OE7# ==> NC */ PAD_NC(GPP_A7, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A17 : DISP_MISCC ==> NC */ PAD_NC(GPP_A17, NONE), /* A19 : DDSP_HPD1 ==> NC */ diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 8ea51d8..bdf3815 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -25,6 +25,7 @@ /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ /* A12 : SATAXPCIE1 ==> EN_PP3300_SSD */ /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ /* A16 : USB_OC3# ==> USB_C3_OC_ODL */ diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 40d73eb..22b2c70 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -29,7 +29,7 @@ /* A12 : SATAXPCIE1 ==> CLKREQ_9B */ PAD_NC(GPP_A12, NONE), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 9938564..269e8b9 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -29,7 +29,7 @@ /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ @@ -458,7 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_A13, GPIO_LOCK_CONFIG }, /* GSC_PCH_INT_ODL */ { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index 4cf99df..78cc853 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -5,6 +5,8 @@ #include <soc/gpio.h> static const struct pad_config board_id0_1_overrides[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ diff --git a/src/mainboard/google/brya/variants/brya4es/gpio.c b/src/mainboard/google/brya/variants/brya4es/gpio.c index 4cf99df..78cc853 100644 --- a/src/mainboard/google/brya/variants/brya4es/gpio.c +++ b/src/mainboard/google/brya/variants/brya4es/gpio.c @@ -5,6 +5,8 @@ #include <soc/gpio.h> static const struct pad_config board_id0_1_overrides[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 186c045..5a57941 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -11,6 +11,8 @@ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, NONE, DEEP), /* A8 : SRCCLKREQ7# ==> PEN_DET_ODL */ PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), /* B5 : ISH_I2C0_SDA ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index fc43e94..db3f7a0 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -15,6 +15,8 @@ PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> NC */ PAD_NC(GPP_A12, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c index 5606733..14bc922 100644 --- a/src/mainboard/google/brya/variants/gimble4es/gpio.c +++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c @@ -15,6 +15,8 @@ PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> NC */ PAD_NC(GPP_A12, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 57975f7..cd5aa26 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -15,6 +15,8 @@ PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> NC */ PAD_NC(GPP_A12, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A15 : USB_OC2# ==> NC */ PAD_NC(GPP_A15, NONE), /* A19 : DDSP_HPD1 ==> NC */ diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index 36766f4..4d8f520 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -11,6 +11,8 @@ PAD_NC(GPP_A6, NONE), /* A7 : SRCCLK_OE7# ==> NC */ PAD_NC(GPP_A7, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index 42d2bcb..b49c3fe 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -11,6 +11,8 @@ PAD_NC(GPP_A6, NONE), /* A7 : SRCCLK_OE7# ==> NC */ PAD_NC(GPP_A7, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index 854b6ca..918f9cf 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A17 : DISP_MISCC ==> NC */ PAD_NC(GPP_A17, NONE), /* A19 : DDSP_HPD1 ==> NC */ diff --git a/src/mainboard/google/brya/variants/redrix4es/gpio.c b/src/mainboard/google/brya/variants/redrix4es/gpio.c index a04ebaf..b360672 100644 --- a/src/mainboard/google/brya/variants/redrix4es/gpio.c +++ b/src/mainboard/google/brya/variants/redrix4es/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A17 : DISP_MISCC ==> NC */ PAD_NC(GPP_A17, NONE), /* A19 : DDSP_HPD1 ==> NC */ diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index a97aef8..0e15b5e 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -15,6 +15,8 @@ PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> NC */ PAD_NC(GPP_A12, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c index 7105c09..acd0698 100644 --- a/src/mainboard/google/brya/variants/taeko4es/gpio.c +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -15,6 +15,8 @@ PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> NC */ PAD_NC(GPP_A12, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/taniks/gpio.c b/src/mainboard/google/brya/variants/taniks/gpio.c index 05a68d1..00f8049 100644 --- a/src/mainboard/google/brya/variants/taniks/gpio.c +++ b/src/mainboard/google/brya/variants/taniks/gpio.c @@ -15,6 +15,8 @@ PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> NC */ PAD_NC(GPP_A12, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index 6dbfb69..d26310b 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -9,6 +9,8 @@ static const struct pad_config override_gpio_table[] = { /* A11 : PMC_I2C_SDA ==> NC */ PAD_NC(GPP_A11, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* B2 : VRALERT# ==> RGB_RST_ODL */ PAD_CFG_GPO(GPP_B2, 1, DEEP), diff --git a/src/mainboard/google/brya/variants/volmar/gpio.c b/src/mainboard/google/brya/variants/volmar/gpio.c index 3f3a181..a3cfc90 100644 --- a/src/mainboard/google/brya/variants/volmar/gpio.c +++ b/src/mainboard/google/brya/variants/volmar/gpio.c @@ -15,6 +15,8 @@ PAD_NC(GPP_A8, NONE), /* A12 : SATAXPCIE1 ==> NC */ PAD_NC(GPP_A12, NONE), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A15 : USB_OC2# ==> NC */ PAD_NC(GPP_A15, NONE), /* A19 : DDSP_HPD1 ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62 Gerrit-Change-Number: 61500 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61499 ) Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs ...................................................................... mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d --- M src/mainboard/google/brya/variants/agah/gpio.c M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/anahera4es/gpio.c M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya4es/gpio.c M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/gimble/gpio.c M src/mainboard/google/brya/variants/gimble4es/gpio.c M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix4es/gpio.c M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/brya/variants/taeko4es/gpio.c M src/mainboard/google/brya/variants/taniks/gpio.c M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/volmar/gpio.c 21 files changed, 80 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/61499/1 diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index fbb9f0f..25c20f3 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -34,6 +34,10 @@ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), /* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 1d15a08..ab3ea66 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -70,6 +70,10 @@ /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), + /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H20 : IMGCLKOUT1 ==> NC */ PAD_NC(GPP_H20, NONE), /* H21 : IMGCLKOUT2 ==> Privacy screen */ diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c index 40dd56f..e7ded60 100644 --- a/src/mainboard/google/brya/variants/anahera4es/gpio.c +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -26,6 +26,10 @@ PAD_NC(GPP_B5, NONE), /* B6 : ISH_I2C0_SCL ==> NC */ PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 8757e40..8ea51d8 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -51,8 +51,6 @@ PAD_NC(GPP_B5, NONE), /* B6 : ISH_I2C0_SCL ==> NC */ PAD_NC(GPP_B6, NONE), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ /* B9 : NC */ /* B10 : NC */ /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ @@ -197,8 +195,10 @@ /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ - /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ - /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 268cddc..40d73eb 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -269,9 +269,9 @@ /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 0583930..9938564 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -66,9 +66,9 @@ /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B9 : NC */ PAD_NC(GPP_B9, NONE), /* B10 : NC */ @@ -458,8 +458,6 @@ } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_B6, GPIO_LOCK_CONFIG }, /* PCH_I2C_TPM_SCL */ - { GPP_B7, GPIO_LOCK_CONFIG }, /* PCH_I2C_TPM_SDA */ { GPP_A13, GPIO_LOCK_CONFIG }, /* GSC_PCH_INT_ODL */ { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index f6171a6..4cf99df 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -7,6 +7,10 @@ static const struct pad_config board_id0_1_overrides[] = { /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), /* C3 : SML0CLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/brya4es/gpio.c b/src/mainboard/google/brya/variants/brya4es/gpio.c index f6171a6..4cf99df 100644 --- a/src/mainboard/google/brya/variants/brya4es/gpio.c +++ b/src/mainboard/google/brya/variants/brya4es/gpio.c @@ -7,6 +7,10 @@ static const struct pad_config board_id0_1_overrides[] = { /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), /* C3 : SML0CLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 3f09d5b..186c045 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -73,6 +73,10 @@ PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index c0749c3..fc43e94 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -79,6 +79,10 @@ /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA_P2 */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL_P2 */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c index 685b37a..5606733 100644 --- a/src/mainboard/google/brya/variants/gimble4es/gpio.c +++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c @@ -32,6 +32,10 @@ PAD_NC(GPP_B5, NONE), /* B6 : ISH_I2C0_SCL ==> NC */ PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 6f74e25..57975f7 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -63,6 +63,10 @@ /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index e30163c..36766f4 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -57,6 +57,10 @@ /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H19 : SRCCLKREQ4# ==> NC */ PAD_NC(GPP_H19, NONE), /* H21 : IMGCLKOUT2 ==> NC */ diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index f0d1c5d..42d2bcb 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -24,6 +24,10 @@ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index f9fd731..854b6ca 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -50,6 +50,10 @@ /* H3 : SX_EXIT_HOLDOFF# ==> NC */ PAD_NC(GPP_H3, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H20 : IMGCLKOUT1 ==> NC */ PAD_NC(GPP_H20, NONE), /* H21 : IMGCLKOUT2 ==> Privacy screen */ diff --git a/src/mainboard/google/brya/variants/redrix4es/gpio.c b/src/mainboard/google/brya/variants/redrix4es/gpio.c index afcb7e9..a04ebaf 100644 --- a/src/mainboard/google/brya/variants/redrix4es/gpio.c +++ b/src/mainboard/google/brya/variants/redrix4es/gpio.c @@ -20,6 +20,10 @@ /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index 4d93e54..a97aef8 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -97,6 +97,10 @@ /* F23 : BP105_CTRL ==> PP1050_CTRL */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c index 5d8badf..7105c09 100644 --- a/src/mainboard/google/brya/variants/taeko4es/gpio.c +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -34,6 +34,10 @@ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), diff --git a/src/mainboard/google/brya/variants/taniks/gpio.c b/src/mainboard/google/brya/variants/taniks/gpio.c index 41f080b..05a68d1 100644 --- a/src/mainboard/google/brya/variants/taniks/gpio.c +++ b/src/mainboard/google/brya/variants/taniks/gpio.c @@ -115,6 +115,10 @@ /* F23 : BP105_CTRL ==> PP1050_CTRL */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index b7ade2e..6dbfb69 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -47,6 +47,10 @@ /* F19 : NC */ PAD_NC(GPP_F19, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H12 : I2C7_SDA ==> UWB_SDA */ PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), /* H13 : I2C7_SCL ==> UWB_SCL */ diff --git a/src/mainboard/google/brya/variants/volmar/gpio.c b/src/mainboard/google/brya/variants/volmar/gpio.c index 8c13b2f..3f3a181 100644 --- a/src/mainboard/google/brya/variants/volmar/gpio.c +++ b/src/mainboard/google/brya/variants/volmar/gpio.c @@ -72,6 +72,10 @@ /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Gerrit-Change-Number: 61499 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add the Primary to Sideband bridge library
by Angel Pons (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Wonkyu Kim, John Zhao, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61283 ) Change subject: soc/intel/common: Add the Primary to Sideband bridge library ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Gerrit-Change-Number: 61283 Gerrit-PatchSet: 7 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 14:04:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45/raminit.c: Fix indent for 'if' statement
by Felix Held (Code Review) 31 Jan '22

31 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61474 ) Change subject: nb/intel/gm45/raminit.c: Fix indent for 'if' statement ...................................................................... nb/intel/gm45/raminit.c: Fix indent for 'if' statement Change-Id: I316ae56321da1183caefeac3163b8909d1a554b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61474 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/gm45/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d990497..e7663b9 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -32,8 +32,8 @@ { sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); if ((sysinfo->stepping > STEPPING_B3) && - (sysinfo->stepping != STEPPING_CONVERSION_A1)) - die("Unknown stepping.\n"); + (sysinfo->stepping != STEPPING_CONVERSION_A1)) + die("Unknown stepping.\n"); if (sysinfo->stepping <= STEPPING_B3) printk(BIOS_DEBUG, "Stepping %c%d\n", 'A' + sysinfo->stepping / 4, sysinfo->stepping % 4); else -- To view, visit https://review.coreboot.org/c/coreboot/+/61474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I316ae56321da1183caefeac3163b8909d1a554b1 Gerrit-Change-Number: 61474 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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