coreboot-gerrit January 2022

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Change in coreboot[master]: soc/intel/common/cse: Make cse_disable_mei_devices a public function
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Sridhar Siricilla, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61430 ) Change subject: soc/intel/common/cse: Make cse_disable_mei_devices a public function ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/61430/comment/09b37410_cad564ad PS3, Line 489: Function to make cse disable > nit: It disables cse Sorry, I don't think there is anything grammatically wrong here. Also read line #471, #474 etc. comment added here is intended to align with other functions in this file. Please suggest otherwise. -- To view, visit https://review.coreboot.org/c/coreboot/+/61430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Gerrit-Change-Number: 61430 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:44:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Subrata Banik (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Nico Huber, Sridhar Siricilla, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/bd49633b_8fec46d4 PS2, Line 666: is_cse_fw_update_enabled > >is there any restriction that on after FSI, we can't read the softstrap ? > > There is no point enabling the SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE since we don't want override native coreboot/SoC functionality/features (for example CSE FW update get triggered through debug flag) post FSI and Descriptor Region is Read-only. The intention of SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE for debug purposes. > BTW,SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE doesn't use soft strap area. It uses unused area (OEM section) as scratch pad. So, if I read it correctly there is no restriction while reading OEM sections prior or post FSI. hence, why we would like to introduce a Kconfig to guard the read operation which would eventually get drop during FSI. Any owner for ensuring the same across program ? 256 Bytes are reserved at the top of the Flash Descriptor for use by the OEM. The information stored by the OEM can only be written during the manufacturing process as the Flash Descriptor read/write permissions must be set to Read Only when the computer leaves the manufacturing floor. The PCH Flash controller does not read this information. FFh is suggested to reduce programming time. I could sense there are some underlying assumption which is not documented anything, either please raise a bug or write a .md file to clear out those assumptions. > > > Are you thinking if this region is locked and what value we will read, will that be always `1` (meaning CSE FW update is enable? in that case, you should opt for cse_fw_update_enable instead `disable`, so if softstrap is locked on production system, it will still read as `enable`/1) > > By default, OEM SECTION contains all 0XFF, empty area. If nothing is written to OEM section, when coreboot reads, it gets 0xFF. But, our override logic looks for 1 to control the specific CB/SoC feature. > > >Hence, guard is required. > > > >>Why? to protect it from reading ? > > No need to read as we want to withdraw the logic during FSI. > > >>Also, please note SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE will be used to control >>other SOC/coreboot features as well going forward. > > > >Any pointer about those *other SOC/coreboot features*, unless we have some >visibility it just a vision that you have and we are missing that might be. > > I will try to share the feature set we want to control through SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE flag by next week. I could sense there are some underlying assumption which is not documented anything, either please raise a bug or write a .md file to clear out those assumptions. File src/soc/intel/common/block/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/08ef2ae7_c0119f45 PS2, Line 28: cse_fw_update_disable > Assumption is, coreboot enables a feature by default and debug logic look for OEM SECTION if the feature is disabled or not. Hence, so identifier is chosen to reflect it's purpose. When OEM section indicates a feature has to be disabled, then override logic reverts the feature. I agree with everything expect the need for a config that meant to guard reading OEM section. You can achieve all you intended here without that additional Kconfig guard even. Also, if I understood it correctly the default value for OEM region is 0xFF so that way, unless someone override it for debug purpose, it would always read as `1` and consider `update is enable` and upon resetting the desire bit for debug purpose (to skip CSE update), the code logic would read it `0`. Not sure if it make sense to refer default `1` as CSE FW update disable. return pre_mem_debug.cse_fw_update_disable == 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:40:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Make cse_disable_mei_devices a public function
by Sridhar Siricilla (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61430 ) Change subject: soc/intel/common/cse: Make cse_disable_mei_devices a public function ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/61430/comment/cf85ef13_12362c1a PS3, Line 489: Function to make cse disable nit: It disables cse -- To view, visit https://review.coreboot.org/c/coreboot/+/61430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Gerrit-Change-Number: 61430 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:26:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 31 Jan '22

31 Jan '22

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Change in coreboot[master]: cpu/x86/Makefile.inc: Build smi_trigger on !HAVE_SMI_HANDLER
by Kyösti Mälkki (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59913 ) Change subject: cpu/x86/Makefile.inc: Build smi_trigger on !HAVE_SMI_HANDLER ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/Makefile.inc: https://review.coreboot.org/c/coreboot/+/59913/comment/15b6e260_85877139 PS3, Line 13: ramstage-y += backup_default_smm.c Since this is not under smm/ maybe move smi_trigger.c too? -- To view, visit https://review.coreboot.org/c/coreboot/+/59913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie57819b3d169311371a1caca83c9b0c796b46048 Gerrit-Change-Number: 59913 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:10:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Use PAD config macro to add lock support
by Meera Ravindranath (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, EricR Lai. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60320 ) Change subject: mb/google/brya: Use PAD config macro to add lock support ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60320/comment/4835a799_0c2e75e2 PS7, Line 13: TEST=Boot to OS, issue warm reboot and see no issue with any IP : enumeration > But are the corresponding GPIO pads actually locked? Or does the coreboot log contain a bunch of "gp […] No, they are locked. the gpio_lock_pad errors are resolved by the CL's that are merged below in the train. -- To view, visit https://review.coreboot.org/c/coreboot/+/60320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee Gerrit-Change-Number: 60320 Gerrit-PatchSet: 12 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:04:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/3ab67c19_4976edf7 PS2, Line 666: is_cse_fw_update_enabled >is there any restriction that on after FSI, we can't read the softstrap ? There is no point enabling the SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE since we don't want override native coreboot/SoC functionality/features (for example CSE FW update get triggered through debug flag) post FSI and Descriptor Region is Read-only. The intention of SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE for debug purposes. BTW,SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE doesn't use soft strap area. It uses unused area (OEM section) as scratch pad. > Are you thinking if this region is locked and what value we will read, will that be always `1` (meaning CSE FW update is enable? in that case, you should opt for cse_fw_update_enable instead `disable`, so if softstrap is locked on production system, it will still read as `enable`/1) By default, OEM SECTION contains all 0XFF, empty area. If nothing is written to OEM section, when coreboot reads, it gets 0xFF. But, our override logic looks for 1 to control the specific CB/SoC feature. >Hence, guard is required. > >>Why? to protect it from reading ? No need to read as we want to withdraw the logic during FSI. >>Also, please note SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE will be used to control >>other SOC/coreboot features as well going forward. > >Any pointer about those *other SOC/coreboot features*, unless we have some >visibility it just a vision that you have and we are missing that might be. I will try to share the feature set we want to control through SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE flag by next week. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 Jan 2022 09:00:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
by Cliff Huang (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Lance Zhao, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Thejaswani Putta, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61352 to look at the new patch set (#3). Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ...................................................................... soc/intel/common/block/pcie/rtd3: Add PM methods to the device. Add L23 enter/exit, modPHY power gate, and source clock control methods. DL23: method for L2/L3 entry. L23D: method for L2/L3 exit. PSD0: method for modPHY power gate. SRCK: method for enabling/disable source clock. These optional methods are to be used in the device ACPI to construct flows with root port's power management functions. Test: Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 111 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61352/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Gerrit-Change-Number: 61352 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apl: Use Kconfig to enable CseRbp
by Sean Rhodes (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Paul Menzel, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61282 to look at the new patch set (#6). Change subject: soc/intel/apl: Use Kconfig to enable CseRbp ...................................................................... soc/intel/apl: Use Kconfig to enable CseRbp This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is memory mapped and ensures SkipCseRbp UPD is guarded against this config. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103 --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/romstage.c 2 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/61282/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103 Gerrit-Change-Number: 61282 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/psp: add PSP command
by Jason Glenesk (Code Review) 31 Jan '22

31 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Name of user not set #1004133, Al Hirani, Rob Barnes, Fred Reitberger. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 ) Change subject: soc/amd/common/block/psp: add PSP command ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Can you update the description as […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Gerrit-Change-Number: 61462 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Name of user not set #1004133 Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 31 Jan 2022 07:47:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1004133 Gerrit-MessageType: comment

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coreboot-gerrit January 2022