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Change subject: soc/intel/common/cse: Implement HECI notify
......................................................................
Patch Set 15: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60405/comment/c7a28875_78f15ca3
PS15, Line 15: HECI device lists
Not sure what you mean here. Is it a "several device lists" of HECI devices? Ot do you mean a "single device list" of all HECI devices?
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/7b86c877_4347e8c0
PS15, Line 240: its
Should this be "it's" as yopu mean "it is " here?
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Name of user not set #1004133 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 )
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Can you update the description as
"Add PSP command to send SPL fuse command if PSP indicates SPL fusing is required"
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Change subject: soc/intel/common/cse: Rework heci_disable function
......................................................................
Patch Set 7: Code-Review+1
(2 comments)
File src/soc/intel/apollolake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/61431/comment/5897e989_fa2efe4d
PS7, Line 30: /* Reserved */
Still marked as reserved now that we now its functionality?
File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61431/comment/fbe2836d_fc2ed4a6
PS7, Line 2: disable_heci.c
Don't we usually have a separate line for every file to add to a stage?
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Hello Reka Norman,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/61497
to review the following change.
Change subject: mb/google/brya: Implement variant_cros_gpios() for nissa baseboard
......................................................................
mb/google/brya: Implement variant_cros_gpios() for nissa baseboard
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Change-Id: Ib49164cf51965228c65c6566b0711ae690b6cb50
---
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/61497/1
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
index 9d4f5a6..8a3ea0e 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
@@ -429,7 +429,8 @@
}
static const struct cros_gpio cros_gpios[] = {
- /* TODO */
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};
const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
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Change subject: mb/google/dedede/var/galtic: Generate SPD ID for Samsung K4U6E3S4AA-MGCR
......................................................................
Patch Set 1: Code-Review+2
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Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61480
to look at the new patch set (#3).
Change subject: cpu/x86/smm: Add SMM_LEGACY_ASEG
......................................................................
cpu/x86/smm: Add SMM_LEGACY_ASEG
Followup will allow use of PARALLEL_MP with SMM_ASEG so
some guards need to be adjusted.
Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785
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---
M src/cpu/amd/agesa/family15tn/Makefile.inc
M src/cpu/amd/smm/Makefile.inc
M src/cpu/x86/Kconfig
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/include/cpu/x86/smi_deprecated.h
M src/southbridge/intel/i82801dx/Makefile.inc
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801ix/Makefile.inc
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/smihandler.c
10 files changed, 19 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61480/3
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Change subject: mb/google/brya: Use PAD config macro to add lock support
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> @Meera/Maulik. can you please take care of this CL.
Yes, Subrata. let me rebase this.
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Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS5:
> Can you please go ahead to approve this PR since no objection from others? We want to chain this PR […]
@Angel, any further thoughts on this ?
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